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/axis_test_patern.sv
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////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
axis_test_patern |
#( |
N, // data bus width in bytes |
W, // word width in bytes |
WPB // number of words per beat |
) |
( |
axis_if axis_out, |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
// synthesis translate_off |
initial |
begin |
a_words_per_beat: assert(N == W * WPB) else $fatal; |
a_wpb: assert((WPB != 0) & ((WPB & (WPB - 1)) == 0)) else $fatal; // power of two |
end |
// synthesis translate_on |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// |
localparam W_LG = $clog2(W); |
|
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// -------------------------------------------------------------------- |
// |
reg [(W*8)-W_LG-1:0] counter; |
|
always_ff @(posedge aclk) |
if(~aresetn) |
counter <= 0; |
else if(axis_out.tready & axis_out.tvalid) |
counter <= counter + 1; |
|
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// -------------------------------------------------------------------- |
// counter test pattern |
wire [(N*8)-1:0] tp_counter; |
genvar j; |
|
generate |
for(j = 0; j < WPB; j++) |
begin: counting_test_pattern_gen |
wire [W_LG-1:0] index = j; |
assign tp_counter[j*W*8 +: W*8] = {counter, index}; |
end |
endgenerate |
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// -------------------------------------------------------------------- |
// |
wire [(N*8)-1:0] tp_mux_out = tp_counter; |
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// -------------------------------------------------------------------- |
// |
assign axis_out.tvalid = 1; |
assign axis_out.tdata = tp_mux_out; |
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// -------------------------------------------------------------------- |
// |
endmodule |
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