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  • This comparison shows the changes necessary to convert path
    /qaz_libs/trunk/axi4_stream_lib/src
    from Rev 49 to Rev 50
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Rev 49 → Rev 50

/data_to_axis_fsm.sv File deleted
/axis_flow_control.sv File deleted
/axis_to_memory.sv
0,0 → 1,129
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
axis_to_memory
#(
W, // data width in bits
A, // address width in bits
P = 1 // pipeline delay
)
(
axis_if axis_ar,
axis_if axis_r,
output wr,
output [A-1:0] addr,
output [W-1:0] din,
input [W-1:0] dout,
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
localparam CW = ($clog2(P) == 0) ? 1 : $clog2(P);
localparam D = 2 ** CW;
localparam UB = $clog2(D);
 
// --------------------------------------------------------------------
reg [P-1:0] pipeline;
wire ar = axis_ar.tready & axis_ar.tvalid;
wire rd_ready = pipeline[0];
wire bypass;
 
generate
if(P > 1) begin: pipeline_gen
always_ff @(posedge aclk)
if(~aresetn)
pipeline <= 0;
else
pipeline <= {ar, pipeline[P-1:1]};
end
else begin: min_pipeline_gen // P == 1
always_ff @(posedge aclk)
if(~aresetn)
pipeline <= 0;
else
pipeline <= ar;
end
endgenerate
 
// --------------------------------------------------------------------
wire wr_full;
wire [W-1:0] wr_data = dout;
wire wr_en = bypass ? 0 : rd_ready;
wire rd_empty;
wire [W-1:0] rd_data;
wire rd_en = axis_r.tready & axis_r.tvalid & ~bypass;
wire [UB:0] count;
 
sync_fifo #(W, D) fifo_i(.clk(aclk), .reset(~aresetn), .*);
 
// --------------------------------------------------------------------
// assign bypass = rd_empty & (count != 0) & rd_ready;
assign bypass = 0;
 
// // --------------------------------------------------------------------
// logic [$clog2($bits(pipeline)+1)-1:0] in_pipeline;
 
// always_comb begin
// in_pipeline = '0;
 
// foreach(pipeline[idx]) begin
// in_pipeline += pipeline[idx];
// end
// end
 
// --------------------------------------------------------------------
reg [$clog2($bits(pipeline)+1)-1:0] pipeline_count;
reg [$clog2($bits(pipeline)+1)-1:0] next_pipeline_count;
 
always_comb
case({rd_ready, ar})
2'b0_0: next_pipeline_count = pipeline_count;
2'b0_1: next_pipeline_count = pipeline_count + 1;
2'b1_0: next_pipeline_count = pipeline_count - 1;
2'b1_1: next_pipeline_count = pipeline_count;
endcase
 
always_ff @(posedge aclk)
if(~aresetn)
pipeline_count <= 0;
else
pipeline_count <= next_pipeline_count;
 
// --------------------------------------------------------------------
assign axis_ar.tready = (pipeline_count + count < D) | rd_en;
assign axis_r.tdata = bypass ? dout : rd_data;
assign axis_r.tlast = 1;
assign axis_r.tvalid = ~rd_empty | bypass;
 
// --------------------------------------------------------------------
assign wr = 0;
// assign addr = axis_ar.tdata;
 
// --------------------------------------------------------------------
endmodule

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