URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
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- This comparison shows the changes necessary to convert path
/qaz_libs/trunk/axi4_stream_lib
- from Rev 36 to Rev 37
- ↔ Reverse comparison
Rev 36 → Rev 37
/src/axis_catenate.sv
92,6 → 92,55
|
// -------------------------------------------------------------------- |
// |
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_bus[1:0](.*); |
genvar j; |
|
generate |
if(U_IS_EOP > -1) |
begin: u_is_eop_gen |
for(j = 0; j < U; j++) |
begin: for_tuser_gen |
if(j == U_IS_EOP) |
begin: choped_tuser_gen |
assign axis_bus[0].tuser[j] = 0; |
end |
else |
begin: tuser_gen |
assign axis_bus[0].tuser[j] = axis_in[0].tuser[j]; |
end |
end |
end |
else |
if(U_IS_EOP > -1) |
begin: tlast_gen |
assign axis_bus[0].tlast = axis_in[0].tlast; |
end |
else |
begin: choped_tlast_gen |
assign axis_bus[0].tlast = 0; |
end |
endgenerate |
|
|
// -------------------------------------------------------------------- |
// |
assign axis_in[0].tready = axis_bus[0].tready; |
assign axis_bus[0].tvalid = axis_in[0].tvalid; |
assign axis_bus[0].tdata = axis_in[0].tdata; |
assign axis_bus[0].tstrb = axis_in[0].tstrb; |
assign axis_bus[0].tkeep = axis_in[0].tkeep; |
assign axis_bus[0].tid = axis_in[0].tid; |
assign axis_bus[0].tdest = axis_in[0].tdest; |
|
|
// -------------------------------------------------------------------- |
// |
axis_alias |
axis_alias_i(axis_in[1], axis_bus[1]); |
|
|
// -------------------------------------------------------------------- |
// |
defparam axis_mux_i.N = N; // why are needed these for recursive modules? |
defparam axis_mux_i.I = I; |
defparam axis_mux_i.D = D; |
98,7 → 147,7
defparam axis_mux_i.U = U; |
axis_mux |
// axis_mux #(.N(N), .I(I), .D(D), .U(U)) |
axis_mux_i(.axis_in(axis_in), .*); |
axis_mux_i(.axis_in(axis_bus), .*); |
|
|
// -------------------------------------------------------------------- |
/src/axis_map_fifo.sv
29,12 → 29,12
axis_map_fifo |
#( |
N, // data bus width in bytes |
I = 0, // TID width |
D = 0, // TDEST width |
I = 1, // TID width |
D = 1, // TDEST width |
U = 1, // TUSER width |
USE_TSTRB = 0, // set to 1 to enable, 0 to disable |
USE_TKEEP = 0, // set to 1 to enable, 0 to disable |
USE_XID = 0, // set to 1 to enable, 0 to disable |
// USE_XID = 0, // set to 1 to enable, 0 to disable |
W = 0 |
) |
( |
50,9 → 50,9
// synthesis translate_off |
initial |
begin |
a_tid_unsuported: assert(I == 0) else $fatal; |
a_tdest_unsuported: assert(D == 0) else $fatal; |
a_xid_unsuported: assert(USE_XID == 0) else $fatal; |
// a_tid_unsuported: assert(I == 0) else $fatal; |
// a_tdest_unsuported: assert(D == 0) else $fatal; |
// a_xid_unsuported: assert(USE_XID == 0) else $fatal; |
a_w: assert(W == (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1) else $fatal; |
end |
// synthesis translate_on |
67,19 → 67,19
begin |
assign wr_data = |
{ |
axis_in.tdata, |
axis_in.tlast, |
axis_in.tuser, |
axis_in.tstrb, |
axis_in.tkeep |
axis_in.tkeep, |
axis_in.tdata |
}; |
assign |
{ |
axis_out.tdata, |
axis_out.tlast, |
axis_out.tuser, |
axis_out.tstrb, |
axis_out.tkeep |
axis_out.tkeep, |
axis_out.tdata |
} = rd_data; |
end |
else if(USE_TSTRB) |
86,17 → 86,17
begin |
assign wr_data = |
{ |
axis_in.tdata, |
axis_in.tlast, |
axis_in.tuser, |
axis_in.tstrb |
axis_in.tstrb, |
axis_in.tdata |
}; |
assign |
{ |
axis_out.tdata, |
axis_out.tlast, |
axis_out.tuser, |
axis_out.tstrb |
axis_out.tstrb, |
axis_out.tdata |
} = rd_data; |
end |
else if(USE_TKEEP) |
103,17 → 103,17
begin |
assign wr_data = |
{ |
axis_in.tdata, |
axis_in.tlast, |
axis_in.tuser, |
axis_in.tkeep |
axis_in.tkeep, |
axis_in.tdata |
}; |
assign |
{ |
axis_out.tdata, |
axis_out.tlast, |
axis_out.tuser, |
axis_out.tkeep |
axis_out.tkeep, |
axis_out.tdata |
} = rd_data; |
end |
else |
120,15 → 120,15
begin |
assign wr_data = |
{ |
axis_in.tdata, |
axis_in.tlast, |
axis_in.tuser |
axis_in.tuser, |
axis_in.tdata |
}; |
assign |
{ |
axis_out.tdata, |
axis_out.tlast, |
axis_out.tuser |
axis_out.tuser, |
axis_out.tdata |
} = rd_data; |
end |
end |
/src/axis_mux.sv
45,7 → 45,12
|
// -------------------------------------------------------------------- |
// |
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_mux_out(.*); |
defparam axis_mux_out.N = N; // why are needed these for recursive modules? |
defparam axis_mux_out.I = I; |
defparam axis_mux_out.D = D; |
defparam axis_mux_out.U = U; |
axis_if axis_mux_out(.*); |
// axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_mux_out(.*); |
|
assign axis_in[0].tready = select ? 0 : axis_mux_out.tready; |
assign axis_in[1].tready = select ? axis_mux_out.tready : 0; |
62,15 → 67,19
|
// -------------------------------------------------------------------- |
// |
defparam axis_register_slice_i.N = N; // why are needed these for recursive modules? |
defparam axis_register_slice_i.I = I; |
defparam axis_register_slice_i.D = D; |
defparam axis_register_slice_i.U = U; |
axis_register_slice |
#( |
.N(N), |
.I(I), |
.D(D), |
.U(U), |
.USE_TSTRB(0), |
.USE_TKEEP(0) |
) |
// #( |
// .N(N), |
// .I(I), |
// .D(D), |
// .U(U), |
// .USE_TSTRB(0), |
// .USE_TKEEP(0) |
// ) |
axis_register_slice_i |
( |
.axis_in(axis_mux_out), // slave |
/src/axis_switch_allocator.sv
46,21 → 46,6
|
// -------------------------------------------------------------------- |
// |
wire eop_in; |
|
axis_eop_set #(U_IS_EOP) |
axis_eop_set_i |
( |
.axis_in(axis_in), |
.tready(axis_switch_in.tready), |
.tvalid(axis_in.tvalid), |
.axis_eop(eop_in), |
.* |
); |
|
|
// -------------------------------------------------------------------- |
// |
wire eop_out_mux; |
reg [SA-1:0] select; |
|
82,6 → 67,21
|
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// -------------------------------------------------------------------- |
// |
wire eop_in; |
|
axis_eop_set #(U_IS_EOP) |
axis_eop_set_i |
( |
.axis_in(axis_in), |
.tready(axis_switch_in.tready), |
.tvalid(axis_in.tvalid), |
.axis_eop(eop_in), |
.* |
); |
|
|
// -------------------------------------------------------------------- |
// state machine binary definitions |
enum reg [3:0] |
{ |
116,9 → 116,9
next_state <= FLUSH; |
|
SWITCH: next_state <= SETTLE; |
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SETTLE: next_state <= ALLOT; // let select propagate to the switches |
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SETTLE: next_state <= ALLOT; // let select propagate to the switches |
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default: next_state <= ALLOT; |
endcase |
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