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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

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  • This comparison shows the changes necessary to convert path 
    /qaz_libs/trunk/basal/src
    from Rev 36 to Rev 37
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  •

Rev 36 → Rev 37

/RAM/bram_tdp.v
60,25 → 60,25
// --------------------------------------------------------------------
// Port A
always @(posedge a_clk)
if(a_wr)
begin
a_dout <= mem[a_addr];
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
a_dout <= a_din;
mem[a_addr] <= a_din;
end
else
a_dout <= mem[a_addr];
 
 
// --------------------------------------------------------------------
// Port B
always @(posedge b_clk)
if(b_wr)
begin
b_dout <= mem[b_addr];
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
b_dout <= b_din;
mem[b_addr] <= b_din;
end
else
b_dout <= mem[b_addr];
 
 
// --------------------------------------------------------------------
/synchronize/pulse_synchronizer.v
0,0 → 1,85
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
pulse_synchronizer
(
input in,
output out,
output busy,
input in_clk,
input in_reset,
input out_clk,
input out_reset
);
// --------------------------------------------------------------------
//
reg [1:0] in_s;
reg in_r;
wire in_w = in ? 1 : (in_s[1] ? 0 : in_r);
always @(posedge in_clk)
if(in_reset)
in_r <= 0;
else
in_r <= in_w;
 
// --------------------------------------------------------------------
//
reg [2:0] out_r;
always @(posedge out_clk)
if(out_reset)
out_r <= 0;
else
out_r <= {out_r[1:0], in_r};
 
// --------------------------------------------------------------------
//
always @(posedge in_clk)
if(in_reset)
in_s <= 0;
else
in_s <= {in_s[0], out_r[1]};
 
// --------------------------------------------------------------------
//
assign out = out_r[1] & ~out_r[2];
assign busy = in_s[1] | in_r;
// --------------------------------------------------------------------
//
endmodule
 

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