URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
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- This comparison shows the changes necessary to convert path
/qaz_libs/trunk/basal
- from Rev 49 to Rev 50
- ↔ Reverse comparison
Rev 49 → Rev 50
/sim/src/fifo_agent_pkg.sv
File deleted
/sim/src/fifo_bfm_pkg.sv
File deleted
/sim/src/legacy/fifo_agent_pkg.sv
0,0 → 1,102
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
package fifo_agent_pkg; |
|
// -------------------------------------------------------------------- |
// |
import fifo_bfm_pkg::*; |
|
class fifo_agent_class #(W = 8); |
|
fifo_bfm_class source_fifo; |
fifo_bfm_class sink_fifo; |
fifo_transaction_class tr_h; |
fifo_transaction_class clone_h; |
|
//-------------------------------------------------------------------- |
function |
new |
( |
virtual fifo_write_if #(.W(W)) source, |
virtual fifo_read_if #(.W(W)) sink |
); |
|
this.source_fifo = new(.source(source)); |
this.sink_fifo = new(.sink(sink)); |
this.tr_h = new(); |
|
endfunction: new |
|
|
// -------------------------------------------------------------------- |
// |
function void init; |
|
source_fifo.init("source", SOURCE); |
sink_fifo.init("sink", SINK); |
|
endfunction: init |
|
|
// -------------------------------------------------------------------- |
// |
task automatic |
start_q; |
|
source_fifo.fifo_write_q(); |
sink_fifo.fifo_read_q(); |
|
endtask: start_q |
|
|
// -------------------------------------------------------------------- |
// |
task automatic |
queue_random; |
|
if (!tr_h.randomize()) |
begin |
$display("^^^ %16.t | %m | ERROR! randomize error", $time); |
$stop; |
end |
|
clone_h = tr_h.clone(); |
source_fifo.fifo_tr_q.put(clone_h); |
sink_fifo.fifo_tr_q.put(clone_h); |
|
endtask: queue_random |
|
|
// -------------------------------------------------------------------- |
// |
|
endclass: fifo_agent_class |
|
endpackage: fifo_agent_pkg |
|
/sim/src/legacy/fifo_bfm_pkg.sv
0,0 → 1,380
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
package fifo_bfm_pkg; |
|
typedef enum |
{ |
SOURCE, |
SINK, |
BOTH |
} fifo_type_t; |
|
// -------------------------------------------------------------------- |
// |
class fifo_transaction_class; |
|
rand int data; |
rand int write_delay = 0; |
rand int read_delay = 0; |
|
constraint default_write_delay |
{ |
write_delay >= 0 && write_delay <= 4; |
write_delay dist {0 := 60, [1:4] :=40 }; |
} |
|
constraint default_read_delay |
{ |
read_delay >= 0 && read_delay <= 4; |
read_delay dist {0 := 60, [1:4] :=40 }; |
} |
|
|
// -------------------------------------------------------------------- |
// |
function void copy |
( |
ref fifo_transaction_class from |
); |
|
// $display("^^^ %16.t | %m", $time); |
|
this.data = from.data; |
this.write_delay = from.write_delay; |
this.read_delay = from.read_delay; |
|
endfunction: copy |
|
|
// -------------------------------------------------------------------- |
// |
extern virtual function fifo_transaction_class clone(); |
// virtual function fifo_transaction_class clone(); |
|
// $display("^^^ %16.t | %m", $time); |
|
// clone = new(); |
// clone.copy(this); |
// return(clone); |
|
// endfunction: clone |
|
|
// -------------------------------------------------------------------- |
// |
|
endclass: fifo_transaction_class |
|
|
// -------------------------------------------------------------------- |
// |
function fifo_transaction_class fifo_transaction_class::clone(); |
|
// $display("^^^ %16.t | %m", $time); |
|
clone = new(); |
clone.copy(this); |
|
endfunction: clone |
|
|
// -------------------------------------------------------------------- |
// |
class fifo_bfm_class #(W = 8); |
|
string fifo_name; |
fifo_type_t fifo_type; |
|
virtual fifo_write_if #(.W(W)) source = null; |
virtual fifo_read_if #(.W(W)) sink = null; |
fifo_transaction_class fifo_tr = new(); |
|
|
//-------------------------------------------------------------------- |
function new |
( |
virtual fifo_write_if #(.W(W)) source = null, |
virtual fifo_read_if #(.W(W)) sink = null |
); |
|
if(source != null) |
this.source = source; |
|
if(sink != null) |
this.sink = sink; |
|
endfunction: new |
|
|
// -------------------------------------------------------------------- |
// |
function void |
init |
( |
input string fifo_name, |
input fifo_type_t fifo_type |
); |
|
this.fifo_name = fifo_name; |
this.fifo_type = fifo_type; |
|
if(fifo_type == SOURCE) |
source.cb_s.wr_en <= 0; |
else if(fifo_type == SINK) |
sink.cb_s.rd_en <= 0; |
else if(fifo_type == BOTH) |
if((this.source == null) | (this.sink == null)) |
begin |
$display("^^^ %16.t | %m | ERROR! %s fifo_type == BOTH with null class", $time, fifo_type.name); |
$stop; |
end |
else |
begin |
source.cb_s.wr_en <= 0; |
sink.cb_s.rd_en <= 0; |
end |
else |
begin |
$display("^^^ %16.t | %m | ERROR! fifo_type %s is invalid", $time, fifo_type.name); |
$stop; |
end |
|
$display("^^^ %16.t | %m | initialization of %s for %s", $time, fifo_name, fifo_type.name); |
|
endfunction: init |
|
|
// -------------------------------------------------------------------- |
// |
task |
write |
( |
input [W-1:0] wr_data, |
input int write_delay = 0 |
); |
|
source.cb_s.wr_data <= wr_data; |
source.cb_s.wr_en <= 0; |
|
source.zero_cycle_delay(); |
|
if(write_delay != 0) |
repeat(write_delay) @(source.cb_s); |
|
@(source.cb_s iff (source.cb_s.full == 0)); |
// @(source.cb_s iff (~source.cb_s.full)); |
source.cb_s.wr_en <= 1; |
|
@(posedge source.clk); |
source.cb_s.wr_en <= 0; |
|
endtask: write |
|
|
// -------------------------------------------------------------------- |
// |
task |
fork_write |
( |
input [W-1:0] wr_data, |
input int write_delay = 0 |
); |
|
fork |
write(wr_data, write_delay); |
join_none |
|
#0; |
|
endtask: fork_write |
|
|
// -------------------------------------------------------------------- |
// |
mailbox #(int) rd_data_q = new(); |
|
task |
read |
( |
input int read_delay = 0 |
); |
|
sink.cb_s.rd_en <= 0; |
|
sink.zero_cycle_delay(); |
|
if(read_delay != 0) |
repeat(read_delay) @(sink.cb_s); |
|
@(sink.cb_s iff (sink.cb_s.empty == 0)); |
// @(sink.cb_s iff (~sink.cb_s.empty)); |
sink.cb_s.rd_en <= 1; |
|
@(posedge sink.clk); |
|
sink.cb_s.rd_en <= 0; |
|
rd_data_q.put(sink.cb_s.rd_data); |
|
endtask: read |
|
|
// -------------------------------------------------------------------- |
// |
task automatic |
fork_read |
( |
input int read_delay = 0 |
); |
|
fork |
read(read_delay); |
join_none |
|
#0; |
|
endtask: fork_read |
|
|
// -------------------------------------------------------------------- |
// |
mailbox #(fifo_transaction_class) fifo_tr_q; |
semaphore fifo_tr_q_semaphore = new(1); |
|
|
// -------------------------------------------------------------------- |
// |
event fifo_write_done; |
|
task automatic |
fifo_write_q; |
|
if((fifo_type != SOURCE) & (fifo_type == BOTH)) |
begin |
$display("^^^ %16.t | %m | ERROR! wrong fifo_type |", $time); |
return; |
end |
|
if(fifo_tr_q_semaphore.try_get() == 0) |
begin |
$display("^^^ %16.t | %m | ERROR! fifo_tr_q_semaphore.try_get() == 0 |", $time); |
return; |
end |
|
$display("^^^ %16.t | %m is active |", $time); |
|
this.fifo_tr_q = new(); |
|
fifo_write_fork : fork |
forever |
begin |
|
fifo_tr_q.get(fifo_tr); |
fork_write(fifo_tr.data, fifo_tr.write_delay); |
|
wait fork; |
|
->fifo_write_done; |
end |
join_none |
|
#0; |
|
endtask: fifo_write_q |
|
|
// -------------------------------------------------------------------- |
// |
fifo_transaction_class fifo_tr_clone; |
event fifo_read_done; |
logic [W - 1:0] rd_data; |
logic [W - 1:0] rd_result; |
int compare_result; |
int compare_errors = 0; |
|
task automatic |
fifo_read_q; |
|
if((fifo_type != SINK) & (fifo_type == BOTH)) |
begin |
$display("^^^ %16.t | %m | ERROR! wrong fifo_type |", $time); |
return; |
end |
|
|
if(fifo_tr_q_semaphore.try_get() == 0) |
begin |
$display("^^^ %16.t | %m | ERROR! fifo_tr_q_semaphore.try_get() == 0 |", $time); |
return; |
end |
|
$display("^^^ %16.t | %m is active |", $time); |
|
this.fifo_tr_q = new(); |
fifo_tr_clone = fifo_tr.clone(); |
|
fifo_read_q_fork : fork |
forever |
begin |
|
fifo_tr_q.get(fifo_tr); |
fork_read(fifo_tr.read_delay); |
|
wait fork; |
|
->fifo_read_done; |
|
rd_data_q.get(rd_result); |
rd_data = fifo_tr.data; |
|
if(rd_result != rd_data) |
begin |
$display("^^^ %16.t | %m | ERROR! rd_result != fifo_tr.data |", $time); |
$display("^^^ %16.t | %m | rd_result = %h |", $time, rd_result); |
$display("^^^ %16.t | %m | fifo_tr.data = %h |", $time, fifo_tr.data); |
end |
|
// compare_result = avf_in_frame.compare(8, f_h); |
// compare_errors += compare_result; |
|
end |
join_none |
|
#0; |
|
endtask: fifo_read_q |
|
|
// -------------------------------------------------------------------- |
// |
|
endclass: fifo_bfm_class |
|
endpackage: fifo_bfm_pkg |
|
/sim/tests/tb_tiny_async_fifo/tb_tiny_async_fifo.sv
File deleted
/sim/tests/tb_tiny_async_fifo/wip.do
File deleted
/sim/tests/tb_tiny_async_fifo/init_test.do
File deleted
/sim/tests/tb_tiny_async_fifo/the_test.sv
File deleted
/sim/tests/tb_tiny_async_fifo/sim.do
File deleted
/sim/tests/tb_tiny_sync_fifo/init_test.do
File deleted
/sim/tests/tb_tiny_sync_fifo/the_test.sv
File deleted
/sim/tests/tb_tiny_sync_fifo/sim.do
File deleted
/sim/tests/tb_tiny_sync_fifo/tb_tiny_sync_fifo.sv
File deleted
/sim/tests/tb_tiny_sync_fifo/wip.do
File deleted
/sim/tests/legacy/tb_tiny_async_fifo/init_test.do
0,0 → 1,33
# ------------------------------------ |
# |
# ------------------------------------ |
|
global env |
|
set env(ROOT_DIR) ../../../../.. |
set env(PROJECT_DIR) ../../.. |
set env(SIM_TARGET) fpga |
|
# load sim procedures |
do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do |
|
radix -hexadecimal |
|
make_lib work 1 |
|
sim_compile_all async_fifo |
sim_compile_all sim |
|
# simulation $root |
vlog $env(PROJECT_DIR)/sim/src/tb_tiny_async_fifo.sv |
|
# compile test last |
vlog ./the_test.sv |
|
# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top |
|
# run the sim |
sim_run_test |
|
|
|
/sim/tests/legacy/tb_tiny_async_fifo/sim.do
0,0 → 1,21
# |
# |
|
|
quit -sim |
|
# vsim opt_tb_top |
|
vsim -novopt work.tb_top |
# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top |
|
# vsim -voptargs="+acc=rn+/tb_top/dut" -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top |
# vsim -pli "C:/Xilinx/Vivado/2015.4/lib/win64.o/libxil_vsim.dll" -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top |
|
|
# # log all signals |
# log -r * |
|
# run -all |
|
|
/sim/tests/legacy/tb_tiny_async_fifo/tb_tiny_async_fifo.sv
0,0 → 1,122
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module tb_top(); |
|
// -------------------------------------------------------------------- |
// test bench clock & reset |
wire clk_200mhz; |
wire tb_clk = clk_200mhz; |
wire tb_rst; |
wire aclk = tb_clk; |
wire aresetn = ~tb_rst; |
|
tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst); |
|
// wire clk_100mhz; |
// tb_clk #(.PERIOD(10_000)) tb_100mhz_clk(clk_100mhz); |
|
|
// -------------------------------------------------------------------- |
// |
localparam W = 8; |
|
fifo_write_if #(.W(W)) source(clk_200mhz, tb_rst); |
fifo_read_if #(.W(W)) sink(clk_200mhz, tb_rst); |
|
|
// -------------------------------------------------------------------- |
// |
tiny_async_fifo |
dut(.*); |
|
|
// -------------------------------------------------------------------- |
// sim models |
// | | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ |
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
|
// -------------------------------------------------------------------- |
// |
// import fifo_bfm_pkg::*; |
|
// fifo_bfm_class bfm = new(source, sink); |
|
// initial |
// bfm.init("", BOTH); |
|
|
// -------------------------------------------------------------------- |
// |
import fifo_agent_pkg::*; |
|
fifo_agent_class bfm = new(source, sink); |
|
initial |
begin |
bfm.init(); |
bfm.start_q(); |
end |
|
|
|
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ |
// | | | | | | | | | | | | | | | | | |
// sim models |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// debug wires |
|
|
// -------------------------------------------------------------------- |
// test |
the_test test( tb_clk, tb_rst ); |
|
initial |
begin |
|
test.run_the_test(); |
|
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench done.", $time); |
$display("^^^---------------------------------"); |
|
$display("^^^---------------------------------"); |
|
$stop(); |
|
end |
|
endmodule |
|
|
|
/sim/tests/legacy/tb_tiny_async_fifo/the_test.sv
0,0 → 1,77
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`timescale 1ps/1ps |
|
|
module |
the_test( |
input tb_clk, |
input tb_rst |
); |
|
// -------------------------------------------------------------------- |
// |
int data; |
|
|
// -------------------------------------------------------------------- |
// |
task run_the_test; |
|
// -------------------------------------------------------------------- |
// insert test below |
// -------------------------------------------------------------------- |
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench begun.\n", $time); |
$display("^^^---------------------------------"); |
// -------------------------------------------------------------------- |
|
tb_top.tb.timeout_stop(1000ms); |
|
|
// -------------------------------------------------------------------- |
wait(~tb_rst); |
|
|
// -------------------------------------------------------------------- |
|
repeat(20) @(posedge tb_clk); |
|
repeat(100) tb_top.bfm.queue_random(); |
repeat(500) @(posedge tb_clk); |
|
|
// -------------------------------------------------------------------- |
// insert test above |
// -------------------------------------------------------------------- |
|
endtask |
|
|
endmodule |
|
/sim/tests/legacy/tb_tiny_async_fifo/wip.do
0,0 → 1,13
# |
|
|
vlog -f ../../libs/async_fifo_verilog/tiny_async_fifo.f |
# vlog -f ../../libs/sim_verilog/fifo_bfm.f |
|
# simulation $root |
vlog ../../src/tb_tiny_async_fifo.sv |
|
# compile test last |
vlog ./the_test.sv |
|
|
/sim/tests/legacy/tb_tiny_sync_fifo/init_test.do
0,0 → 1,33
# ------------------------------------ |
# |
# ------------------------------------ |
|
global env |
|
set env(ROOT_DIR) ../../../../.. |
set env(PROJECT_DIR) ../../.. |
set env(SIM_TARGET) fpga |
|
# load sim procedures |
do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do |
|
radix -hexadecimal |
|
make_lib work 1 |
|
sim_compile_all sync_fifo |
sim_compile_all sim |
|
# simulation $root |
vlog $env(PROJECT_DIR)/sim/src/tb_tiny_sync_fifo.sv |
|
# compile test last |
vlog ./the_test.sv |
|
# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top |
|
# run the sim |
sim_run_test |
|
|
|
/sim/tests/legacy/tb_tiny_sync_fifo/sim.do
0,0 → 1,21
# |
# |
|
|
quit -sim |
|
# vsim opt_tb_top |
|
vsim -novopt work.tb_top |
# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top |
|
# vsim -voptargs="+acc=rn+/tb_top/dut" -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top |
# vsim -pli "C:/Xilinx/Vivado/2015.4/lib/win64.o/libxil_vsim.dll" -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top |
|
|
# # log all signals |
# log -r * |
|
# run -all |
|
|
/sim/tests/legacy/tb_tiny_sync_fifo/tb_tiny_sync_fifo.sv
0,0 → 1,122
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module tb_top(); |
|
// -------------------------------------------------------------------- |
// test bench clock & reset |
wire clk_200mhz; |
wire tb_clk = clk_200mhz; |
wire tb_rst; |
wire aclk = tb_clk; |
wire aresetn = ~tb_rst; |
|
tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst); |
|
// wire clk_100mhz; |
// tb_clk #(.PERIOD(10_000)) tb_100mhz_clk(clk_100mhz); |
|
|
// -------------------------------------------------------------------- |
// |
localparam W = 8; |
|
fifo_write_if #(.W(W)) source(clk_200mhz, tb_rst); |
fifo_read_if #(.W(W)) sink(clk_200mhz, tb_rst); |
|
|
// -------------------------------------------------------------------- |
// |
tiny_sync_fifo |
dut(.*); |
|
|
// -------------------------------------------------------------------- |
// sim models |
// | | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ |
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
|
// -------------------------------------------------------------------- |
// |
// import fifo_bfm_pkg::*; |
|
// fifo_bfm_class bfm = new(source, sink); |
|
// initial |
// bfm.init("", BOTH); |
|
|
// -------------------------------------------------------------------- |
// |
import fifo_agent_pkg::*; |
|
fifo_agent_class bfm = new(source, sink); |
|
initial |
begin |
bfm.init(); |
bfm.start_q(); |
end |
|
|
|
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ |
// | | | | | | | | | | | | | | | | | |
// sim models |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// debug wires |
|
|
// -------------------------------------------------------------------- |
// test |
the_test test( tb_clk, tb_rst ); |
|
initial |
begin |
|
test.run_the_test(); |
|
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench done.", $time); |
$display("^^^---------------------------------"); |
|
$display("^^^---------------------------------"); |
|
$stop(); |
|
end |
|
endmodule |
|
|
|
/sim/tests/legacy/tb_tiny_sync_fifo/the_test.sv
0,0 → 1,88
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`timescale 1ps/1ps |
|
|
module |
the_test( |
input tb_clk, |
input tb_rst |
); |
|
// -------------------------------------------------------------------- |
// |
int data; |
|
|
// -------------------------------------------------------------------- |
// |
task run_the_test; |
|
// -------------------------------------------------------------------- |
// insert test below |
// -------------------------------------------------------------------- |
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench begun.\n", $time); |
$display("^^^---------------------------------"); |
// -------------------------------------------------------------------- |
|
tb_top.tb.timeout_stop(1000ms); |
|
|
// -------------------------------------------------------------------- |
wait(~tb_rst); |
|
|
// -------------------------------------------------------------------- |
|
repeat(10) @(posedge tb_clk); |
|
repeat(100) tb_top.bfm.queue_random(); |
|
|
// tb_top.bfm.write(8'h22, 0); |
// tb_top.bfm.write(8'haa, 0); |
// tb_top.bfm.read(10); |
// tb_top.bfm.write(8'hff, 5); |
// tb_top.bfm.read(0); |
// tb_top.bfm.read(0); |
// tb_top.bfm.write(8'h11, 1); |
|
|
repeat(1000) @(posedge tb_clk); |
|
|
// -------------------------------------------------------------------- |
// insert test above |
// -------------------------------------------------------------------- |
|
endtask |
|
|
endmodule |
|
/sim/tests/legacy/tb_tiny_sync_fifo/wip.do
0,0 → 1,13
# |
|
|
vlog -f ../../libs/FPGA_verilog/tiny_fifo.f |
vlog -f ../../libs/sim_verilog/fifo_bfm.f |
|
# simulation $root |
vlog ../../src/tb_tiny_sync_fifo.sv |
|
# compile test last |
vlog ./the_test.sv |
|
|
/src/FIFOs/tiny_async_fifo.sv
File deleted
/src/FIFOs/sync_fifo.sv
25,7 → 25,6
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module |
sync_fifo |
#( |
37,11 → 36,9
output wr_full, |
input [W-1:0] wr_data, |
input wr_en, |
|
output rd_empty, |
output [W-1:0] rd_data, |
input rd_en, |
|
output [UB:0] count, |
input clk, |
input reset |
48,12 → 45,21
); |
|
// -------------------------------------------------------------------- |
// |
generate |
begin: fifo_gen |
if(D == 2) |
begin |
assign count = 0; |
reg [UB:0] count_r; |
assign count = count_r; |
|
always_comb |
case({wr_full, rd_empty}) |
2'b0_0: count_r = 1; |
2'b0_1: count_r = 0; |
2'b1_0: count_r = 2; |
2'b1_1: count_r = 'x; // should never happen |
endcase |
|
tiny_sync_fifo #(.W(W)) |
tiny_sync_fifo_i(.*); |
end |
73,7 → 79,6
end |
endgenerate |
|
|
// -------------------------------------------------------------------- |
// synthesis translate_off |
always_ff @(posedge clk) |
85,9 → 90,5
// synthesis translate_on |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
|
/src/misc/barrel_shifter.v
0,0 → 1,73
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2019 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
barrel_shifter |
#( |
parameter W = 32, |
parameter D = W, |
parameter UB = $clog2(D) |
) |
( |
input direction, // right = 0, left = 1 |
input op, // logical = 0, arithmetic = 1; left arithmetic not supported |
input [UB-1:0] amount, // 0 not allowed |
input [W-1:0] data_in, |
output [W-1:0] data_out, |
|
input reset, |
input clk |
); |
|
// -------------------------------------------------------------------- |
wire [W-1:0] out [UB:0]; |
wire shift_in = direction & op ? data_in[W-1] : 0; |
genvar j, k; |
|
// -------------------------------------------------------------------- |
generate |
for(k = 0; k < D; k = k + 1) |
begin : reversal |
assign out[5][k] = direction ? data_in[k] : data_in[D - 1 - k]; |
assign data_out[k] = direction ? out[0][k] : out[0][D - 1 - k]; |
end |
endgenerate |
|
// -------------------------------------------------------------------- |
generate |
for(j = 0; j < UB; j = j + 1) |
for(k = 0; k < D; k = k + 1) |
begin : shifter |
if(k > D - 1 - (2**j)) |
assign out[j][k] = amount[j] ? shift_in : out[j+1][k]; |
else |
assign out[j][k] = amount[j] ? out[j+1][k + (2**j)] : out[j+1][k]; |
end |
endgenerate |
|
// -------------------------------------------------------------------- |
endmodule |