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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

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  • This comparison shows the changes necessary to convert path 
    /qaz_libs/trunk/camera_link
    from Rev 25 to Rev 27
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Rev 25 → Rev 27

/sim/src/camera_link_clk.v
0,0 → 1,78
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 10ps/1ps
 
 
module camera_link_clk
(
input clk_in,
 
output reg [3:0] clk_7x_index,
output clk_out_7x,
output clock_good,
 
input reset
);
 
// --------------------------------------------------------------------
//
clock_mult
#( .MULT(7) )
clk_out_7x_i
(
.clock_in(clk_in),
.clock_out(clk_out_7x),
.clock_good(clock_good),
 
.reset(reset)
);
 
 
// --------------------------------------------------------------------
//
wire delayed_clk_in;
 
assign #1 delayed_clk_in = clk_in;
 
wire clk_in_rise = (delayed_clk_in == 1'b0) & (clk_in == 1'b1);
 
always @(posedge clk_out_7x)
begin
if(clk_in_rise)
clk_7x_index <= 5;
else if( clk_7x_index >= 6 )
clk_7x_index <= 0;
else
clk_7x_index <= clk_7x_index + 1;
end
 
 
endmodule
 
 
 
/sim/src/cl_area_scan_checker.v
0,0 → 1,155
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module cl_area_scan_checker
(
input cl_fval,
input cl_lval,
input cl_dval,
input [63:0] cl_data,
input cl_clk,
 
input cl_reset
);
 
 
// --------------------------------------------------------------------
//
wire [13:0] cl_pixel_counter;
wire [15:0] cl_frame_x;
wire [15:0] cl_frame_y;
wire cl_fval_fall;
wire cl_fval_rise;
wire cl_lval_fall;
wire cl_lval_rise;
wire cl_data_en;
reg cl_base_format = 0;
reg cl_full_format = 0;
 
cl_util
util
(
.cl_fval(cl_fval),
.cl_lval(cl_lval),
.cl_dval(cl_dval),
.cl_data(cl_data),
.cl_clk(cl_clk),
 
.cl_base_format(cl_base_format),
.cl_full_format(cl_full_format),
 
.cl_fval_fall(cl_fval_fall),
.cl_fval_rise(cl_fval_rise),
.cl_lval_fall(cl_lval_fall),
.cl_lval_rise(cl_lval_rise),
.cl_data_en(cl_data_en),
 
.cl_pixel_counter(cl_pixel_counter),
.cl_frame_x(cl_frame_x),
.cl_frame_y(cl_frame_y),
 
.cl_reset(cl_reset)
);
 
 
// --------------------------------------------------------------------
//
 
task init;
input integer fpa_outputs;
begin
 
cl_base_format = 0;
cl_full_format = 0;
 
if( (fpa_outputs == 1) | (fpa_outputs == 2) )
begin
$display( "-!- %16.t | %m: FPA with %0d outputs. Assuming Base CameraLink Format", $time, fpa_outputs );
cl_base_format = 1;
end
else if( (fpa_outputs == 4) | (fpa_outputs == 8) )
begin
$display( "-!- %16.t | %m: FPA with %0d outputs. Assuming Full CameraLink Format", $time, fpa_outputs );
cl_full_format = 1;
end
else
begin
$display( "-!- %16.t | %m: FPA with %0d not supported.", $time, fpa_outputs );
$stop();
end
 
end
endtask
 
task disable_checker;
begin
 
cl_base_format = 0;
cl_full_format = 0;
 
end
endtask
 
 
// --------------------------------------------------------------------
//
task checker;
input integer pixel_counter;
begin
 
if( cl_base_format )
begin
if( cl_data[15:0] != pixel_counter )
begin
log.inc_fail_count;
$display( "-!- %16.t | %m: data error at pixel 0x%4x. Pixel is 0x%4x and should be 0x%4x", $time, pixel_counter, cl_data[15:0], pixel_counter );
end
end
else if( cl_full_format )
begin
if( (cl_data[15:0] != pixel_counter) | (cl_data[31:16] != (pixel_counter + 1)) | (cl_data[47:32] != (pixel_counter + 2)) | (cl_data[63:48] != (pixel_counter + 3)) )
begin
log.inc_fail_count;
$display( "-!- %16.t | %m: data error somewhere between pixel 0x%4x and 0x%4x.", $time, pixel_counter, pixel_counter + 4 );
end
end
 
end
endtask
 
 
// --------------------------------------------------------------------
//
always @(negedge cl_clk)
if( cl_data_en )
checker( cl_pixel_counter );
 
 
 
endmodule
 
/sim/src/cl_line_scan_checker.v
0,0 → 1,168
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module cl_line_scan_checker
(
input cl_fval,
input cl_lval,
input cl_dval,
input [63:0] cl_data,
input cl_clk,
 
input cl_reset
);
 
// --------------------------------------------------------------------
//
wire [13:0] cl_pixel_counter;
wire [15:0] cl_frame_x;
wire [15:0] cl_frame_y;
wire cl_fval_fall;
wire cl_fval_rise;
wire cl_lval_fall;
wire cl_lval_rise;
wire cl_data_en;
reg cl_base_format = 0;
reg cl_full_format = 0;
 
cl_util
util
(
.cl_fval(cl_fval),
.cl_lval(cl_lval),
.cl_dval(cl_dval),
.cl_data(cl_data),
.cl_clk(cl_clk),
 
.cl_base_format(cl_base_format),
.cl_full_format(cl_full_format),
 
.cl_fval_fall(cl_fval_fall),
.cl_fval_rise(cl_fval_rise),
.cl_lval_fall(cl_lval_fall),
.cl_lval_rise(cl_lval_rise),
.cl_data_en(cl_data_en),
 
.cl_pixel_counter(cl_pixel_counter),
.cl_frame_x(cl_frame_x),
.cl_frame_y(cl_frame_y),
 
.cl_reset(cl_reset)
);
 
 
// --------------------------------------------------------------------
//
reg [15:0] cl_base_data_lenght;
reg [15:0] cl_base_eod_index;
reg [15:0] cl_base_id_index;
 
task init;
input integer fpa_outputs;
input reg [15:0] data_lenght;
input reg [15:0] eod_index;
input reg [15:0] id_index;
begin
 
cl_base_format = 0;
cl_full_format = 0;
if( (fpa_outputs == 1) | (fpa_outputs == 2) )
begin
$display( "-!- %16.t | %m: FPA with %0d outputs. Assuming Base CameraLink Format", $time, fpa_outputs );
cl_base_format = 1;
end
else if( (fpa_outputs == 4) | (fpa_outputs == 8) )
begin
$display( "-!- %16.t | %m: FPA with %0d outputs. Assuming Full CameraLink Format", $time, fpa_outputs );
cl_full_format = 1;
end
else
begin
$display( "-!- %16.t | %m: FPA with %0d not supported.", $time, fpa_outputs );
$stop();
end
 
cl_base_data_lenght = data_lenght;
cl_base_eod_index = eod_index;
cl_base_id_index = id_index;
 
end
endtask
task disable_checker;
begin
 
cl_base_format = 0;
cl_full_format = 0;
 
end
endtask
 
 
// --------------------------------------------------------------------
//
task checker;
input integer frame_x;
begin
 
if( frame_x < cl_base_data_lenght )
if( cl_data[15:0] != frame_x )
begin
log.inc_fail_count;
$display( "-!- %16.t | %m: data error at pixel %x. Pixel is %x and should be %x", $time, frame_x, cl_data[15:0], frame_x );
end
else if((cl_base_eod_index == frame_x) | ( (cl_base_eod_index + 1) == frame_x ))
if(cl_data[15:0] != FPA_EOD)
begin
log.inc_fail_count;
$display( "-!- %16.t | %m: EOD error at pixel %x.", $time, frame_x );
end
else if( cl_base_id_index <= frame_x )
if( cl_data[15:0] != ( (frame_x - cl_base_id_index) + 16'h0e00 ) )
begin
log.inc_fail_count;
$display( "-!- %16.t | %m: EOD error at pixel %x.", $time, frame_x );
end
 
end
endtask
 
 
// --------------------------------------------------------------------
//
always @(negedge cl_clk)
if( cl_data_en )
checker( cl_frame_x );
 
 
 
endmodule
 
 
 
/sim/src/cl_util.v
0,0 → 1,145
//
//
//
 
 
module cl_util
(
input cl_fval,
input cl_lval,
input cl_dval,
input [63:0] cl_data,
input cl_clk,
 
input cl_base_format,
input cl_full_format,
 
output cl_fval_fall,
output cl_fval_rise,
output cl_lval_fall,
output cl_lval_rise,
output cl_data_en,
 
output reg [13:0] cl_pixel_counter,
output reg [15:0] cl_frame_x,
output reg [15:0] cl_frame_y,
 
input cl_reset
);
 
// --------------------------------------------------------------------
//
task get_frames;
input integer count;
begin
 
repeat(count) @(negedge cl_fval);
 
$display( "-!- %16.t | %m: got %0d frames.", $time, count );
 
end
endtask
 
 
// --------------------------------------------------------------------
// cl_fval & cl_lval edge detector
reg cl_fval_r;
assign cl_fval_fall = ~cl_fval & cl_fval_r;
assign cl_fval_rise = cl_fval & ~cl_fval_r;
 
always @(posedge cl_clk)
cl_fval_r <= cl_fval;
 
reg cl_lval_r;
assign cl_lval_fall = ~cl_lval & cl_lval_r;
assign cl_lval_rise = cl_lval & ~cl_lval_r;
 
always @(posedge cl_clk)
cl_lval_r <= cl_lval;
 
 
// --------------------------------------------------------------------
// pixel counter
always @(posedge cl_clk)
if( ~cl_fval | cl_reset | (cl_pixel_counter > 14'h3ff0) )
cl_pixel_counter <= 0;
else if( cl_data_en )
if( cl_base_format )
cl_pixel_counter <= cl_pixel_counter + 1;
else if( cl_full_format )
cl_pixel_counter <= cl_pixel_counter + 4;
 
 
// --------------------------------------------------------------------
// frame x coordinate
always @(posedge cl_clk)
if( ~cl_fval | ~cl_lval | cl_reset )
cl_frame_x <= 0;
else if( cl_data_en )
if( cl_base_format )
cl_frame_x <= cl_frame_x + 1;
else if( cl_full_format )
cl_frame_x <= cl_frame_x + 4;
 
 
// --------------------------------------------------------------------
// frame y coordinate
always @(posedge cl_clk)
if( ~cl_fval | cl_reset )
cl_frame_y <= 0;
else if( cl_lval_fall )
cl_frame_y <= cl_frame_y + 1;
 
 
// --------------------------------------------------------------------
//
integer cl_line_width;
integer cl_height;
integer cl_width;
 
always @(posedge cl_clk)
if( cl_fval_rise | cl_reset )
cl_line_width <= 0;
else if( cl_lval_fall )
cl_line_width <= cl_frame_x;
 
always @(posedge cl_clk)
if( cl_fval_fall )
cl_height <= cl_frame_y;
 
always @(posedge cl_clk)
if( cl_fval_fall )
cl_width <= cl_line_width;
 
task display_frame_size;
begin
 
$display( "-!- %16.t | %m: last frame size was %0dX%0d.", $time, cl_width, cl_height );
 
end
endtask
 
task validate_frame_size;
input integer width;
input integer height;
begin
 
if( (height != cl_height) | (width != cl_width) )
begin
log.inc_fail_count;
$display( "-!- %16.t | %m: last frame size should be %0dX%0d but was %0dX%0d", $time, width, height, cl_width, cl_height );
end
 
end
endtask
 
 
// --------------------------------------------------------------------
// outputs
assign cl_data_en = cl_dval & cl_lval & cl_fval;
 
 
endmodule
 
 
 
/sim/src/tb_channel_link_rx_if.sv
0,0 → 1,167
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
interface
tb_channel_link_rx_if
(
input [3:0] p,
input [3:0] n,
input [4:0] invert_mux,
input reset,
input clk_p,
input clk_n
);
// --------------------------------------------------------------------
//
timeunit 1ps / 1ps;
time clk_period = 0;
time clk_7x_period = 0;
time strobe_delay = 0;
 
// --------------------------------------------------------------------
//
int bit_index;
logic clk_7x;
wire tx_clk = invert_mux[4] ? ~clk_p : clk_p;
// --------------------------------------------------------------------
//
default clocking cb @(posedge tx_clk);
input p;
input n;
input reset;
endclocking
 
 
// --------------------------------------------------------------------
//
localparam B = 7;
 
// --------------------------------------------------------------------
//
task
generate_clocks
(
time clk_7x_period,
time strobe_delay
);
 
bit_index = 5;
forever
@(cb)
begin
#strobe_delay;
clk_7x <= 1;
 
generate_clk_7x_fork : fork
begin
repeat((B * 2) - 1)
begin
#(clk_7x_period / 2);
clk_7x <= ~clk_7x;
if(clk_7x == 1)
if(bit_index == 6)
bit_index = 0;
else
bit_index++;
end
end
join_none
 
end
 
endtask: generate_clocks
// --------------------------------------------------------------------
//
logic [6:0] rx_in [4];
 
always @(posedge clk_7x)
begin
rx_in[3][bit_index] <= invert_mux[3] ? ~p[3] : p[3];
rx_in[2][bit_index] <= invert_mux[2] ? ~p[2] : p[2];
rx_in[1][bit_index] <= invert_mux[1] ? ~p[1] : p[1];
rx_in[0][bit_index] <= invert_mux[0] ? ~p[0] : p[0];
end
// --------------------------------------------------------------------
//
logic [27:0] rx_data;
 
always @(posedge clk_7x)
if(bit_index == 6)
begin
// 6 5 4 3 2 1 0
{rx_data[27], rx_data[ 5], rx_data[10], rx_data[11], rx_data[16], rx_data[17], rx_data[23]} <= {invert_mux[3] ? ~p[3] : p[3], rx_in[3][5:0]};
{rx_data[19], rx_data[20], rx_data[21], rx_data[22], rx_data[24], rx_data[25], rx_data[26]} <= {invert_mux[2] ? ~p[2] : p[2], rx_in[2][5:0]};
{rx_data[ 8], rx_data[ 9], rx_data[12], rx_data[13], rx_data[14], rx_data[15], rx_data[18]} <= {invert_mux[1] ? ~p[1] : p[1], rx_in[1][5:0]};
{rx_data[ 0], rx_data[ 1], rx_data[ 2], rx_data[ 3], rx_data[ 4], rx_data[ 6], rx_data[ 7]} <= {invert_mux[0] ? ~p[0] : p[0], rx_in[0][5:0]};
end
// --------------------------------------------------------------------
//
wire dval = rx_data[26];
wire fval = rx_data[25];
wire lval = rx_data[24];
wire spare = rx_data[23];
wire [7:0] port_a_d_g = {rx_data[5], rx_data[27], rx_data[6], rx_data[4:0]};
wire [7:0] port_b_e_h = {rx_data[11], rx_data[10], rx_data[14:12], rx_data[9:7]};
wire [7:0] port_c_f = {rx_data[17:16], rx_data[22:18], rx_data[15]};
// --------------------------------------------------------------------
//
task
init_clocks;
 
time clk_rise_t;
@(cb iff ~reset);
clk_rise_t = $time;
 
@(cb iff ~reset);
clk_period = $time - clk_rise_t;
clk_7x_period = clk_period / B;
strobe_delay = clk_7x_period / 2;
 
$display("^^^ %16.t | %m | clk_period = %t, ", $time, clk_period);
$display("^^^ %16.t | %m | clk_7x_period = %t", $time, clk_7x_period);
$display("^^^ %16.t | %m | strobe_delay = %t", $time, strobe_delay);
 
generate_clocks_fork : fork
generate_clocks(clk_7x_period, strobe_delay);
join_none
 
endtask: init_clocks
 
 
// --------------------------------------------------------------------
//
initial
begin
wait(~reset);
#500ns;
init_clocks();
end
// --------------------------------------------------------------------
//
 
endinterface
 
/src/camera_link.v
0,0 → 1,119
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module camera_link
(
input [3:0] x_data_in,
input x_clk,
input [3:0] y_data_in,
input y_clk,
input [3:0] z_data_in,
input z_clk,
 
input reset
);
 
// --------------------------------------------------------------------
//
wire [27:0] x_data_out;
wire x_dval = x_data_out[26];
wire x_fval = x_data_out[25];
wire x_lval = x_data_out[24];
wire x_spare = x_data_out[23];
channel_link
i_channel_link_x
(
.clk_in(x_clk),
.data_in(x_data_in),
.data_out(x_data_out),
.reset(reset)
);
 
 
// --------------------------------------------------------------------
//
wire [27:0] y_data_out;
wire y_dval = y_data_out[26];
wire y_fval = y_data_out[25];
wire y_lval = y_data_out[24];
wire y_spare = y_data_out[23];
channel_link
i_channel_link_y
(
.clk_in(y_clk),
.data_in(y_data_in),
.data_out(y_data_out),
.reset(reset)
);
 
 
// --------------------------------------------------------------------
//
wire [27:0] z_data_out;
wire z_dval = z_data_out[26];
wire z_fval = z_data_out[25];
wire z_lval = z_data_out[24];
wire z_spare = z_data_out[23];
channel_link
i_channel_link_z
(
.clk_in(z_clk),
.data_in(z_data_in),
.data_out(z_data_out),
.reset(reset)
);
 
 
// --------------------------------------------------------------------
//
wire [7:0] cl_port_a = { x_data_out[5], x_data_out[27], x_data_out[6], x_data_out[4:0] };
wire [7:0] cl_port_b = { x_data_out[11], x_data_out[10], x_data_out[14:12], x_data_out[9:7] };
wire [7:0] cl_port_c = { x_data_out[17:16], x_data_out[22:18], x_data_out[15] };
wire [7:0] cl_port_d = { y_data_out[5], y_data_out[27], y_data_out[6], y_data_out[4:0] };
wire [7:0] cl_port_e = { y_data_out[11], y_data_out[10], y_data_out[14:12], y_data_out[9:7] };
wire [7:0] cl_port_f = { y_data_out[17:16], y_data_out[22:18], y_data_out[15] };
wire [7:0] cl_port_g = { z_data_out[5], z_data_out[27], z_data_out[6], z_data_out[4:0] };
wire [7:0] cl_port_h = { z_data_out[11], z_data_out[10], z_data_out[14:12], z_data_out[9:7] };
 
wire [13:0] fpa_pixel_0 = { cl_port_a[5:0], cl_port_b };
wire [13:0] fpa_pixel_1 = { cl_port_c[5:0], cl_port_d };
wire [13:0] fpa_pixel_2 = { cl_port_e[5:0], cl_port_f };
wire [13:0] fpa_pixel_3 = { cl_port_g[5:0], cl_port_h };
 
endmodule
 
 
 
/src/camera_link_if.sv
0,0 → 1,118
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
interface
camera_link_if
(
input reset,
input clk_7x,
input clk
);
wire frame_valid;
wire line_valid;
wire data_valid;
wire [7:0] port_a;
wire [7:0] port_b;
wire [7:0] port_c;
wire [7:0] port_d;
wire [7:0] port_e;
wire [7:0] port_f;
wire [7:0] port_g;
wire [7:0] port_h;
// --------------------------------------------------------------------
//
default clocking cb @(posedge clk iff ~reset);
input reset;
input clk;
inout port_a;
inout port_b;
inout port_c;
inout port_d;
inout port_e;
inout port_f;
inout port_g;
inout port_h;
endclocking
 
 
// --------------------------------------------------------------------
//
modport
camera
(
input reset,
input clk_7x,
input clk,
output data_valid,
output frame_valid,
output line_valid,
output port_a,
output port_b,
output port_c,
output port_d,
output port_e,
output port_f,
output port_g,
output port_h,
clocking cb
);
// --------------------------------------------------------------------
//
modport
frame_grabber
(
input reset,
input clk_7x,
input clk,
input data_valid,
input frame_valid,
input line_valid,
input port_a,
input port_b,
input port_c,
input port_d,
input port_e,
input port_f,
input port_g,
input port_h,
clocking cb
);
// --------------------------------------------------------------------
//
endinterface
 
 
/src/channel_link.v
0,0 → 1,111
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module channel_link
(
input clk_in,
input [3:0] data_in,
output reg [27:0] data_out,
input reset
);
 
// --------------------------------------------------------------------
//
 
wire [3:0] clk_7x_index;
wire clkout_7x;
camera_link_clk i_camera_link_clk
(
.clk_in(clk_in),
.clk_7x_index(clk_7x_index),
.clk_out_7x(clkout_7x),
.clock_good(),
.reset(reset)
);
 
// --------------------------------------------------------------------
//
reg payload [6:0] [3:0];
 
always @(negedge clkout_7x)
begin
payload[clk_7x_index][0] <= data_in[0];
payload[clk_7x_index][1] <= data_in[1];
payload[clk_7x_index][2] <= data_in[2];
payload[clk_7x_index][3] <= data_in[3];
end
 
 
// --------------------------------------------------------------------
//
always @(posedge clkout_7x)
if( clk_7x_index == 6 )
begin
data_out[0] <= payload[6][0];
data_out[1] <= payload[5][0];
data_out[2] <= payload[4][0];
data_out[3] <= payload[3][0];
data_out[4] <= payload[2][0];
data_out[6] <= payload[1][0];
data_out[7] <= payload[0][0];
 
data_out[8] <= payload[6][1];
data_out[9] <= payload[5][1];
data_out[12] <= payload[4][1];
data_out[13] <= payload[3][1];
data_out[14] <= payload[2][1];
data_out[15] <= payload[1][1];
data_out[18] <= payload[0][1];
 
data_out[19] <= payload[6][2];
data_out[20] <= payload[5][2];
data_out[21] <= payload[4][2];
data_out[22] <= payload[3][2];
data_out[24] <= payload[2][2];
data_out[25] <= payload[1][2];
data_out[26] <= payload[0][2];
 
data_out[27] <= payload[6][3];
data_out[5] <= payload[5][3];
data_out[10] <= payload[4][3];
data_out[11] <= payload[3][3];
data_out[16] <= payload[2][3];
data_out[17] <= payload[1][3];
data_out[23] <= payload[0][3];
end
 
 
endmodule
 
 
 
/src/channel_link_if.sv
0,0 → 1,74
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
interface
channel_link_if;
wire [3:0] p;
wire [3:0] n;
wire clk_p;
wire clk_n;
// --------------------------------------------------------------------
//
default clocking cb @(posedge clk_p);
inout p;
inout n;
endclocking
 
 
// --------------------------------------------------------------------
//
modport
out
(
output p,
output n,
clocking cb
);
// --------------------------------------------------------------------
//
modport
in
(
input p,
input n,
clocking cb
);
// --------------------------------------------------------------------
//
endinterface
 
 

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