URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
Compare Revisions
- This comparison shows the changes necessary to convert path
/qaz_libs/trunk/sim/libs
- from Rev 49 to Rev 50
- ↔ Reverse comparison
Rev 49 → Rev 50
/bfm_packages_verilog/axis_bfm.f
File deleted
/bfm_packages_verilog/axi4_models.f
File deleted
/bfm_packages_verilog/BFM.f
1,4 → 1,3
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${LIB_BASE_DIR}/BFM/src/tb/tb_pkg.sv |
${LIB_BASE_DIR}/BFM/src/tb/tb_bfm_pkg.sv |
/qaz_lib_verilog/basal.f
1,38 → 1,15
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${LIB_BASE_DIR}/basal/src/8b10b/decode_8b10b.v |
${LIB_BASE_DIR}/basal/src/8b10b/encode_8b10b.v |
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${LIB_BASE_DIR}/basal/src/FIFOs/bc_sync_fifo.v |
${LIB_BASE_DIR}/basal/src/FIFOs/sync_fifo.sv |
${LIB_BASE_DIR}/basal/src/FIFOs/tiny_sync_fifo.sv |
${LIB_BASE_DIR}/basal/src/FIFOs/async_fifo.sv |
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${LIB_BASE_DIR}/basal/src/misc/bit_connect_big_to_little.v |
${LIB_BASE_DIR}/basal/src/misc/bit_connect_little_to_big.v |
${LIB_BASE_DIR}/basal/src/misc/bit_swap_big_to_little.v |
${LIB_BASE_DIR}/basal/src/misc/bit_swap_little_to_big.v |
${LIB_BASE_DIR}/basal/src/misc/one_hot_encoder.sv |
${LIB_BASE_DIR}/basal/src/misc/pulse_stretcher.v |
${LIB_BASE_DIR}/basal/src/misc/recursive_mux.sv |
${LIB_BASE_DIR}/basal/src/misc/sr_latch.v |
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${LIB_BASE_DIR}/basal/src/PRBS/cf_pnmon.v |
${LIB_BASE_DIR}/basal/src/PRBS/pcie_scrambler.v |
${LIB_BASE_DIR}/basal/src/PRBS/prbs_23_to_16.v |
${LIB_BASE_DIR}/basal/src/PRBS/prbs_23_to_64.v |
${LIB_BASE_DIR}/basal/src/PRBS/prbs_23_to_8.v |
${LIB_BASE_DIR}/basal/src/PRBS/prbs_7_to_14.v |
${LIB_BASE_DIR}/basal/src/PRBS/prbs_7_to_8.v |
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${LIB_BASE_DIR}/basal/src/RAM/asym_ram_sdp_read_wider.v |
${LIB_BASE_DIR}/basal/src/RAM/asym_ram_sdp_write_wider.v |
${LIB_BASE_DIR}/basal/src/RAM/bram_tdp.v |
${LIB_BASE_DIR}/basal/src/RAM/byte_enabled_simple_dual_port_ram.sv |
${LIB_BASE_DIR}/basal/src/RAM/read_mixed_width_ram.sv |
${LIB_BASE_DIR}/basal/src/RAM/write_mixed_width_ram.sv |
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${LIB_BASE_DIR}/basal/src/synchronize/synchronizer.v |
${LIB_BASE_DIR}/basal/src/synchronize/sync_reset.v |
${LIB_BASE_DIR}/basal/src/synchronize/pulse_synchronizer.v |
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/sim_verilog/axi4_models.f
File deleted
/sim_verilog/BFM.f
1,5 → 1,5
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${LIB_BASE_DIR}/BFM/src/tb/tb_base.sv |
${LIB_BASE_DIR}/BFM/src/tb/tb_clk.sv |
${LIB_BASE_DIR}/BFM/src/tb/tb_clk_class.sv |
# ${LIB_BASE_DIR}/BFM/src/tb/tb_clk.sv |
# ${LIB_BASE_DIR}/BFM/src/tb/tb_clk_class.sv |
/tb_packages_verilog/BFM.f
1,8 → 1,5
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${LIB_BASE_DIR}/BFM/src/tb/tb_clk_pkg.sv |
${LIB_BASE_DIR}/BFM/src/tb/q_pkg.sv |
${LIB_BASE_DIR}/BFM/src/tb/bfm_pkg.sv |
${LIB_BASE_DIR}/BFM/src/tb/logger_pkg.sv |
# ${LIB_BASE_DIR}/BFM/src/tb/tb_clk_pkg.sv |
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${LIB_BASE_DIR}/BFM/src/video_frame/video_frame_pkg.sv |