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Rev 12 → Rev 13
/AXI/src/wb_axi4lite_read_fsm.v
0,0 → 1,106
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
|
module |
wb_axi4lite_read_fsm |
( |
input axi_arvalid, |
input axi_rready, |
|
input wb_ack_i, |
input wb_err_i, |
input wb_rty_i, |
input wb_stall_i, |
input wb_cyc_o, |
input wb_stb_o, |
|
output read_idle, |
output read_waiting_for_slave, |
output read_waiting_for_master, |
output axi_arready, |
output axi_rvalid, |
output fsm_error, |
|
input axi_aclk, |
input axi_aresetn |
); |
|
//--------------------------------------------------- |
// |
wire wb_xfer_in_progress = wb_cyc_o & wb_stb_o; |
|
|
//--------------------------------------------------- |
// state machine binary definitions |
parameter IDLE_STATE = 4'b0001; |
parameter READ_VALID_STATE = 4'b0010; |
parameter READ_READY_STATE = 4'b0100; |
parameter ERROR_STATE = 4'b1000; |
|
|
//--------------------------------------------------- |
// common next state logic |
reg [3:0] axi_next_state; |
|
always @(*) |
if( axi_rready ) |
if( axi_arvalid ) |
if( wb_xfer_in_progress ) |
axi_next_state <= IDLE_STATE; |
else |
axi_next_state <= READ_VALID_STATE; |
else |
axi_next_state <= IDLE_STATE; |
else |
axi_next_state <= READ_READY_STATE; |
|
|
//--------------------------------------------------- |
// state machine flop |
reg [3:0] state; |
reg [3:0] next_state; |
|
always @(posedge axi_aclk) |
if(~axi_aresetn) |
state <= IDLE_STATE; |
else |
state <= next_state; |
|
|
//--------------------------------------------------- |
// state machine |
always @(*) |
case(state) |
IDLE_STATE: if( axi_arvalid ) |
next_state <= READ_VALID_STATE; |
else |
next_state <= IDLE_STATE; |
|
READ_VALID_STATE: if( wb_ack_i ) // wait for wb slave to return data |
next_state <= axi_next_state; |
else |
next_state <= READ_VALID_STATE; |
|
READ_READY_STATE: next_state <= axi_next_state; // wait for master to accept wb slave data |
|
ERROR_STATE: next_state <= IDLE_STATE; |
|
default: next_state <= ERROR_STATE; |
|
endcase |
|
|
//--------------------------------------------------- |
// outputs |
assign fsm_error = (state == ERROR_STATE); |
assign axi_arready = (state != READ_VALID_STATE) | (next_state != READ_VALID_STATE); |
assign axi_rvalid = (state != IDLE_STATE) & wb_ack_i; |
assign read_idle = (state == IDLE_STATE); |
assign read_waiting_for_slave = (state == READ_VALID_STATE) | (next_state == READ_VALID_STATE); |
assign read_waiting_for_master = (state == READ_READY_STATE) | (next_state == READ_READY_STATE); |
|
|
endmodule |
|
/AXI/src/reg_file_v1_0_S00_AXI.v
0,0 → 1,402
|
`timescale 1 ns / 1 ps |
|
module reg_file_v1_0_S00_AXI # |
( |
// Users to add parameters here |
|
// User parameters ends |
// Do not modify the parameters beyond this line |
|
// Width of S_AXI data bus |
parameter integer C_S_AXI_DATA_WIDTH = 32, |
// Width of S_AXI address bus |
parameter integer C_S_AXI_ADDR_WIDTH = 4 |
) |
( |
// Users to add ports here |
|
// User ports ends |
// Do not modify the ports beyond this line |
|
// Global Clock Signal |
input wire S_AXI_ACLK, |
// Global Reset Signal. This Signal is Active LOW |
input wire S_AXI_ARESETN, |
// Write address (issued by master, acceped by Slave) |
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR, |
// Write channel Protection type. This signal indicates the |
// privilege and security level of the transaction, and whether |
// the transaction is a data access or an instruction access. |
input wire [2 : 0] S_AXI_AWPROT, |
// Write address valid. This signal indicates that the master signaling |
// valid write address and control information. |
input wire S_AXI_AWVALID, |
// Write address ready. This signal indicates that the slave is ready |
// to accept an address and associated control signals. |
output wire S_AXI_AWREADY, |
// Write data (issued by master, acceped by Slave) |
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA, |
// Write strobes. This signal indicates which byte lanes hold |
// valid data. There is one write strobe bit for each eight |
// bits of the write data bus. |
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB, |
// Write valid. This signal indicates that valid write |
// data and strobes are available. |
input wire S_AXI_WVALID, |
// Write ready. This signal indicates that the slave |
// can accept the write data. |
output wire S_AXI_WREADY, |
// Write response. This signal indicates the status |
// of the write transaction. |
output wire [1 : 0] S_AXI_BRESP, |
// Write response valid. This signal indicates that the channel |
// is signaling a valid write response. |
output wire S_AXI_BVALID, |
// Response ready. This signal indicates that the master |
// can accept a write response. |
input wire S_AXI_BREADY, |
// Read address (issued by master, acceped by Slave) |
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR, |
// Protection type. This signal indicates the privilege |
// and security level of the transaction, and whether the |
// transaction is a data access or an instruction access. |
input wire [2 : 0] S_AXI_ARPROT, |
// Read address valid. This signal indicates that the channel |
// is signaling valid read address and control information. |
input wire S_AXI_ARVALID, |
// Read address ready. This signal indicates that the slave is |
// ready to accept an address and associated control signals. |
output wire S_AXI_ARREADY, |
// Read data (issued by slave) |
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA, |
// Read response. This signal indicates the status of the |
// read transfer. |
output wire [1 : 0] S_AXI_RRESP, |
// Read valid. This signal indicates that the channel is |
// signaling the required read data. |
output wire S_AXI_RVALID, |
// Read ready. This signal indicates that the master can |
// accept the read data and response information. |
input wire S_AXI_RREADY, |
|
output reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0, |
output reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1, |
output reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2, |
output reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3 |
|
); |
|
// AXI4LITE signals |
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr; |
reg axi_awready; |
reg axi_wready; |
reg [1 : 0] axi_bresp; |
reg axi_bvalid; |
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr; |
reg axi_arready; |
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata; |
reg [1 : 0] axi_rresp; |
reg axi_rvalid; |
|
// Example-specific design signals |
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH |
// ADDR_LSB is used for addressing 32/64 bit registers/memories |
// ADDR_LSB = 2 for 32 bits (n downto 2) |
// ADDR_LSB = 3 for 64 bits (n downto 3) |
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1; |
localparam integer OPT_MEM_ADDR_BITS = 1; |
//---------------------------------------------- |
//-- Signals for user logic register space example |
//------------------------------------------------ |
//-- Number of Slave Registers 4 |
// reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0; |
// reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1; |
// reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2; |
// reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3; |
wire slv_reg_rden; |
wire slv_reg_wren; |
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out; |
integer byte_index; |
|
// I/O Connections assignments |
|
assign S_AXI_AWREADY = axi_awready; |
assign S_AXI_WREADY = axi_wready; |
assign S_AXI_BRESP = axi_bresp; |
assign S_AXI_BVALID = axi_bvalid; |
assign S_AXI_ARREADY = axi_arready; |
assign S_AXI_RDATA = axi_rdata; |
assign S_AXI_RRESP = axi_rresp; |
assign S_AXI_RVALID = axi_rvalid; |
// Implement axi_awready generation |
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both |
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is |
// de-asserted when reset is low. |
|
always @( posedge S_AXI_ACLK ) |
begin |
if ( S_AXI_ARESETN == 1'b0 ) |
begin |
axi_awready <= 1'b0; |
end |
else |
begin |
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID) |
begin |
// slave is ready to accept write address when |
// there is a valid write address and write data |
// on the write address and data bus. This design |
// expects no outstanding transactions. |
axi_awready <= 1'b1; |
end |
else |
begin |
axi_awready <= 1'b0; |
end |
end |
end |
|
// Implement axi_awaddr latching |
// This process is used to latch the address when both |
// S_AXI_AWVALID and S_AXI_WVALID are valid. |
|
always @( posedge S_AXI_ACLK ) |
begin |
if ( S_AXI_ARESETN == 1'b0 ) |
begin |
axi_awaddr <= 0; |
end |
else |
begin |
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID) |
begin |
// Write Address latching |
axi_awaddr <= S_AXI_AWADDR; |
end |
end |
end |
|
// Implement axi_wready generation |
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both |
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is |
// de-asserted when reset is low. |
|
always @( posedge S_AXI_ACLK ) |
begin |
if ( S_AXI_ARESETN == 1'b0 ) |
begin |
axi_wready <= 1'b0; |
end |
else |
begin |
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID) |
begin |
// slave is ready to accept write data when |
// there is a valid write address and write data |
// on the write address and data bus. This design |
// expects no outstanding transactions. |
axi_wready <= 1'b1; |
end |
else |
begin |
axi_wready <= 1'b0; |
end |
end |
end |
|
// Implement memory mapped register select and write logic generation |
// The write data is accepted and written to memory mapped registers when |
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to |
// select byte enables of slave registers while writing. |
// These registers are cleared when reset (active low) is applied. |
// Slave register write enable is asserted when valid address and data are available |
// and the slave is ready to accept the write address and write data. |
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID; |
|
always @( posedge S_AXI_ACLK ) |
begin |
if ( S_AXI_ARESETN == 1'b0 ) |
begin |
slv_reg0 <= 0; |
slv_reg1 <= 0; |
slv_reg2 <= 0; |
slv_reg3 <= 0; |
end |
else begin |
if (slv_reg_wren) |
begin |
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) |
2'h0: |
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) |
if ( S_AXI_WSTRB[byte_index] == 1 ) begin |
// Respective byte enables are asserted as per write strobes |
// Slave register 0 |
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; |
end |
2'h1: |
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) |
if ( S_AXI_WSTRB[byte_index] == 1 ) begin |
// Respective byte enables are asserted as per write strobes |
// Slave register 1 |
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; |
end |
2'h2: |
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) |
if ( S_AXI_WSTRB[byte_index] == 1 ) begin |
// Respective byte enables are asserted as per write strobes |
// Slave register 2 |
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; |
end |
2'h3: |
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) |
if ( S_AXI_WSTRB[byte_index] == 1 ) begin |
// Respective byte enables are asserted as per write strobes |
// Slave register 3 |
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; |
end |
default : begin |
slv_reg0 <= slv_reg0; |
slv_reg1 <= slv_reg1; |
slv_reg2 <= slv_reg2; |
slv_reg3 <= slv_reg3; |
end |
endcase |
end |
end |
end |
|
// Implement write response logic generation |
// The write response and response valid signals are asserted by the slave |
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. |
// This marks the acceptance of address and indicates the status of |
// write transaction. |
|
always @( posedge S_AXI_ACLK ) |
begin |
if ( S_AXI_ARESETN == 1'b0 ) |
begin |
axi_bvalid <= 0; |
axi_bresp <= 2'b0; |
end |
else |
begin |
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID) |
begin |
// indicates a valid write response is available |
axi_bvalid <= 1'b1; |
axi_bresp <= 2'b0; // 'OKAY' response |
end // work error responses in future |
else |
begin |
if (S_AXI_BREADY && axi_bvalid) |
//check if bready is asserted while bvalid is high) |
//(there is a possibility that bready is always asserted high) |
begin |
axi_bvalid <= 1'b0; |
end |
end |
end |
end |
|
// Implement axi_arready generation |
// axi_arready is asserted for one S_AXI_ACLK clock cycle when |
// S_AXI_ARVALID is asserted. axi_awready is |
// de-asserted when reset (active low) is asserted. |
// The read address is also latched when S_AXI_ARVALID is |
// asserted. axi_araddr is reset to zero on reset assertion. |
|
always @( posedge S_AXI_ACLK ) |
begin |
if ( S_AXI_ARESETN == 1'b0 ) |
begin |
axi_arready <= 1'b0; |
axi_araddr <= 32'b0; |
end |
else |
begin |
if (~axi_arready && S_AXI_ARVALID) |
begin |
// indicates that the slave has acceped the valid read address |
axi_arready <= 1'b1; |
// Read address latching |
axi_araddr <= S_AXI_ARADDR; |
end |
else |
begin |
axi_arready <= 1'b0; |
end |
end |
end |
|
// Implement axi_arvalid generation |
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both |
// S_AXI_ARVALID and axi_arready are asserted. The slave registers |
// data are available on the axi_rdata bus at this instance. The |
// assertion of axi_rvalid marks the validity of read data on the |
// bus and axi_rresp indicates the status of read transaction.axi_rvalid |
// is deasserted on reset (active low). axi_rresp and axi_rdata are |
// cleared to zero on reset (active low). |
always @( posedge S_AXI_ACLK ) |
begin |
if ( S_AXI_ARESETN == 1'b0 ) |
begin |
axi_rvalid <= 0; |
axi_rresp <= 0; |
end |
else |
begin |
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid) |
begin |
// Valid read data is available at the read data bus |
axi_rvalid <= 1'b1; |
axi_rresp <= 2'b0; // 'OKAY' response |
end |
else if (axi_rvalid && S_AXI_RREADY) |
begin |
// Read data is accepted by the master |
axi_rvalid <= 1'b0; |
end |
end |
end |
|
// Implement memory mapped register select and read logic generation |
// Slave register read enable is asserted when valid address is available |
// and the slave is ready to accept the read address. |
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid; |
always @(*) |
begin |
// Address decoding for reading registers |
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) |
2'h0 : reg_data_out <= slv_reg0; |
2'h1 : reg_data_out <= slv_reg1; |
2'h2 : reg_data_out <= slv_reg2; |
2'h3 : reg_data_out <= slv_reg3; |
default : reg_data_out <= 0; |
endcase |
end |
|
// Output register or memory read data |
always @( posedge S_AXI_ACLK ) |
begin |
if ( S_AXI_ARESETN == 1'b0 ) |
begin |
axi_rdata <= 0; |
end |
else |
begin |
// When there is a valid read address (S_AXI_ARVALID) with |
// acceptance of read address by the slave (axi_arready), |
// output the read dada |
if (slv_reg_rden) |
begin |
axi_rdata <= reg_data_out; // register read data |
end |
end |
end |
|
// Add user logic here |
|
// User logic ends |
|
endmodule |
/AXI/src/wb_axi4lite_bridge.v
0,0 → 1,189
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
|
module |
wb_axi4lite_bridge |
#( |
parameter DATA_WIDTH = 32, |
parameter ADDR_WIDTH = 32 |
) |
( |
input [ADDR_WIDTH-1:0] axi_awaddr, |
input [2:0] axi_awprot, |
input axi_awvalid, |
output axi_awready, |
input [DATA_WIDTH-1:0] axi_wdata, |
input [(DATA_WIDTH/8)-1:0] axi_wstrb, |
input axi_wvalid, |
output axi_wready, |
output [1:0] axi_bresp, |
output axi_bvalid, |
input axi_bready, |
input [ADDR_WIDTH-1:0] axi_araddr, |
input [2:0] axi_arprot, |
input axi_arvalid, |
output axi_arready, |
output [DATA_WIDTH-1:0] axi_rdata, |
output [1:0] axi_rresp, |
output axi_rvalid, |
input axi_rready, |
|
input axi_aclk, |
input axi_aresetn, |
|
input wb_ack_i, // normal termination |
input wb_err_i, // termination w/ error |
input wb_rty_i, // termination w/ retry |
input wb_stall_i, // slave pipeline can accept another request |
input [DATA_WIDTH-1:0] wb_dat_i, // input data bus |
output wb_cyc_o, // cycle valid output |
output [ADDR_WIDTH-1:0] wb_adr_o, // address bus outputs |
output wb_stb_o, // strobe output |
output wb_we_o, // indicates write transfer |
output [(DATA_WIDTH/8)-1:0] wb_sel_o, // byte select outputs |
output [DATA_WIDTH-1:0] wb_dat_o |
); |
|
|
//--------------------------------------------------- |
// |
reg [ADDR_WIDTH-1:0] axi_araddr_r; |
|
always @(posedge axi_aclk) |
if( axi_arvalid ) |
axi_araddr_r <= axi_araddr; |
|
|
//--------------------------------------------------- |
// |
reg [2:0] axi_arprot_r; |
|
always @(posedge axi_aclk) |
if( axi_arvalid ) |
axi_arprot_r <= axi_arprot; |
|
|
//--------------------------------------------------- |
// |
reg [ADDR_WIDTH-1:0] axi_awaddr_r; |
|
always @(posedge axi_aclk) |
if( axi_awvalid ) |
axi_awaddr_r <= axi_awaddr; |
|
|
//--------------------------------------------------- |
// |
reg [(DATA_WIDTH/8)-1:0] axi_wstrb_r; |
|
always @(posedge axi_aclk) |
if( axi_awvalid ) |
axi_wstrb_r <= axi_wstrb; |
|
|
//--------------------------------------------------- |
// |
wire read_idle; |
wire read_waiting_for_slave; |
wire read_waiting_for_master; |
|
(* KEEP = "TRUE" *) wire read_fsm_error; |
|
wb_axi4lite_read_fsm |
wb_axi4lite_read_fsm_i |
( |
.axi_arvalid(axi_arvalid), |
.axi_rready(axi_rready), |
|
.wb_ack_i(wb_ack_i), |
.wb_err_i(wb_err_i), |
.wb_rty_i(wb_rty_i), |
.wb_stall_i(wb_stall_i), |
.wb_cyc_o(wb_cyc_o), |
.wb_stb_o(wb_stb_o), |
|
.read_idle(read_idle), |
.read_waiting_for_slave(read_waiting_for_slave), |
.read_waiting_for_master(read_waiting_for_master), |
.axi_arready(axi_arready), |
.axi_rvalid(axi_rvalid), |
.fsm_error(read_fsm_error), |
|
.axi_aclk(axi_aclk), |
.axi_aresetn(axi_aresetn) |
); |
|
|
|
//--------------------------------------------------- |
// |
wire write_idle; |
wire write_waiting_for_slave; |
wire write_waiting_for_master; |
|
wb_axi4lite_write_fsm |
wb_axi4lite_write_fsm_i |
( |
.axi_awvalid(axi_awvalid), |
.axi_wvalid(axi_wvalid), |
.axi_bready(axi_bready), |
.axi_rready(axi_rready), |
|
.wb_ack_i(wb_ack_i), |
.wb_err_i(wb_err_i), |
.wb_rty_i(wb_rty_i), |
.wb_stall_i(wb_stall_i), |
.wb_cyc_o(wb_cyc_o), |
.wb_stb_o(wb_stb_o), |
|
.write_idle(write_idle), |
.write_waiting_for_slave(write_waiting_for_slave), |
.write_waiting_for_master(write_waiting_for_master), |
.axi_awready(axi_awready), |
.axi_wready(axi_wready), |
.axi_bvalid(axi_bvalid), |
.fsm_error(fsm_error), |
|
.axi_aclk(axi_aclk), |
.axi_aresetn(axi_aresetn) |
); |
|
|
//--------------------------------------------------- |
// |
wb_master_fsm |
wb_master_fsm_i |
( |
.wb_ack_i(wb_ack_i), |
.wb_stall_i(wb_stall_i), |
.wb_cyc_o(wb_cyc_o), |
.wb_stb_o(wb_stb_o), |
.wb_we_o(wb_we_o), |
|
.read_idle(read_idle), |
.read_waiting_for_slave(read_waiting_for_slave), |
.read_waiting_for_master(read_waiting_for_master), |
.write_idle(write_idle), |
.write_waiting_for_slave(write_waiting_for_slave), |
.write_waiting_for_master(write_waiting_for_master), |
|
.axi_aclk(axi_aclk), |
.axi_aresetn(axi_aresetn) |
); |
|
|
//--------------------------------------------------- |
// |
assign axi_bresp = (wb_err_i | wb_rty_i) ? 2'b10 : 2'b00; |
assign axi_rdata = wb_dat_i; |
assign axi_rresp = (wb_err_i | wb_rty_i) ? 2'b10 : 2'b00; |
|
assign wb_adr_o = wb_we_o ? axi_awaddr_r : axi_araddr_r; |
assign wb_sel_o = wb_we_o ? axi_wstrb_r : {(DATA_WIDTH/8){1'b1}}; |
assign wb_dat_o = axi_wdata; |
|
|
endmodule |
|
/AXI/src/wb_master_fsm.v
0,0 → 1,111
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
|
module |
wb_master_fsm |
( |
input wb_ack_i, |
input wb_stall_i, |
output reg wb_cyc_o, |
output reg wb_stb_o, |
output reg wb_we_o, |
|
input read_idle, |
input read_waiting_for_slave, |
input read_waiting_for_master, |
input write_idle, |
input write_waiting_for_slave, |
input write_waiting_for_master, |
|
input axi_aclk, |
input axi_aresetn |
); |
|
//--------------------------------------------------- |
// state machine binary definitions |
parameter IDLE_STATE = 5'b0_0001; |
parameter WB_READ_STATE = 5'b0_0010; |
parameter WB_WRITE_STATE = 5'b0_0100; |
parameter WB_ACK_STATE = 5'b0_1000; |
parameter ERROR_STATE = 5'b1_0000; |
|
|
//--------------------------------------------------- |
// common next state logic |
reg [4:0] wb_next_state; |
|
always @(*) |
if( wb_ack_i ) |
wb_next_state <= IDLE_STATE; |
else |
wb_next_state <= WB_ACK_STATE; |
|
|
//--------------------------------------------------- |
// state machine flop |
reg [4:0] state; |
reg [4:0] next_state; |
|
always @(posedge axi_aclk) |
if(~axi_aresetn) |
state <= IDLE_STATE; |
else |
state <= next_state; |
|
|
//--------------------------------------------------- |
// state machine |
always @(*) |
case(state) |
IDLE_STATE: if( write_waiting_for_slave ) |
next_state <= WB_WRITE_STATE; |
else if( read_waiting_for_slave ) |
next_state <= WB_READ_STATE; |
else |
next_state <= IDLE_STATE; |
|
WB_READ_STATE: next_state <= wb_next_state; |
|
WB_WRITE_STATE: next_state <= wb_next_state; |
|
WB_ACK_STATE: next_state <= wb_next_state; |
|
ERROR_STATE: next_state <= IDLE_STATE; |
|
default: next_state <= ERROR_STATE; |
|
endcase |
|
|
//--------------------------------------------------- |
// |
wire reset_flops = (next_state == IDLE_STATE) | ~axi_aresetn; |
|
always @(posedge axi_aclk) |
if( reset_flops ) |
wb_cyc_o <= 0; |
else |
wb_cyc_o <= 1; |
|
always @(posedge axi_aclk) |
if( reset_flops ) |
wb_stb_o <= 0; |
else |
wb_stb_o <= 1; |
|
always @(posedge axi_aclk) |
if( reset_flops ) |
wb_we_o <= 0; |
else if(next_state == WB_WRITE_STATE) |
wb_we_o <= 1; |
|
|
//--------------------------------------------------- |
// outputs |
assign fsm_error = (state == ERROR_STATE); |
|
|
endmodule |
|
/AXI/src/wb_axi4lite_write_fsm.v
0,0 → 1,115
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
|
module |
wb_axi4lite_write_fsm |
( |
input axi_awvalid, |
input axi_wvalid, |
input axi_bready, |
input axi_rready, |
|
input wb_ack_i, |
input wb_err_i, |
input wb_rty_i, |
input wb_stall_i, |
input wb_cyc_o, |
input wb_stb_o, |
|
output write_idle, |
output write_waiting_for_slave, |
output write_waiting_for_master, |
output axi_awready, |
output axi_wready, |
output axi_bvalid, |
output fsm_error, |
|
input axi_aclk, |
input axi_aresetn |
); |
|
//--------------------------------------------------- |
// |
wire wb_xfer_in_progress = wb_cyc_o & wb_stb_o; |
|
|
//--------------------------------------------------- |
// state machine binary definitions |
parameter IDLE_STATE = 4'b0001; |
parameter WRITE_VALID_STATE = 4'b0010; |
parameter WRITE_READY_STATE = 4'b0100; |
parameter ERROR_STATE = 4'b1000; |
|
|
//--------------------------------------------------- |
// common next state logic |
reg [3:0] axi_next_state; |
|
always @(*) |
if( axi_awvalid ) |
axi_next_state <= WRITE_VALID_STATE; |
else |
axi_next_state <= IDLE_STATE; |
|
|
//--------------------------------------------------- |
// state machine flop |
reg [3:0] state; |
reg [3:0] next_state; |
|
always @(posedge axi_aclk) |
if(~axi_aresetn) |
state <= IDLE_STATE; |
else |
state <= next_state; |
|
|
//--------------------------------------------------- |
// state machine |
always @(*) |
case(state) |
IDLE_STATE: if( axi_awvalid ) |
if( wb_xfer_in_progress ) |
next_state <= IDLE_STATE; |
else |
next_state <= WRITE_VALID_STATE; |
else |
next_state <= IDLE_STATE; |
|
WRITE_VALID_STATE: if( axi_wvalid & wb_ack_i ) // wait for wb slave to accept data |
if( axi_bready ) |
next_state <= axi_next_state; |
else |
next_state <= WRITE_READY_STATE; |
else |
next_state <= WRITE_VALID_STATE; |
|
WRITE_READY_STATE: if( wb_ack_i ) // wait for master to accept wb slave response |
next_state <= axi_next_state; |
else |
next_state <= WRITE_READY_STATE; |
|
ERROR_STATE: next_state <= IDLE_STATE; |
|
default: next_state <= ERROR_STATE; |
|
endcase |
|
|
//--------------------------------------------------- |
// outputs |
assign write_idle = (state == IDLE_STATE); |
assign write_waiting_for_slave = (state == WRITE_VALID_STATE); |
assign write_waiting_for_master = (state == WRITE_READY_STATE); |
assign axi_awready = (state != WRITE_READY_STATE); |
assign axi_wready = (state != IDLE_STATE) & wb_ack_i; |
assign axi_bvalid = (state != IDLE_STATE) & wb_ack_i; |
assign fsm_error = (state == ERROR_STATE); |
|
|
endmodule |
|
|
|
/AXI/sim/tests/debug_unit_reg_file_v1_0_S00_AXI/setup_test.do
0,0 → 1,32
# |
|
set env(ROOT_DIR) ../../../.. |
set env(PROJECT_DIR) ../../.. |
|
|
if {[file exists work/_info]} { |
echo "INFO: Simulation library work already exists" |
# echo "INFO: deleting ./work and recompiling all" |
# file delete -force ./work |
# vlib work |
} else { |
vlib work |
} |
|
vlog -O0 -f ../../libs/FPGA_verilog/FPGA_AXI.f |
|
vlog -O0 -f ../../libs/sim_verilog/tb_lib.f |
vlog -O0 -f ../../libs/sim_verilog/axi4_bfm.f |
|
if { [info exists env(MAKEFILE_TEST_RUN)] } { |
vlog -O0 +incdir+../../src/BP065-BU-01000-r0p1-00rel0/sva +define+MAKEFILE_TEST_RUN ../../src/tb_unit_reg_file_v1_0_S00_AXI.sv |
} else { |
vlog -O0 +incdir+../../src/BP065-BU-01000-r0p1-00rel0/sva ../../src/tb_unit_reg_file_v1_0_S00_AXI.sv |
} |
|
# unit sim files |
|
# compile test last |
vlog -O0 ./the_test.sv |
|
|
/AXI/sim/tests/debug_unit_reg_file_v1_0_S00_AXI/wip.do
0,0 → 1,13
# |
|
|
vlog -O0 -f ../../libs/FPGA_verilog/FPGA_AXI.f |
|
vlog -O0 -f ../../libs/sim_verilog/axi4_bfm.f |
|
vlog -O0 +incdir+../../src/BP065-BU-01000-r0p1-00rel0/sva ../../src/tb_unit_reg_file_v1_0_S00_AXI.sv |
|
|
vlog -O0 ./the_test.sv |
|
|
/AXI/sim/tests/debug_unit_reg_file_v1_0_S00_AXI/the_test.sv
0,0 → 1,71
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
`timescale 1ps/1ps |
|
|
module the_test( |
input tb_clk, |
input tb_rst |
); |
|
// -------------------------------------------------------------------- |
// |
import qaz_axi4_bfm_pkg::*; |
v_qaz_axi4_bfm axi4lite_bfm = $root.tb_top.axi4lite_bfm.bfm; |
|
int read_data; |
|
// -------------------------------------------------------------------- |
// |
task run_the_test; |
begin |
|
// -------------------------------------------------------------------- |
// insert test below |
// -------------------------------------------------------------------- |
|
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench begun.\n", $time); |
$display("^^^---------------------------------"); |
|
wait( ~tb_rst ); |
$display("^^^ %16.t | out of reset.\n", $time); |
|
repeat(10) @(posedge tb_clk); |
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.read( 32'h0000_0010, read_data ); |
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.read( 32'h0000_0014, read_data ); |
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.write( 32'h0000_0010, 32'habbabeef, 8'hff ); |
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.read( 32'h0000_0010, read_data ); |
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.write( 32'h0000_001c, 32'h1badcafe, 8'hff ); |
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.read( 32'h0000_001c, read_data ); |
|
repeat(20) @(posedge tb_clk); |
|
$stop(); |
|
|
// -------------------------------------------------------------------- |
// insert test above |
// -------------------------------------------------------------------- |
|
end |
endtask |
|
|
endmodule |
|
|
/AXI/sim/tests/debug_unit_reg_file_v1_0_S00_AXI/sim.do
0,0 → 1,17
# |
# |
|
|
quit -sim |
|
|
# vsim -novopt -L simprims_ver -L unisims_ver work.glbl work.tb_top |
vsim -novopt work.tb_top |
|
|
# # log all signals |
# log -r * |
|
# run -all ; |
|
|
/AXI/sim/tests/debug_unit_wb_axi4lite_bridge/setup_test.do
0,0 → 1,37
# |
|
set env(ROOT_DIR) ../../../.. |
set env(PROJECT_DIR) ../../.. |
|
|
if {[file exists work/_info]} { |
echo "INFO: Simulation library work already exists" |
# echo "INFO: deleting ./work and recompiling all" |
# file delete -force ./work |
# vlib work |
} else { |
vlib work |
} |
|
vlog -O0 -f ../../libs/FPGA_verilog/FPGA_AXI.f |
|
vlog -O0 -f ../../libs/sim_verilog/tb_lib.f |
vlog -O0 -f ../../libs/sim_verilog/axi4_bfm.f |
vlog -O0 -f ../../libs/sim_verilog/wishbone.f |
|
# if { [info exists env(MAKEFILE_TEST_RUN)] } { |
# vlog -O0 +incdir+../../src/BP065-BU-01000-r0p1-00rel0/sva +define+MAKEFILE_TEST_RUN ../../src/tb_unit_reg_file_v1_0_S00_AXI.sv |
# } else { |
# vlog -O0 +incdir+../../src/BP065-BU-01000-r0p1-00rel0/sva ../../src/tb_unit_reg_file_v1_0_S00_AXI.sv |
# } |
|
vlog -O0 +incdir+../../src/BP065-BU-01000-r0p1-00rel0/sva ../../src/tb_unit_debug_unit_wb_axi4lite_bridge.sv |
|
|
|
# unit sim files |
|
# compile test last |
vlog -O0 ./the_test.sv |
|
|
/AXI/sim/tests/debug_unit_wb_axi4lite_bridge/wb_slave_model.txt
0,0 → 1,16
00 |
00 |
00 |
00 |
11 |
11 |
11 |
11 |
22 |
22 |
22 |
22 |
33 |
33 |
33 |
33 |
/AXI/sim/tests/debug_unit_wb_axi4lite_bridge/wip.do
0,0 → 1,13
# |
|
vlog -O0 -f ../../libs/FPGA_verilog/FPGA_AXI.f |
|
vlog -O0 -f ../../libs/sim_verilog/tb_lib.f |
vlog -O0 -f ../../libs/sim_verilog/axi4_bfm.f |
vlog -O0 -f ../../libs/sim_verilog/wishbone.f |
|
vlog -O0 +incdir+../../src/BP065-BU-01000-r0p1-00rel0/sva ../../src/tb_unit_debug_unit_wb_axi4lite_bridge.sv |
|
vlog -O0 ./the_test.sv |
|
|
/AXI/sim/tests/debug_unit_wb_axi4lite_bridge/the_test.sv
0,0 → 1,99
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
`timescale 1ps/1ps |
|
|
module the_test( |
input tb_clk, |
input tb_rst |
); |
|
// -------------------------------------------------------------------- |
// |
import qaz_axi4_bfm_pkg::*; |
v_qaz_axi4_bfm axi4lite_bfm = $root.tb_top.axi4lite_bfm.bfm; |
|
int read_data; |
|
// -------------------------------------------------------------------- |
// |
task run_the_test; |
begin |
|
// -------------------------------------------------------------------- |
// insert test below |
// -------------------------------------------------------------------- |
|
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench begun.\n", $time); |
$display("^^^---------------------------------"); |
|
wait( ~tb_rst ); |
$display("^^^ %16.t | out of reset.\n", $time); |
|
repeat(10) @(posedge tb_clk); |
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.read( 32'h0000_0010, read_data ); |
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.read( 32'h0000_0014, read_data ); |
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.read( 32'h0000_0018, read_data ); |
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.read( 32'h0000_001c, read_data ); |
|
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.write( 32'h0000_0010, 32'habba_beef, 4'b1111 ); |
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.read( 32'h0000_0010, read_data ); |
|
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.write( 32'h0000_0014, 32'h1bad_cafe, 4'b1111 ); |
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.read( 32'h0000_0014, read_data ); |
|
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.write( 32'h0000_0018, 32'ha1b2_c2d3, 4'b1111 ); |
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.read( 32'h0000_0018, read_data ); |
|
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.write( 32'h0000_001C, 32'hffff_ffff, 4'b1111 ); |
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.read( 32'h0000_001C, read_data ); |
|
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.write( 32'h0000_001C, 32'h7600_3200, 4'b1010 ); |
|
repeat(5) @(posedge tb_clk); |
axi4lite_bfm.read( 32'h0000_001C, read_data ); |
|
|
repeat(10) @(posedge tb_clk); |
|
|
// -------------------------------------------------------------------- |
// insert test above |
// -------------------------------------------------------------------- |
|
end |
endtask |
|
|
endmodule |
|
|
/AXI/sim/tests/debug_unit_wb_axi4lite_bridge/sim.do
0,0 → 1,17
# |
# |
|
|
quit -sim |
|
|
# vsim -novopt -L simprims_ver -L unisims_ver work.glbl work.tb_top |
vsim -novopt work.tb_top |
|
|
# # log all signals |
# log -r * |
|
# run -all ; |
|
|
/AXI/sim/scripts/sim_procs.do
0,0 → 1,169
# ------------------------------------ |
# |
# ------------------------------------ |
|
|
# ------------------------------------ |
# |
proc sim_compile_all { target } { |
|
global env |
|
set env(ROOT_DIR) ../../../.. |
set env(PROJECT_DIR) ../../.. |
set env(SIM_TARGET) $target |
|
if {[file exists work/_info]} { |
echo "INFO: Simulation library work already exists" |
echo "INFO: deleting ./work and recompiling all" |
file delete -force ./work |
vlib work |
} else { |
vlib work |
} |
|
if { [file exists ../../libs/altera_sim.f] } { |
vlog -O0 -f ../../libs/altera_sim.f |
} elseif {[file exists ../../libs/xilinx_sim.f]} { |
vlog -O0 -f ../../libs/xilinx_sim.f |
} |
|
foreach filename [glob -nocomplain -directory ../../libs/sim_verilog/ *.f] { |
echo "INFO: compiling $filename" |
vlog -O0 -f $filename |
} |
|
foreach filename [glob -nocomplain -directory ../../libs/sim_VHDL/ *.f] { |
echo "INFO: compiling $filename" |
vcom -explicit -O0 -f $filename |
} |
|
switch $target { |
|
"fpga" { |
echo "INFO: compiling $target rtl" |
|
foreach filename [glob -nocomplain -directory ../../libs/FPGA_verilog/ *.f] { |
echo "INFO: compiling $filename" |
vlog -O0 -f $filename |
} |
|
foreach filename [glob -nocomplain -directory ../../libs/FPGA_VHDL/ *.f] { |
echo "INFO: compiling $filename" |
vcom -explicit -O0 -f $filename |
} |
} |
|
"syn" { |
echo "INFO: compiling $target rtl" |
|
foreach filename [glob -nocomplain -directory ../../libs/syn_verilog/ *.f] { |
echo "INFO: compiling $filename" |
vlog -O0 -f $filename |
} |
|
foreach filename [glob -nocomplain -directory ../../libs/syn_VHDL/ *.f] { |
echo "INFO: compiling $filename" |
vcom -explicit -O0 -f $filename |
} |
} |
|
"gate" { |
echo "INFO: compiling $target rtl" |
|
foreach filename [glob -nocomplain -directory ../../libs/gate_verilog/ *.f] { |
echo "INFO: compiling $filename" |
vlog -O0 -f $filename |
} |
|
foreach filename [glob -nocomplain -directory ../../libs/gate_VHDL/ *.f] { |
echo "INFO: compiling $filename" |
vcom -explicit -O0 -f $filename |
} |
} |
|
default { |
echo "ERROR: <$target> Target not suported!!!" |
} |
} |
|
} |
|
|
# ------------------------------------ |
# |
proc sim_run_sim { } { |
|
if {[file exists ./sim.do]} { |
do ./sim.do |
} elseif {[file exists ../../libs/sim.do]} { |
do ../../libs/sim.do |
} elseif {[file exists ../../libs/altera_sim.f]} { |
vsim -novopt -f ../../libs/altera_sim.f -l transcript.txt work.tb_top |
} elseif {[file exists ../../libs/xilinx_sim.f]} { |
vsim -novopt -f ../../libs/xilinx_sim.f -l transcript.txt work.tb_top work.glbl |
} |
|
if { [file exists ./wave.do] } { |
do ./wave.do |
} |
} |
|
|
# ------------------------------------ |
# |
proc sim_run_test { } { |
|
global env |
|
if { [file exists work/_info] } { |
echo "INFO: Simulation library work already exists" |
} else { |
vlib work |
} |
|
# unique setup |
if { [file exists ./setup_test.do] } { |
do ./setup_test.do |
} |
|
if { [info exists env(MAKEFILE_TEST_RUN)] } { |
|
vlog +define+MAKEFILE_TEST_RUN ../../src/tb_top.v |
|
} else { |
|
sim_run_sim |
} |
|
run -all |
|
} |
|
|
# ------------------------------------ |
# |
proc sim_restart { } { |
|
global env |
|
# work in progress files to compile |
if { [file exists ./wip.do] } { |
echo "INFO: found ./wip.do" |
do ./wip.do |
} else { |
|
sim_compile_all $::env(SIM_TARGET) |
} |
|
if { [string equal nodesign [runStatus]] } { |
sim_run_sim |
} else { |
restart -force |
} |
|
run -all |
|
} |
|
|
/AXI/sim/scripts/sim_debug_init.do
0,0 → 1,24
# ------------------------------------ |
# |
# ------------------------------------ |
|
do ../../scripts/sim_procs.do |
|
global env |
|
set env(SIM_TARGET) fpga |
|
|
radix -hexadecimal |
|
if { [file exists ./setup_test.do] } { |
do ./setup_test.do |
} else { |
sim_compile_all rtl |
} |
|
|
sim_run_test |
|
|
|
/AXI/sim/scripts/sim_run_test.do
0,0 → 1,13
# ------------------------------------ |
# |
# ------------------------------------ |
|
do ../../scripts/sim_procs.do |
|
|
sim_run_test |
|
quit |
|
|
|
/AXI/sim/src/tb_unit_reg_file_v1_0_S00_AXI.sv
0,0 → 1,282
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
`ifndef AXI4PC_TYPES |
`include "Axi4PC_ace_defs.v" |
`endif |
|
`ifndef AXI4PC_MESSAGES |
`include "Axi4PC_ace_message_defs.v" |
`endif |
|
|
module tb_top(); |
|
// -------------------------------------------------------------------- |
// test bench clock & reset |
wire clk_200mhz; |
wire tb_clk = clk_200mhz; |
wire tb_rst; |
|
tb_base #( .PERIOD(5000) ) tb( clk_200mhz, tb_rst ); |
|
|
//------------------------------------------------------------------------------ |
// INDEX: 1) Parameters |
//------------------------------------------------------------------------------ |
|
// INDEX: - Configurable (user can set) |
// ===== |
// Parameters below can be set by the user. |
|
// Set DATA_WIDTH to the data-bus width required |
localparam DATA_WIDTH = 32; // data bus width, default = 64-bit |
|
// Select the number of channel ID bits required |
localparam WID_WIDTH = 4; // (A|W|R|B)ID width |
localparam RID_WIDTH = 4; // (A|W|R|B)ID width |
|
// Select the size of the USER buses, default = 32-bit |
localparam AWUSER_WIDTH = 32; // width of the user AW sideband field |
localparam WUSER_WIDTH = 32; // width of the user W sideband field |
localparam BUSER_WIDTH = 32; // width of the user B sideband field |
localparam ARUSER_WIDTH = 32; // width of the user AR sideband field |
localparam RUSER_WIDTH = 32; // width of the user R sideband field |
|
// Size of CAMs for storing outstanding read bursts, this should match or |
// exceed the number of outstanding read addresses accepted into the slave |
// interface |
localparam MAXRBURSTS = 16; |
|
// Size of CAMs for storing outstanding write bursts, this should match or |
// exceed the number of outstanding write bursts into the slave interface |
localparam MAXWBURSTS = 16; |
|
// Maximum number of cycles between VALID -> READY high before a warning is |
// generated |
localparam MAXWAITS = 16; |
|
// Recommended Rules Enable |
// enable/disable reporting of all AXI4_REC*_* rules |
localparam RecommendOn = 1'b1; |
// enable/disable reporting of just AXI4_REC*_MAX_WAIT rules |
localparam RecMaxWaitOn = 1'b1; |
|
|
// Set the protocol - used to disable some AXI4 checks for ACE |
localparam PROTOCOL = `AXI4PC_AMBA_ACE_LITE; |
|
// Set ADDR_WIDTH to the address-bus width required |
localparam ADDR_WIDTH = 32; // address bus width, default = 32-bit |
|
// Set EXMON_WIDTH to the exclusive access monitor width required |
localparam EXMON_WIDTH = 4; // exclusive access width, default = 4-bit |
|
// INDEX: - Calculated (user should not override) |
// ===== |
// Do not override the following parameters: they must be calculated exactly |
// as shown below |
localparam DATA_MAX = DATA_WIDTH-1; // data max index |
localparam ADDR_MAX = ADDR_WIDTH-1; // address max index |
localparam STRB_WIDTH = DATA_WIDTH/8; // WSTRB width |
localparam STRB_MAX = STRB_WIDTH-1; // WSTRB max index |
localparam STRB_1 = {{STRB_MAX{1'b0}}, 1'b1}; // value 1 in strobe width |
localparam ID_MAX_R = RID_WIDTH? RID_WIDTH-1:0; // ID max index |
localparam ID_MAX_W = WID_WIDTH? WID_WIDTH-1:0; // ID max index |
localparam ID_MAX = ID_MAX_W > ID_MAX_R ? ID_MAX_W : ID_MAX_R; // ID max index |
localparam EXMON_MAX = EXMON_WIDTH-1; // EXMON max index |
localparam EXMON_HI = {EXMON_WIDTH{1'b1}}; // EXMON max value |
|
localparam AWUSER_MAX = AWUSER_WIDTH ? AWUSER_WIDTH-1:0; // AWUSER max index |
localparam WUSER_MAX = WUSER_WIDTH ? WUSER_WIDTH-1:0; // WUSER max index |
localparam BUSER_MAX = BUSER_WIDTH ? BUSER_WIDTH-1:0; // BUSER max index |
localparam ARUSER_MAX = ARUSER_WIDTH ? ARUSER_WIDTH-1:0; // ARUSER max index |
localparam RUSER_MAX = RUSER_WIDTH ? RUSER_WIDTH-1:0; // RUSER max index |
|
|
// -------------------------------------------------------------------- |
// |
wire axi_aclk = clk_200mhz; // AXI Clock |
wire axi_aresetn = ~tb_rst; // AXI Reset |
|
tb_axi4lite_bfm_if |
#( |
.DATA_WIDTH(DATA_WIDTH), |
.WID_WIDTH(WID_WIDTH), |
.RID_WIDTH(RID_WIDTH), |
.AWUSER_WIDTH(AWUSER_WIDTH), |
.WUSER_WIDTH(WUSER_WIDTH), |
.BUSER_WIDTH(BUSER_WIDTH), |
.ARUSER_WIDTH(ARUSER_WIDTH), |
.RUSER_WIDTH(RUSER_WIDTH), |
.ADDR_WIDTH(ADDR_WIDTH), |
.EXMON_WIDTH(EXMON_WIDTH) |
) |
axi4lite_bfm |
( |
.axi_aclk(axi_aclk), |
.axi_aresetn(axi_aresetn) |
); |
|
|
// -------------------------------------------------------------------- |
// |
wire [DATA_MAX:0] slv_reg0; |
wire [DATA_MAX:0] slv_reg1; |
wire [DATA_MAX:0] slv_reg2; |
wire [DATA_MAX:0] slv_reg3; |
|
reg_file_v1_0_S00_AXI |
dut |
( |
.S_AXI_ACLK(axi_aclk), |
.S_AXI_ARESETN(axi_aresetn), |
.S_AXI_AWADDR(axi4lite_bfm.axi_awaddr[3:0]), |
.S_AXI_AWPROT(axi4lite_bfm.axi_awprot), |
.S_AXI_AWVALID(axi4lite_bfm.axi_awvalid), |
.S_AXI_AWREADY(axi4lite_bfm.axi_awready), |
.S_AXI_WDATA(axi4lite_bfm.axi_wdata), |
.S_AXI_WSTRB(axi4lite_bfm.axi_wstrb), |
.S_AXI_WVALID(axi4lite_bfm.axi_wvalid), |
.S_AXI_WREADY(axi4lite_bfm.axi_wready), |
.S_AXI_BRESP(axi4lite_bfm.axi_bresp), |
.S_AXI_BVALID(axi4lite_bfm.axi_bvalid), |
.S_AXI_BREADY(axi4lite_bfm.axi_bready), |
.S_AXI_ARADDR(axi4lite_bfm.axi_araddr[3:0]), |
.S_AXI_ARPROT(axi4lite_bfm.axi_arprot), |
.S_AXI_ARVALID(axi4lite_bfm.axi_arvalid), |
.S_AXI_ARREADY(axi4lite_bfm.axi_arready), |
.S_AXI_RDATA(axi4lite_bfm.axi_rdata), |
.S_AXI_RRESP(axi4lite_bfm.axi_rresp), |
.S_AXI_RVALID(axi4lite_bfm.axi_rvalid), |
.S_AXI_RREADY(axi4lite_bfm.axi_rready), |
.slv_reg0(slv_reg0), |
.slv_reg1(slv_reg1), |
.slv_reg2(slv_reg2), |
.slv_reg3(slv_reg3) |
); |
|
|
// -------------------------------------------------------------------- |
// sim models |
// | | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ |
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
|
|
// -------------------------------------------------------------------- |
// |
Axi4PC_ace |
#( |
.DATA_WIDTH(DATA_WIDTH), |
.WID_WIDTH(WID_WIDTH), |
.RID_WIDTH(RID_WIDTH), |
.AWUSER_WIDTH(AWUSER_WIDTH), |
.WUSER_WIDTH(WUSER_WIDTH), |
.BUSER_WIDTH(BUSER_WIDTH), |
.ARUSER_WIDTH(ARUSER_WIDTH), |
.RUSER_WIDTH(RUSER_WIDTH), |
.MAXRBURSTS(MAXRBURSTS), |
.MAXWBURSTS(MAXWBURSTS), |
.MAXWAITS(MAXWAITS), |
.RecommendOn(RecommendOn), |
.RecMaxWaitOn(RecMaxWaitOn), |
.PROTOCOL(PROTOCOL), |
.ADDR_WIDTH(ADDR_WIDTH), |
.EXMON_WIDTH(EXMON_WIDTH) |
) |
Axi4PC_ace_i |
( |
.ACLK(axi_aclk), |
.ARESETn(axi_aresetn), |
.AWID(axi4lite_bfm.axi_awid), |
.AWADDR(axi4lite_bfm.axi_awaddr), |
.AWLEN(axi4lite_bfm.axi_awlen), |
.AWSIZE(axi4lite_bfm.axi_awsize), |
.AWBURST(axi4lite_bfm.axi_awburst), |
.AWCACHE(axi4lite_bfm.axi_awcache), |
.AWPROT(axi4lite_bfm.axi_awprot), |
.AWQOS(axi4lite_bfm.axi_awqos), |
.AWREGION(axi4lite_bfm.axi_awregion), |
.AWLOCK(axi4lite_bfm.axi_awlock), |
.AWUSER(axi4lite_bfm.axi_awuser), |
.AWVALID(axi4lite_bfm.axi_awvalid), |
.AWREADY(axi4lite_bfm.axi_awready), |
.WDATA(axi4lite_bfm.axi_wdata), |
.WSTRB(axi4lite_bfm.axi_wstrb), |
.WUSER(axi4lite_bfm.axi_wuser), |
.WLAST(axi4lite_bfm.axi_wlast), |
.WVALID(axi4lite_bfm.axi_wvalid), |
.WREADY(axi4lite_bfm.axi_wready), |
.BID(axi4lite_bfm.axi_bid), |
.BRESP(axi4lite_bfm.axi_bresp), |
.BUSER(axi4lite_bfm.axi_buser), |
.BVALID(axi4lite_bfm.axi_bvalid), |
.BREADY(axi4lite_bfm.axi_bready), |
.ARID(axi4lite_bfm.axi_arid), |
.ARADDR(axi4lite_bfm.axi_araddr), |
.ARLEN(axi4lite_bfm.axi_arlen), |
.ARSIZE(axi4lite_bfm.axi_arsize), |
.ARBURST(axi4lite_bfm.axi_arburst), |
.ARCACHE(axi4lite_bfm.axi_arcache), |
.ARQOS(axi4lite_bfm.axi_arqos), |
.ARREGION(axi4lite_bfm.axi_arregion), |
.ARPROT(axi4lite_bfm.axi_arprot), |
.ARLOCK(axi4lite_bfm.axi_arlock), |
.ARUSER(axi4lite_bfm.axi_aruser), |
.ARVALID(axi4lite_bfm.axi_arvalid), |
.ARREADY(axi4lite_bfm.axi_arready), |
.RID(axi4lite_bfm.axi_rid), |
.RDATA(axi4lite_bfm.axi_rdata), |
.RRESP(axi4lite_bfm.axi_rresp), |
.RUSER(axi4lite_bfm.axi_ruser), |
.RLAST(axi4lite_bfm.axi_rlast), |
.RVALID(axi4lite_bfm.axi_rvalid), |
.RREADY(axi4lite_bfm.axi_rready), |
.CACTIVE(axi4lite_bfm.axi_cactive), |
.CSYSREQ(axi4lite_bfm.axi_csysreq), |
.CSYSACK(axi4lite_bfm.axi_csysack) |
); |
|
|
|
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ |
// | | | | | | | | | | | | | | | | | |
// sim models |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// debug wires |
|
|
|
// -------------------------------------------------------------------- |
// test |
the_test test( tb_clk, tb_rst ); |
|
initial |
begin |
|
test.run_the_test(); |
|
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench done.", $time); |
$display("^^^---------------------------------"); |
|
$display("^^^---------------------------------"); |
|
`ifdef MAKEFILE_TEST_RUN |
$finish(); |
`else |
$stop(); |
`endif |
|
end |
|
endmodule |
|
|
|
/AXI/sim/src/tb_axi4lite_bfm_if.sv
0,0 → 1,316
// -------------------------------------------------------------------- |
// |
|
|
interface |
tb_axi4lite_bfm_if |
#( |
DATA_WIDTH = 64, // data bus width, default = 64-bit |
WID_WIDTH = 4, // (A|W|R|B)ID width |
RID_WIDTH = 4, // (A|W|R|B)ID width |
AWUSER_WIDTH = 32, // width of the user AW sideband field |
WUSER_WIDTH = 32, // width of the user W sideband field |
BUSER_WIDTH = 32, // width of the user B sideband field |
ARUSER_WIDTH = 32, // width of the user AR sideband field |
RUSER_WIDTH = 32, // width of the user R sideband field |
ADDR_WIDTH = 32, // address bus width, default = 32-bit |
EXMON_WIDTH = 4 // exclusive access width, default = 4-bit |
) |
( |
input logic axi_aclk, |
input logic axi_aresetn |
); |
|
// -------------------------------------------------------------------- |
// |
import qaz_axi4_bfm_pkg::*; |
|
|
// -------------------------------------------------------------------- |
// INDEX: - Calculated (user should not override) |
// ===== |
localparam DATA_MAX = DATA_WIDTH-1; // data max index |
localparam ADDR_MAX = ADDR_WIDTH-1; // address max index |
localparam STRB_WIDTH = DATA_WIDTH/8; // WSTRB width |
localparam STRB_MAX = STRB_WIDTH-1; // WSTRB max index |
localparam STRB_1 = {{STRB_MAX{1'b0}}, 1'b1}; // value 1 in strobe width |
localparam ID_MAX_R = RID_WIDTH? RID_WIDTH-1:0; // ID max index |
localparam ID_MAX_W = WID_WIDTH? WID_WIDTH-1:0; // ID max index |
localparam ID_MAX = ID_MAX_W > ID_MAX_R ? ID_MAX_W : ID_MAX_R; // ID max index |
localparam EXMON_MAX = EXMON_WIDTH-1; // EXMON max index |
localparam EXMON_HI = {EXMON_WIDTH{1'b1}}; // EXMON max value |
|
localparam AWUSER_MAX = AWUSER_WIDTH ? AWUSER_WIDTH-1:0; // AWUSER max index |
localparam WUSER_MAX = WUSER_WIDTH ? WUSER_WIDTH-1:0; // WUSER max index |
localparam BUSER_MAX = BUSER_WIDTH ? BUSER_WIDTH-1:0; // BUSER max index |
localparam ARUSER_MAX = ARUSER_WIDTH ? ARUSER_WIDTH-1:0; // ARUSER max index |
localparam RUSER_MAX = RUSER_WIDTH ? RUSER_WIDTH-1:0; // RUSER max index |
|
|
// -------------------------------------------------------------------- |
// |
// INDEX: - Write Address Channel |
// ===== |
logic [ID_MAX_W:0] axi_awid; |
logic [ADDR_MAX:0] axi_awaddr; |
logic [7:0] axi_awlen; |
logic [2:0] axi_awsize; |
logic [1:0] axi_awburst; |
logic [3:0] axi_awcache; |
logic [2:0] axi_awprot; |
logic [3:0] axi_awqos; |
logic [3:0] axi_awregion; |
logic axi_awlock; |
logic [AWUSER_MAX:0] axi_awuser; |
logic axi_awvalid; |
logic axi_awready; |
|
// INDEX: - Write Data Channel |
// ===== |
logic [DATA_MAX:0] axi_wdata; |
logic [STRB_MAX:0] axi_wstrb; |
logic [WUSER_MAX:0] axi_wuser; |
logic axi_wlast; |
logic axi_wvalid; |
logic axi_wready; |
|
// INDEX: - Write Response Channel |
// ===== |
logic [ID_MAX_W:0] axi_bid; |
logic [1:0] axi_bresp; |
logic [BUSER_MAX:0] axi_buser; |
logic axi_bvalid; |
logic axi_bready; |
|
// INDEX: - Read Address Channel |
// ===== |
logic [ID_MAX_R:0] axi_arid; |
logic [ADDR_MAX:0] axi_araddr; |
logic [7:0] axi_arlen; |
logic [2:0] axi_arsize; |
logic [1:0] axi_arburst; |
logic [3:0] axi_arcache; |
logic [3:0] axi_arqos; |
logic [3:0] axi_arregion; |
logic [2:0] axi_arprot; |
logic axi_arlock; |
logic [ARUSER_MAX:0] axi_aruser; |
logic axi_arvalid; |
logic axi_arready; |
|
// INDEX: - Read Data Channel |
// ===== |
logic [ID_MAX_R:0] axi_rid; |
logic [DATA_MAX:0] axi_rdata; |
logic [1:0] axi_rresp; |
logic [RUSER_MAX:0] axi_ruser; |
logic axi_rlast; |
logic axi_rvalid; |
logic axi_rready; |
|
// INDEX: - Low Power Interface |
// ===== |
logic axi_cactive; |
logic axi_csysreq; |
logic axi_csysack; |
|
|
// -------------------------------------------------------------------- |
// |
default clocking cb @(posedge axi_aclk); |
output axi_araddr; |
output axi_arprot; |
input axi_arready; |
output axi_arvalid; |
output axi_awaddr; |
output axi_awprot; |
input axi_awready; |
output axi_awvalid; |
output axi_bready; |
input axi_bresp; |
input axi_bvalid; |
input axi_rdata; |
output axi_rready; |
input axi_rresp; |
input axi_rvalid; |
output axi_wdata; |
input axi_wready; |
output axi_wstrb; |
output axi_wvalid; |
output axi_arlen; |
output axi_arlock; |
output axi_arid; |
output axi_arsize; |
output axi_arqos; |
output axi_arregion; |
output axi_arcache; |
output axi_arburst; |
output axi_aruser; |
output axi_wlast; |
output axi_wuser; |
output axi_cactive; |
output axi_csysreq; |
output axi_csysack; |
output axi_awburst; |
output axi_awcache; |
output axi_awid; |
output axi_awlen; |
output axi_awlock; |
output axi_awqos; |
output axi_awregion; |
output axi_awsize; |
output axi_awuser; |
endclocking |
|
|
// -------------------------------------------------------------------- |
// |
class qaz_axi4_bfm extends v_qaz_axi4_bfm; |
|
|
// -------------------------------------------------------------------- |
// |
task init; |
|
cb.axi_araddr <= 0; |
cb.axi_arprot <= 0; |
cb.axi_arvalid <= 0; |
cb.axi_awaddr <= 0; |
cb.axi_awprot <= 0; |
cb.axi_awvalid <= 0; |
cb.axi_bready <= 0; |
cb.axi_rready <= 0; |
cb.axi_wdata <= 0; |
cb.axi_wstrb <= 0; |
cb.axi_wvalid <= 0; |
|
cb.axi_arlen <= 0; |
cb.axi_arlock <= 0; |
cb.axi_arid <= 0; |
cb.axi_arsize <= 3'b010; |
cb.axi_arqos <= 0; |
cb.axi_arregion <= 0; |
cb.axi_arcache <= 0; |
cb.axi_arburst <= 1; |
cb.axi_aruser <= 0; |
|
axi_ruser <= 0; |
axi_rlast <= 1; |
axi_rid <= 0; |
axi_bid <= 0; |
axi_buser <= 0; |
|
cb.axi_wlast <= 1; |
cb.axi_wuser <= 0; |
|
cb.axi_awburst <= 1; |
cb.axi_awcache <= 0; |
cb.axi_awid <= 0; |
cb.axi_awlen <= 0; |
cb.axi_awlock <= 0; |
cb.axi_awqos <= 0; |
cb.axi_awregion <= 0; |
cb.axi_awsize <= 3'b010; |
cb.axi_awuser <= 0; |
|
cb.axi_cactive <= 1; |
cb.axi_csysreq <= 1; |
cb.axi_csysack <= 1; |
|
endtask: init |
|
|
// -------------------------------------------------------------------- |
// |
task |
read |
( |
input int addr, |
output int data |
); |
|
cb.axi_araddr <= addr; |
cb.axi_arprot <= 0; |
|
##0; |
cb.axi_arvalid <= 1; |
##1; |
|
wait( cb.axi_arready ); |
cb.axi_arvalid <= 0; |
|
// optional delay here |
cb.axi_rready <= 1; |
##1; |
|
wait( cb.axi_rvalid ); |
data = axi_rdata; |
|
// optional delay here |
cb.axi_rready <= 0; |
|
$strobe("^^^ %16.t | %m | 0x%h @ 0x%h", $time, data, addr ); |
|
endtask: read |
|
|
// -------------------------------------------------------------------- |
// |
task |
write |
( |
input int addr, |
input int data, |
input int wstrb |
); |
|
$strobe("^^^ %16.t | %m | 0x%h @ 0x%h | %b", $time, data, addr, wstrb ); |
|
cb.axi_bready <= 0; |
cb.axi_awaddr <= addr; |
cb.axi_wstrb <= wstrb; |
cb.axi_awprot <= 0; |
cb.axi_awvalid <= 0; |
|
##0; |
cb.axi_awvalid <= 1; |
##1; |
|
// optional delay here |
axi_wdata = data; |
cb.axi_wvalid <= 1; |
|
wait( cb.axi_awready ); |
cb.axi_awvalid <= 0; |
|
wait( cb.axi_wready ); |
cb.axi_wvalid <= 0; |
|
wait( cb.axi_bvalid ); |
|
// optional delay here |
cb.axi_bready <= 1; |
|
fork |
begin |
##1; |
cb.axi_bready <= 0; |
end |
join_none |
|
endtask: write |
|
endclass: qaz_axi4_bfm |
|
|
// -------------------------------------------------------------------- |
// |
qaz_axi4_bfm bfm = new; |
|
initial |
bfm.init(); |
|
|
endinterface: tb_axi4lite_bfm_if |
|
|
/AXI/sim/src/wb_slave_model.v
0,0 → 1,161
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`timescale 1ns/10ps |
|
|
module wb_slave_model( clk_i, rst_i, dat_o, dat_i, adr_i, |
cyc_i, stb_i, we_i, sel_i, |
ack_o, err_o, rty_o ); |
|
parameter DWIDTH = 8; |
parameter AWIDTH = 8; |
parameter ACK_DELAY = 2; |
parameter SLAVE_RAM_INIT = "wb_slave_model.txt"; |
|
input clk_i; |
input rst_i; |
output [DWIDTH-1:0] dat_o; |
input [DWIDTH-1:0] dat_i; |
input [AWIDTH-1:0] adr_i; |
input cyc_i; |
input stb_i; |
input we_i; |
input [( (DWIDTH/8) - 1 ):0] sel_i; |
output ack_o; |
output err_o; |
output rty_o; |
|
|
|
|
|
// -------------------------------------------------------------------- |
// slave ram |
reg [7:0] ram[2**AWIDTH-1:0]; |
|
initial |
$readmemh( SLAVE_RAM_INIT, ram ); |
|
// -------------------------------------------------------------------- |
// |
generate |
case( DWIDTH ) |
8: begin |
initial |
$display( "###- wb_slave_model(): WISHBONE 8 BIT SLAVE MODEL INSTANTIATED " ); |
|
always @ (posedge clk_i) |
if (we_i & cyc_i & stb_i & sel_i[0]) |
ram[adr_i] <= dat_i[7:0]; |
|
assign dat_o = ram[adr_i]; |
|
end |
|
16: begin |
initial |
$display( "###- wb_slave_model(): WISHBONE 16 BIT SLAVE MODEL INSTANTIATED " ); |
|
always @ (posedge clk_i) |
if (we_i & cyc_i & stb_i & sel_i[0]) |
ram[{adr_i[AWIDTH-1:1], 1'b0}] <= dat_i[7:0]; |
|
always @ (posedge clk_i) |
if (we_i & cyc_i & stb_i & sel_i[1]) |
ram[{adr_i[AWIDTH-1:1], 1'b1}] <= dat_i[15:8]; |
|
assign dat_o = { ram[{adr_i[AWIDTH-1:1], 1'b1}], ram[{adr_i[AWIDTH-1:1], 1'b0}] }; |
|
end |
|
32: begin |
initial |
$display( "###- wb_slave_model(): WISHBONE 32 BIT SLAVE MODEL INSTANTIATED " ); |
|
always @ (posedge clk_i) |
if (we_i & cyc_i & stb_i & sel_i[0]) |
ram[{adr_i[AWIDTH-1:2], 2'b00}] <= dat_i[7:0]; |
|
always @ (posedge clk_i) |
if (we_i & cyc_i & stb_i & sel_i[1]) |
ram[{adr_i[AWIDTH-1:2], 2'b01}] <= dat_i[15:8]; |
|
always @ (posedge clk_i) |
if (we_i & cyc_i & stb_i & sel_i[2]) |
ram[{adr_i[AWIDTH-1:2], 2'b10}] <= dat_i[23:16]; |
|
always @ (posedge clk_i) |
if (we_i & cyc_i & stb_i & sel_i[3]) |
ram[{adr_i[AWIDTH-1:2], 2'b11}] <= dat_i[31:24]; |
|
assign dat_o = { ram[{adr_i[AWIDTH-1:2], 2'b11}], ram[{adr_i[AWIDTH-1:2], 2'b10}], ram[{adr_i[AWIDTH-1:2], 2'b01}], ram[{adr_i[AWIDTH-1:2], 2'b00}] }; |
|
end |
|
default: begin |
localparam SLAVE_SIZE = -1; |
initial |
begin |
$display( "!!!- wb_slave_model(): invalad DWIDTH parameter" ); |
$stop(); |
end |
end |
endcase |
endgenerate |
|
|
// -------------------------------------------------------------------- |
// ack delay |
reg ack_delayed; |
|
initial |
ack_delayed = 1'b0; |
|
always @(posedge clk_i or cyc_i or stb_i) |
begin |
if(cyc_i & stb_i) |
begin |
ack_delayed = 1'b0; |
repeat(ACK_DELAY) @(posedge clk_i); |
if(cyc_i & stb_i) |
ack_delayed = 1'b1; |
else |
ack_delayed = 1'b0; |
end |
else |
ack_delayed = 1'b0; |
end |
|
// -------------------------------------------------------------------- |
// assign outputs |
assign ack_o = ack_delayed; |
assign err_o = 1'b0; |
assign rty_o = 1'b0; |
|
|
endmodule |
/AXI/sim/src/tb_unit_debug_unit_wb_axi4lite_bridge.sv
0,0 → 1,338
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
`ifndef AXI4PC_TYPES |
`include "Axi4PC_ace_defs.v" |
`endif |
|
`ifndef AXI4PC_MESSAGES |
`include "Axi4PC_ace_message_defs.v" |
`endif |
|
|
module tb_top(); |
|
// -------------------------------------------------------------------- |
// test bench clock & reset |
wire clk_200mhz; |
wire tb_clk = clk_200mhz; |
wire tb_rst; |
|
tb_base #( .PERIOD(5000) ) tb( clk_200mhz, tb_rst ); |
|
wire clk_125mhz; |
tb_clk #( .PERIOD(8000) ) tb_clk_125mhz( clk_125mhz ); |
|
|
//------------------------------------------------------------------------------ |
// INDEX: 1) Parameters |
//------------------------------------------------------------------------------ |
|
// INDEX: - Configurable (user can set) |
// ===== |
// Parameters below can be set by the user. |
|
// Set DATA_WIDTH to the data-bus width required |
localparam DATA_WIDTH = 32; // data bus width, default = 64-bit |
|
// Select the number of channel ID bits required |
localparam WID_WIDTH = 4; // (A|W|R|B)ID width |
localparam RID_WIDTH = 4; // (A|W|R|B)ID width |
|
// Select the size of the USER buses, default = 32-bit |
localparam AWUSER_WIDTH = 32; // width of the user AW sideband field |
localparam WUSER_WIDTH = 32; // width of the user W sideband field |
localparam BUSER_WIDTH = 32; // width of the user B sideband field |
localparam ARUSER_WIDTH = 32; // width of the user AR sideband field |
localparam RUSER_WIDTH = 32; // width of the user R sideband field |
|
// Size of CAMs for storing outstanding read bursts, this should match or |
// exceed the number of outstanding read addresses accepted into the slave |
// interface |
localparam MAXRBURSTS = 16; |
|
// Size of CAMs for storing outstanding write bursts, this should match or |
// exceed the number of outstanding write bursts into the slave interface |
localparam MAXWBURSTS = 16; |
|
// Maximum number of cycles between VALID -> READY high before a warning is |
// generated |
localparam MAXWAITS = 16; |
|
// Recommended Rules Enable |
// enable/disable reporting of all AXI4_REC*_* rules |
localparam RecommendOn = 1'b1; |
// enable/disable reporting of just AXI4_REC*_MAX_WAIT rules |
localparam RecMaxWaitOn = 1'b1; |
|
|
// Set the protocol - used to disable some AXI4 checks for ACE |
localparam PROTOCOL = `AXI4PC_AMBA_ACE_LITE; |
|
// Set ADDR_WIDTH to the address-bus width required |
localparam ADDR_WIDTH = 32; // address bus width, default = 32-bit |
|
// Set EXMON_WIDTH to the exclusive access monitor width required |
localparam EXMON_WIDTH = 4; // exclusive access width, default = 4-bit |
|
// INDEX: - Calculated (user should not override) |
// ===== |
// Do not override the following parameters: they must be calculated exactly |
// as shown below |
localparam DATA_MAX = DATA_WIDTH-1; // data max index |
localparam ADDR_MAX = ADDR_WIDTH-1; // address max index |
localparam STRB_WIDTH = DATA_WIDTH/8; // WSTRB width |
localparam STRB_MAX = STRB_WIDTH-1; // WSTRB max index |
localparam STRB_1 = {{STRB_MAX{1'b0}}, 1'b1}; // value 1 in strobe width |
localparam ID_MAX_R = RID_WIDTH? RID_WIDTH-1:0; // ID max index |
localparam ID_MAX_W = WID_WIDTH? WID_WIDTH-1:0; // ID max index |
localparam ID_MAX = ID_MAX_W > ID_MAX_R ? ID_MAX_W : ID_MAX_R; // ID max index |
localparam EXMON_MAX = EXMON_WIDTH-1; // EXMON max index |
localparam EXMON_HI = {EXMON_WIDTH{1'b1}}; // EXMON max value |
|
localparam AWUSER_MAX = AWUSER_WIDTH ? AWUSER_WIDTH-1:0; // AWUSER max index |
localparam WUSER_MAX = WUSER_WIDTH ? WUSER_WIDTH-1:0; // WUSER max index |
localparam BUSER_MAX = BUSER_WIDTH ? BUSER_WIDTH-1:0; // BUSER max index |
localparam ARUSER_MAX = ARUSER_WIDTH ? ARUSER_WIDTH-1:0; // ARUSER max index |
localparam RUSER_MAX = RUSER_WIDTH ? RUSER_WIDTH-1:0; // RUSER max index |
|
|
// -------------------------------------------------------------------- |
// |
wire axi_aclk = clk_200mhz; // AXI Clock |
wire axi_aresetn = ~tb_rst; // AXI Reset |
|
tb_axi4lite_bfm_if |
#( |
.DATA_WIDTH(DATA_WIDTH), |
.WID_WIDTH(WID_WIDTH), |
.RID_WIDTH(RID_WIDTH), |
.AWUSER_WIDTH(AWUSER_WIDTH), |
.WUSER_WIDTH(WUSER_WIDTH), |
.BUSER_WIDTH(BUSER_WIDTH), |
.ARUSER_WIDTH(ARUSER_WIDTH), |
.RUSER_WIDTH(RUSER_WIDTH), |
.ADDR_WIDTH(ADDR_WIDTH), |
.EXMON_WIDTH(EXMON_WIDTH) |
) |
axi4lite_bfm |
( |
.axi_aclk(axi_aclk), |
.axi_aresetn(axi_aresetn) |
); |
|
|
// -------------------------------------------------------------------- |
// |
localparam WB_DATA_WIDTH = 32; |
localparam WB_ADDR_WIDTH = 4; |
|
wire wb_ack_i; |
wire wb_err_i; |
wire wb_rty_i; |
wire wb_stall_i = 1; |
wire [WB_DATA_WIDTH-1:0] wb_dat_i; |
wire wb_cyc_o; |
wire [WB_ADDR_WIDTH-1:0] wb_adr_o; |
wire wb_stb_o; |
wire wb_we_o; |
wire [3:0] wb_sel_o; |
wire [WB_DATA_WIDTH-1:0] wb_dat_o; |
|
wire wb_clk_i = axi_aclk; |
wire wb_rst_i = ~axi_aresetn; |
|
wb_axi4lite_bridge |
#( |
.DATA_WIDTH(WB_DATA_WIDTH), |
.ADDR_WIDTH(WB_ADDR_WIDTH) |
) |
dut |
( |
.axi_awaddr(axi4lite_bfm.axi_awaddr[3:0]), |
.axi_awprot(axi4lite_bfm.axi_awprot), |
.axi_awvalid(axi4lite_bfm.axi_awvalid), |
.axi_awready(axi4lite_bfm.axi_awready), |
.axi_wdata(axi4lite_bfm.axi_wdata), |
.axi_wstrb(axi4lite_bfm.axi_wstrb), |
.axi_wvalid(axi4lite_bfm.axi_wvalid), |
.axi_wready(axi4lite_bfm.axi_wready), |
.axi_bresp(axi4lite_bfm.axi_bresp), |
.axi_bvalid(axi4lite_bfm.axi_bvalid), |
.axi_bready(axi4lite_bfm.axi_bready), |
.axi_araddr(axi4lite_bfm.axi_araddr[3:0]), |
.axi_arprot(axi4lite_bfm.axi_arprot), |
.axi_arvalid(axi4lite_bfm.axi_arvalid), |
.axi_arready(axi4lite_bfm.axi_arready), |
.axi_rdata(axi4lite_bfm.axi_rdata), |
.axi_rresp(axi4lite_bfm.axi_rresp), |
.axi_rvalid(axi4lite_bfm.axi_rvalid), |
.axi_rready(axi4lite_bfm.axi_rready), |
|
.axi_aclk(axi_aclk), |
.axi_aresetn(axi_aresetn), |
|
.wb_ack_i(wb_ack_i), |
.wb_err_i(wb_err_i), |
.wb_rty_i(wb_rty_i), |
.wb_stall_i(wb_stall_i), |
.wb_dat_i(wb_dat_i), |
.wb_cyc_o(wb_cyc_o), |
.wb_adr_o(wb_adr_o), |
.wb_stb_o(wb_stb_o), |
.wb_we_o(wb_we_o), |
.wb_sel_o(wb_sel_o), |
.wb_dat_o(wb_dat_o) |
); |
|
|
// -------------------------------------------------------------------- |
// sim models |
// | | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ |
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
|
|
// -------------------------------------------------------------------- |
// |
Axi4PC_ace |
#( |
.DATA_WIDTH(DATA_WIDTH), |
.WID_WIDTH(WID_WIDTH), |
.RID_WIDTH(RID_WIDTH), |
.AWUSER_WIDTH(AWUSER_WIDTH), |
.WUSER_WIDTH(WUSER_WIDTH), |
.BUSER_WIDTH(BUSER_WIDTH), |
.ARUSER_WIDTH(ARUSER_WIDTH), |
.RUSER_WIDTH(RUSER_WIDTH), |
.MAXRBURSTS(MAXRBURSTS), |
.MAXWBURSTS(MAXWBURSTS), |
.MAXWAITS(MAXWAITS), |
.RecommendOn(RecommendOn), |
.RecMaxWaitOn(RecMaxWaitOn), |
.PROTOCOL(PROTOCOL), |
.ADDR_WIDTH(ADDR_WIDTH), |
.EXMON_WIDTH(EXMON_WIDTH) |
) |
Axi4PC_ace_i |
( |
.ACLK(axi_aclk), |
.ARESETn(axi_aresetn), |
.AWID(axi4lite_bfm.axi_awid), |
.AWADDR(axi4lite_bfm.axi_awaddr), |
.AWLEN(axi4lite_bfm.axi_awlen), |
.AWSIZE(axi4lite_bfm.axi_awsize), |
.AWBURST(axi4lite_bfm.axi_awburst), |
.AWCACHE(axi4lite_bfm.axi_awcache), |
.AWPROT(axi4lite_bfm.axi_awprot), |
.AWQOS(axi4lite_bfm.axi_awqos), |
.AWREGION(axi4lite_bfm.axi_awregion), |
.AWLOCK(axi4lite_bfm.axi_awlock), |
.AWUSER(axi4lite_bfm.axi_awuser), |
.AWVALID(axi4lite_bfm.axi_awvalid), |
.AWREADY(axi4lite_bfm.axi_awready), |
.WDATA(axi4lite_bfm.axi_wdata), |
.WSTRB(axi4lite_bfm.axi_wstrb), |
.WUSER(axi4lite_bfm.axi_wuser), |
.WLAST(axi4lite_bfm.axi_wlast), |
.WVALID(axi4lite_bfm.axi_wvalid), |
.WREADY(axi4lite_bfm.axi_wready), |
.BID(axi4lite_bfm.axi_bid), |
.BRESP(axi4lite_bfm.axi_bresp), |
.BUSER(axi4lite_bfm.axi_buser), |
.BVALID(axi4lite_bfm.axi_bvalid), |
.BREADY(axi4lite_bfm.axi_bready), |
.ARID(axi4lite_bfm.axi_arid), |
.ARADDR(axi4lite_bfm.axi_araddr), |
.ARLEN(axi4lite_bfm.axi_arlen), |
.ARSIZE(axi4lite_bfm.axi_arsize), |
.ARBURST(axi4lite_bfm.axi_arburst), |
.ARCACHE(axi4lite_bfm.axi_arcache), |
.ARQOS(axi4lite_bfm.axi_arqos), |
.ARREGION(axi4lite_bfm.axi_arregion), |
.ARPROT(axi4lite_bfm.axi_arprot), |
.ARLOCK(axi4lite_bfm.axi_arlock), |
.ARUSER(axi4lite_bfm.axi_aruser), |
.ARVALID(axi4lite_bfm.axi_arvalid), |
.ARREADY(axi4lite_bfm.axi_arready), |
.RID(axi4lite_bfm.axi_rid), |
.RDATA(axi4lite_bfm.axi_rdata), |
.RRESP(axi4lite_bfm.axi_rresp), |
.RUSER(axi4lite_bfm.axi_ruser), |
.RLAST(axi4lite_bfm.axi_rlast), |
.RVALID(axi4lite_bfm.axi_rvalid), |
.RREADY(axi4lite_bfm.axi_rready), |
.CACTIVE(axi4lite_bfm.axi_cactive), |
.CSYSREQ(axi4lite_bfm.axi_csysreq), |
.CSYSACK(axi4lite_bfm.axi_csysack) |
); |
|
|
// -------------------------------------------------------------------- |
// |
|
wb_slave_model |
#( |
.DWIDTH(WB_DATA_WIDTH), |
.AWIDTH(WB_ADDR_WIDTH), |
.ACK_DELAY(0) |
) |
wb_slave_model_i |
( |
.clk_i(wb_clk_i), |
.rst_i(wb_rst_i), |
.dat_o(wb_dat_i), |
.dat_i(wb_dat_o), |
.adr_i(wb_adr_o), |
.cyc_i(wb_cyc_o), |
.stb_i(wb_stb_o), |
.we_i(wb_we_o), |
.sel_i(wb_sel_o), |
.ack_o(wb_ack_i), |
.err_o(wb_err_i), |
.rty_o(wb_rty_i) |
); |
|
|
|
|
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ |
// | | | | | | | | | | | | | | | | | |
// sim models |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// debug wires |
|
|
|
// -------------------------------------------------------------------- |
// test |
the_test test( tb_clk, tb_rst ); |
|
initial |
begin |
|
test.run_the_test(); |
|
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench done.", $time); |
$display("^^^---------------------------------"); |
|
$display("^^^---------------------------------"); |
|
`ifdef MAKEFILE_TEST_RUN |
$finish(); |
`else |
$stop(); |
`endif |
|
end |
|
endmodule |
|
|
|
/AXI/sim/src/qaz_axi4_bfm_pkg.sv
0,0 → 1,14
// -------------------------------------------------------------------- |
// |
|
|
package qaz_axi4_bfm_pkg; |
|
virtual class v_qaz_axi4_bfm; |
pure virtual task init(); |
pure virtual task write( input int addr, input int data, input int wstrb ); |
pure virtual task read( input int addr, output int data ); |
endclass: v_qaz_axi4_bfm |
|
endpackage: qaz_axi4_bfm_pkg |
|
/AXI/sim/src/BP065-BU-01000-r0p1-00rel0/BP065-BU-01000-r0p1-00rel0.txt
0,0 → 1,6
|
|
|
goto http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0576b/index.html to download. requires |
an free account to login. |
|
/AXI/sim/libs/sim_verilog/tb_lib.f
0,0 → 1,16
# |
|
-mfcu |
|
${ROOT_DIR}/tb_class/src/tb_clk_class.sv |
|
${ROOT_DIR}/tb_class/src/tb_clk.sv |
${ROOT_DIR}/tb_class/src/tb_base.sv |
|
|
|
|
|
|
|
|
/AXI/sim/libs/sim_verilog/wishbone.f
0,0 → 1,8
# |
|
|
${PROJECT_DIR}/sim/src/wb_slave_model.v |
|
|
|
|
/AXI/sim/libs/sim_verilog/axi4_bfm.f
0,0 → 1,12
# |
|
+incdir+${PROJECT_DIR}/sim/src/BP065-BU-01000-r0p1-00rel0/sva |
|
${PROJECT_DIR}/sim/src/BP065-BU-01000-r0p1-00rel0/sva/Axi4PC_ace.sv |
|
${PROJECT_DIR}/sim/src/qaz_axi4_bfm_pkg.sv |
${PROJECT_DIR}/sim/src/tb_axi4lite_bfm_if.sv |
|
|
|
|
/AXI/sim/libs/FPGA_verilog/FPGA_AXI.f
0,0 → 1,17
# |
|
${PROJECT_DIR}/src/reg_file_v1_0_S00_AXI.v |
|
${PROJECT_DIR}/src/wb_axi4lite_bridge.v |
${PROJECT_DIR}/src/wb_axi4lite_read_fsm.v |
${PROJECT_DIR}/src/wb_axi4lite_write_fsm.v |
${PROJECT_DIR}/src/wb_master_fsm.v |
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|