URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
Compare Revisions
- This comparison shows the changes necessary to convert path
/qaz_libs/trunk
- from Rev 48 to Rev 49
- ↔ Reverse comparison
Rev 48 → Rev 49
/BFM/sim/tests/tb_axis_video_frame/t_debug.svh
54,11 → 54,7
fork |
s_seq.start(env_h.s_agent_h.sequencer_h); |
join_none |
seq.init( env_h.cfg_h.m_cfg_h.pixels_per_line |
, env_h.cfg_h.m_cfg_h.lines_per_frame |
, env_h.cfg_h.m_cfg_h.bits_per_pixel |
, env_h.cfg_h.m_cfg_h.pixels_per_clk |
); |
seq.init(env_h.cfg_h.m_cfg_h.c_h); |
phase.raise_objection(this); |
seq.start(env_h.m_agent_h.sequencer_h); |
phase.drop_objection(this); |
/BFM/src/anf/anf_pkg.sv
0,0 → 1,41
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2019 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
package anf_pkg; |
import uvm_pkg::*; |
`include "uvm_macros.svh" |
import video_frame_pkg::*; |
import avf_pkg::*; |
|
// -------------------------------------------------------------------- |
`include "numeric_array.svh" |
`include "numeric_frame.svh" |
`include "s_anf_api.svh" |
`include "s_anf_base.svh" |
|
// -------------------------------------------------------------------- |
endpackage |
/BFM/src/anf/numeric_array.svh
0,0 → 1,120
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2019 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
typedef int array_shape_t[]; // same shape convention as numpy |
typedef int array_index_t[]; |
|
class numeric_array #(type T = shortreal); |
array_shape_t shape; |
int dim; |
T a_1d[]; |
T a_2d[][]; |
T a_3d[][][]; |
|
// -------------------------------------------------------------------- |
function void set_entry(array_index_t i, T value); |
case(dim) |
1: a_1d[i[0]] = value; |
2: a_2d[i[0]][i[1]] = value; |
3: a_3d[i[0]][i[1]][i[2]] = value; //[z][y][x] |
default: $stop; // not supported |
endcase |
endfunction |
|
// -------------------------------------------------------------------- |
function T get_entry(array_index_t i); |
case(dim) |
1: get_entry = a_1d[i[0]]; |
2: get_entry = a_2d[i[0]][i[1]]; |
3: get_entry = a_3d[i[0]][i[1]][i[2]]; //[z][y][x] |
default: $stop; // not supported |
endcase |
endfunction |
|
// -------------------------------------------------------------------- |
function longint to_bits(array_index_t i); |
case(type(T)) |
type(shortreal): to_bits = $shortrealtobits(get_entry(i)); |
type(real): to_bits = $realtobits(get_entry(i)); |
default: $stop; // not supported |
endcase |
endfunction |
|
// -------------------------------------------------------------------- |
function int bits; |
case(type(T)) |
type(shortreal): bits = 32; |
type(real): bits = 64; |
default: $stop; // not supported |
endcase |
endfunction |
|
// -------------------------------------------------------------------- |
function void new_2d(array_shape_t shape); |
a_2d = new[shape[0]]; |
foreach(a_2d[y]) |
a_2d[y] = new[shape[1]]; |
endfunction |
|
// -------------------------------------------------------------------- |
function void new_3d(array_shape_t shape); |
a_3d = new[shape[0]]; |
foreach(a_3d[z]) |
begin |
a_3d[z] = new[shape[1]]; |
foreach(a_3d[z,y]) |
a_3d[z][y] = new[shape[2]]; |
end |
endfunction |
|
// -------------------------------------------------------------------- |
function void make_new; |
case(dim) |
1: a_1d = new[shape[0]]; |
2: new_2d(shape); |
3: new_3d(shape); |
default: $stop; // not supported |
endcase |
endfunction |
|
// -------------------------------------------------------------------- |
function void make_2d_constant(T value=0.0); |
$display("### value = %x", $shortrealtobits(value)); |
make_new(); |
foreach(a_2d[y,x]) |
a_2d[y][x] = value; |
endfunction |
|
// -------------------------------------------------------------------- |
function new(array_shape_t shape); |
this.shape = shape; |
this.dim = shape.size(); |
make_new(); |
endfunction |
|
// -------------------------------------------------------------------- |
endclass |
/BFM/src/anf/numeric_frame.svh
0,0 → 1,73
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2019 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
// -------------------------------------------------------------------- |
class numeric_frame #(type T = shortreal) extends video_frame_class; |
numeric_array #(T) a_h; |
|
// -------------------------------------------------------------------- |
function void init |
( |
array_shape_t shape, |
int pixels_per_clk = 1, |
string name = "" |
); |
a_h = new(shape); |
super.init |
( |
a_h.shape[1], |
a_h.shape[0], |
a_h.bits(), |
pixels_per_clk, |
name |
); |
endfunction |
|
// -------------------------------------------------------------------- |
function void make_1d_frame; |
lines = new[lines_per_frame]; |
foreach(lines[l]) |
begin |
lines[l].pixel = new[pixels_per_line]; |
foreach(lines[l].pixel[p]) |
lines[l].pixel[p] = a_h.to_bits('{(l*lines_per_frame)+p}); |
end |
endfunction |
|
// -------------------------------------------------------------------- |
function void make_2d_frame; |
lines = new[lines_per_frame]; |
foreach(lines[l]) |
begin |
lines[l].pixel = new[pixels_per_line]; |
foreach(lines[l].pixel[p]) |
lines[l].pixel[p] = a_h.to_bits('{l,p}); |
end |
endfunction |
|
// -------------------------------------------------------------------- |
endclass |
/BFM/src/anf/s_anf_api.svh
0,0 → 1,98
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2019 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
class s_anf_api #(type T = shortreal) extends s_avf_api; |
`uvm_object_param_utils(s_anf_api #(T)) |
|
|
// -------------------------------------------------------------------- |
function numeric_frame#(T) new_frame; |
numeric_frame #(T) f_h = new(); |
f_h.init( '{c_h.lines_per_frame, c_h.pixels_per_line} |
, c_h.pixels_per_clk |
); |
return f_h; |
endfunction |
|
// -------------------------------------------------------------------- |
task put_array(numeric_frame #(T) f_h); |
f_h.make_2d_frame(); |
frame_buffer.put(f_h); |
endtask |
|
// -------------------------------------------------------------------- |
task automatic put_test_pattern(string pattern, T value = 0.0); |
numeric_frame #(T) f_h = new(); |
f_h.init( '{c_h.lines_per_frame, c_h.pixels_per_line} |
, c_h.pixels_per_clk |
); |
case(pattern.tolower) |
"constant": f_h.a_h.make_2d_constant(value); |
// "counting": f_h.make_counting(); |
// "horizontal": f_h.make_horizontal(); |
// "vertical": f_h.make_vertical(); |
// "random": f_h.make_random(); |
default: `uvm_fatal(get_name(), "Pattern not supported!") |
endcase |
f_h.make_2d_frame(); |
frame_buffer.put(f_h); |
uvm_report_info(get_name(), $sformatf("| put_test_pattern(%s)", pattern.tolower)); |
endtask |
|
// -------------------------------------------------------------------- |
task load_from_file(string file_name); |
byte mem[3:0]; |
integer fd; |
integer code; |
int x, y; |
numeric_frame #(T) f_h = new(); |
|
fd = $fopen(file_name, "rb"); |
f_h.init( '{c_h.lines_per_frame, c_h.pixels_per_line} |
, c_h.pixels_per_clk |
); |
f_h = new_frame(); |
|
for(int i = 0; $feof(fd) == 0; i++) |
begin |
code = $fread(mem, fd); |
y = i / c_h.pixels_per_line; |
x = i % c_h.pixels_per_line; |
f_h.lines[y].pixel[x] = {>>{mem}}; |
end |
|
frame_buffer.put(f_h); |
$fclose(fd); |
endtask |
|
// -------------------------------------------------------------------- |
function new(string name = "s_anf_api"); |
super.new(name); |
endfunction |
|
// -------------------------------------------------------------------- |
endclass |
/BFM/src/anf/s_anf_base.svh
0,0 → 1,45
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2019 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
class s_anf_base #(type T = shortreal) extends uvm_sequence #(avf_sequence_item); |
`uvm_object_param_utils(s_anf_base #(T)) |
|
s_anf_api anf_api_h; |
|
// -------------------------------------------------------------------- |
function void init(video_frame_config c_h); |
anf_api_h = s_anf_api #(T)::type_id::create("s_anf_api"); |
anf_api_h.init(c_h); |
endfunction |
|
// -------------------------------------------------------------------- |
function new(string name = "s_anf_base"); |
super.new(name); |
endfunction |
|
// -------------------------------------------------------------------- |
endclass |
/BFM/src/axis_video_frame/avf_scoreboard.svh
69,7 → 69,7
// |
function void print_video_frame(ref video_frame_class f_h); |
string s; |
f_h.print_config(); |
$display("%s", {80{"="}}); |
$display(f_h.convert2string()); |
endfunction : print_video_frame |
|
/BFM/src/video_frame/video_frame_class.svh
97,19 → 97,21
|
// -------------------------------------------------------------------- |
function flattened_frame_t flatten_frame(); |
int i = 0; |
log.info($sformatf("%m")); |
flatten_frame = new[lines_per_frame*pixels_per_line]; |
|
foreach(this.lines[l]) |
foreach(this.lines[l].pixel[p]) |
begin |
flatten_frame[i] = this.lines[l].pixel[p]; |
i++; |
end |
flatten_frame[(l*pixels_per_line)+p] = this.lines[l].pixel[p]; |
endfunction: flatten_frame |
|
// -------------------------------------------------------------------- |
function void load_flatten_frame(flattened_frame_t a); |
make_constant(0); |
foreach(lines[l]) |
foreach(lines[l].pixel[p]) |
lines[l].pixel[p] = a[(l*pixels_per_line)+p]; |
endfunction: load_flatten_frame |
|
// -------------------------------------------------------------------- |
function void make_constant(int pixel); |
log.info($sformatf("%m")); |
this.lines = new[lines_per_frame]; |
347,14 → 349,19
endfunction: print_config |
|
// -------------------------------------------------------------------- |
function string convert2string(); |
function string convert2string(int grid=8); |
string s; |
string f =""; |
string fs = $sformatf("%%s%%%0d.h" , (bits_per_pixel % 4 == 0) |
? bits_per_pixel / 4 |
: (bits_per_pixel / 4) + 1 |
); |
foreach(this.lines[l]) |
begin |
s = $sformatf("[%4.d]", l); |
foreach(this.lines[l].pixel[p]) |
s = {s, $sformatf("|%4.h", this.lines[l].pixel[p])}; |
s = {s, $sformatf(fs, (p % grid == 0) ? "!" : "|", this.lines[l].pixel[p])}; |
|
f = {f, s, "|\n"}; |
end |
return f; |
/PCIe/syn/a10gx_riffa/a10gx_riffa.qpf
0,0 → 1,7
# -------------------------------------------------------------------------- # |
# |
# -------------------------------------------------------------------------- # |
|
# Revisions |
|
PROJECT_REVISION = "a10gx_riffa" |
/PCIe/syn/a10gx_riffa/a10gx_riffa.qsf
0,0 → 1,397
# -------------------------------------------------------------------------- # |
# |
# |
# -------------------------------------------------------------------------- # |
|
set_global_assignment -name FAMILY "Arria 10" |
set_global_assignment -name DEVICE 10AX115S2F45I1SG |
set_global_assignment -name TOP_LEVEL_ENTITY a10gx_riffa_top |
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files |
|
# -------------------------------------------------------------------------- # |
set_location_assignment PIN_AU33 -to clk_50 |
|
set_location_assignment PIN_BD27 -to cpu_resetn |
set_location_assignment PIN_L28 -to user_led_g[0] |
set_location_assignment PIN_K26 -to user_led_g[1] |
set_location_assignment PIN_K25 -to user_led_g[2] |
set_location_assignment PIN_L25 -to user_led_g[3] |
set_location_assignment PIN_J24 -to user_led_g[4] |
set_location_assignment PIN_A19 -to user_led_g[5] |
set_location_assignment PIN_C18 -to user_led_g[6] |
set_location_assignment PIN_D18 -to user_led_g[7] |
set_location_assignment PIN_L27 -to user_led_r[0] |
set_location_assignment PIN_J26 -to user_led_r[1] |
set_location_assignment PIN_K24 -to user_led_r[2] |
set_location_assignment PIN_L23 -to user_led_r[3] |
set_location_assignment PIN_B20 -to user_led_r[4] |
set_location_assignment PIN_C19 -to user_led_r[5] |
set_location_assignment PIN_D19 -to user_led_r[6] |
set_location_assignment PIN_M23 -to user_led_r[7] |
|
|
|
set_location_assignment PIN_T12 -to user_pb[0] |
set_location_assignment PIN_U12 -to user_pb[1] |
set_location_assignment PIN_U11 -to user_pb[2] |
|
|
|
# -------------------------------------------------------------------------- # |
# PCIe |
set_location_assignment PIN_BC30 -to pcie_perstn |
|
set_location_assignment PIN_AT40 -to pcie_rx_p[0] |
set_location_assignment PIN_AP40 -to pcie_rx_p[1] |
set_location_assignment PIN_AN42 -to pcie_rx_p[2] |
set_location_assignment PIN_AM40 -to pcie_rx_p[3] |
set_location_assignment PIN_AL42 -to pcie_rx_p[4] |
set_location_assignment PIN_AK40 -to pcie_rx_p[5] |
set_location_assignment PIN_AJ42 -to pcie_rx_p[6] |
set_location_assignment PIN_AH40 -to pcie_rx_p[7] |
|
set_location_assignment PIN_BB44 -to pcie_tx_p[0] |
set_location_assignment PIN_BA42 -to pcie_tx_p[1] |
set_location_assignment PIN_AY44 -to pcie_tx_p[2] |
set_location_assignment PIN_AW42 -to pcie_tx_p[3] |
set_location_assignment PIN_AV44 -to pcie_tx_p[4] |
set_location_assignment PIN_AU42 -to pcie_tx_p[5] |
set_location_assignment PIN_AT44 -to pcie_tx_p[6] |
set_location_assignment PIN_AR42 -to pcie_tx_p[7] |
|
|
set_location_assignment PIN_AL37 -to pcie_edge_refclk_p |
|
|
# -------------------------------------------------------------------------- # |
#Group0 |
set_location_assignment PIN_B28 -to emif_0_mem_mem_dq[0] |
set_location_assignment PIN_A28 -to emif_0_mem_mem_dq[1] |
set_location_assignment PIN_A27 -to emif_0_mem_mem_dq[2] |
set_location_assignment PIN_B27 -to emif_0_mem_mem_dq[3] |
set_location_assignment PIN_D27 -to emif_0_mem_mem_dq[4] |
set_location_assignment PIN_E27 -to emif_0_mem_mem_dq[5] |
set_location_assignment PIN_D26 -to emif_0_mem_mem_dq[6] |
set_location_assignment PIN_D28 -to emif_0_mem_mem_dq[7] |
|
set_location_assignment PIN_B26 -to emif_0_mem_mem_dqs[0] |
set_location_assignment PIN_C26 -to emif_0_mem_mem_dqs_n[0] |
|
set_location_assignment PIN_E26 -to emif_0_mem_mem_dbi_n[0] |
|
|
#Group1 |
set_location_assignment PIN_G25 -to emif_0_mem_mem_dq[8] |
set_location_assignment PIN_H25 -to emif_0_mem_mem_dq[9] |
set_location_assignment PIN_G26 -to emif_0_mem_mem_dq[10] |
set_location_assignment PIN_H26 -to emif_0_mem_mem_dq[11] |
set_location_assignment PIN_G28 -to emif_0_mem_mem_dq[12] |
set_location_assignment PIN_F27 -to emif_0_mem_mem_dq[13] |
set_location_assignment PIN_K27 -to emif_0_mem_mem_dq[14] |
set_location_assignment PIN_F28 -to emif_0_mem_mem_dq[15] |
|
set_location_assignment PIN_H28 -to emif_0_mem_mem_dqs[1] |
set_location_assignment PIN_J27 -to emif_0_mem_mem_dqs_n[1] |
|
set_location_assignment PIN_G27 -to emif_0_mem_mem_dbi_n[1] |
|
|
#Group 2 |
set_location_assignment PIN_D31 -to emif_0_mem_mem_dq[16] |
set_location_assignment PIN_E31 -to emif_0_mem_mem_dq[17] |
set_location_assignment PIN_B31 -to emif_0_mem_mem_dq[18] |
set_location_assignment PIN_C31 -to emif_0_mem_mem_dq[19] |
set_location_assignment PIN_A30 -to emif_0_mem_mem_dq[20] |
set_location_assignment PIN_E30 -to emif_0_mem_mem_dq[21] |
set_location_assignment PIN_B30 -to emif_0_mem_mem_dq[22] |
set_location_assignment PIN_D29 -to emif_0_mem_mem_dq[23] |
|
set_location_assignment PIN_C30 -to emif_0_mem_mem_dqs[2] |
set_location_assignment PIN_C29 -to emif_0_mem_mem_dqs_n[2] |
|
set_location_assignment PIN_A29 -to emif_0_mem_mem_dbi_n[2] |
|
#Group 3 |
set_location_assignment PIN_K30 -to emif_0_mem_mem_dq[24] |
set_location_assignment PIN_H30 -to emif_0_mem_mem_dq[25] |
set_location_assignment PIN_G30 -to emif_0_mem_mem_dq[26] |
set_location_assignment PIN_K31 -to emif_0_mem_mem_dq[27] |
set_location_assignment PIN_H29 -to emif_0_mem_mem_dq[28] |
set_location_assignment PIN_K29 -to emif_0_mem_mem_dq[29] |
set_location_assignment PIN_J29 -to emif_0_mem_mem_dq[30] |
set_location_assignment PIN_F29 -to emif_0_mem_mem_dq[31] |
|
set_location_assignment PIN_L30 -to emif_0_mem_mem_dqs[3] |
set_location_assignment PIN_L29 -to emif_0_mem_mem_dqs_n[3] |
|
set_location_assignment PIN_F30 -to emif_0_mem_mem_dbi_n[3] |
|
#Group 4 |
set_location_assignment PIN_AC31 -to emif_0_mem_mem_dq[32] |
set_location_assignment PIN_AB31 -to emif_0_mem_mem_dq[33] |
set_location_assignment PIN_W31 -to emif_0_mem_mem_dq[34] |
set_location_assignment PIN_Y31 -to emif_0_mem_mem_dq[35] |
set_location_assignment PIN_AD31 -to emif_0_mem_mem_dq[36] |
set_location_assignment PIN_AD32 -to emif_0_mem_mem_dq[37] |
set_location_assignment PIN_AD33 -to emif_0_mem_mem_dq[38] |
set_location_assignment PIN_AA30 -to emif_0_mem_mem_dq[39] |
|
set_location_assignment PIN_Y32 -to emif_0_mem_mem_dqs[4] |
set_location_assignment PIN_AA32 -to emif_0_mem_mem_dqs_n[4] |
|
set_location_assignment PIN_AB32 -to emif_0_mem_mem_dbi_n[4] |
|
#Group 5 |
set_location_assignment PIN_AE31 -to emif_0_mem_mem_dq[40] |
set_location_assignment PIN_AE32 -to emif_0_mem_mem_dq[41] |
set_location_assignment PIN_AE30 -to emif_0_mem_mem_dq[42] |
set_location_assignment PIN_AF30 -to emif_0_mem_mem_dq[43] |
set_location_assignment PIN_AG33 -to emif_0_mem_mem_dq[44] |
set_location_assignment PIN_AG32 -to emif_0_mem_mem_dq[45] |
set_location_assignment PIN_AH33 -to emif_0_mem_mem_dq[46] |
set_location_assignment PIN_AH31 -to emif_0_mem_mem_dq[47] |
|
set_location_assignment PIN_AJ32 -to emif_0_mem_mem_dqs[5] |
set_location_assignment PIN_AJ31 -to emif_0_mem_mem_dqs_n[5] |
|
set_location_assignment PIN_AG31 -to emif_0_mem_mem_dbi_n[5] |
|
#Group 6 |
set_location_assignment PIN_U31 -to emif_0_mem_mem_dq[48] |
set_location_assignment PIN_W33 -to emif_0_mem_mem_dq[49] |
set_location_assignment PIN_W32 -to emif_0_mem_mem_dq[50] |
set_location_assignment PIN_V31 -to emif_0_mem_mem_dq[51] |
set_location_assignment PIN_Y34 -to emif_0_mem_mem_dq[52] |
set_location_assignment PIN_W35 -to emif_0_mem_mem_dq[53] |
set_location_assignment PIN_W34 -to emif_0_mem_mem_dq[54] |
set_location_assignment PIN_V34 -to emif_0_mem_mem_dq[55] |
|
set_location_assignment PIN_AA34 -to emif_0_mem_mem_dqs[6] |
set_location_assignment PIN_AA33 -to emif_0_mem_mem_dqs_n[6] |
|
set_location_assignment PIN_Y35 -to emif_0_mem_mem_dbi_n[6] |
|
#Group 7 |
set_location_assignment PIN_AH35 -to emif_0_mem_mem_dq[56] |
set_location_assignment PIN_AJ34 -to emif_0_mem_mem_dq[57] |
set_location_assignment PIN_AJ33 -to emif_0_mem_mem_dq[58] |
set_location_assignment PIN_AH34 -to emif_0_mem_mem_dq[59] |
set_location_assignment PIN_AD35 -to emif_0_mem_mem_dq[60] |
set_location_assignment PIN_AE34 -to emif_0_mem_mem_dq[61] |
set_location_assignment PIN_AC33 -to emif_0_mem_mem_dq[62] |
set_location_assignment PIN_AD34 -to emif_0_mem_mem_dq[63] |
|
set_location_assignment PIN_AF33 -to emif_0_mem_mem_dqs[7] |
set_location_assignment PIN_AF34 -to emif_0_mem_mem_dqs_n[7] |
|
set_location_assignment PIN_AC34 -to emif_0_mem_mem_dbi_n[7] |
|
#Group 8 |
set_location_assignment PIN_A33 -to emif_0_mem_mem_dq[64] |
set_location_assignment PIN_B32 -to emif_0_mem_mem_dq[65] |
set_location_assignment PIN_D32 -to emif_0_mem_mem_dq[66] |
set_location_assignment PIN_C33 -to emif_0_mem_mem_dq[67] |
set_location_assignment PIN_B33 -to emif_0_mem_mem_dq[68] |
set_location_assignment PIN_D34 -to emif_0_mem_mem_dq[69] |
set_location_assignment PIN_C35 -to emif_0_mem_mem_dq[70] |
set_location_assignment PIN_E34 -to emif_0_mem_mem_dq[71] |
|
set_location_assignment PIN_D33 -to emif_0_mem_mem_dqs[8] |
set_location_assignment PIN_C34 -to emif_0_mem_mem_dqs_n[8] |
|
set_location_assignment PIN_A32 -to emif_0_mem_mem_dbi_n[8] |
|
# ###########ADDRESS, CLK, RZQ and REF Clock pins################## |
#middel tile RZQ |
set_location_assignment PIN_J34 -to emif_0_oct_oct_rzqin |
#bottom tile RZQ |
#set_location_assignment PIN_AF32 -to oct_oct_rzqin |
|
set_location_assignment PIN_M32 -to emif_0_mem_mem_a[0] |
set_location_assignment PIN_L32 -to emif_0_mem_mem_a[1] |
set_location_assignment PIN_N34 -to emif_0_mem_mem_a[2] |
set_location_assignment PIN_M35 -to emif_0_mem_mem_a[3] |
set_location_assignment PIN_L34 -to emif_0_mem_mem_a[4] |
set_location_assignment PIN_K34 -to emif_0_mem_mem_a[5] |
set_location_assignment PIN_M33 -to emif_0_mem_mem_a[6] |
set_location_assignment PIN_L33 -to emif_0_mem_mem_a[7] |
set_location_assignment PIN_J33 -to emif_0_mem_mem_a[8] |
set_location_assignment PIN_J32 -to emif_0_mem_mem_a[9] |
set_location_assignment PIN_H31 -to emif_0_mem_mem_a[10] |
set_location_assignment PIN_J31 -to emif_0_mem_mem_a[11] |
set_location_assignment PIN_H34 -to emif_0_mem_mem_a[12] |
set_location_assignment PIN_H33 -to emif_0_mem_mem_a[13] |
set_location_assignment PIN_G32 -to emif_0_mem_mem_a[14] |
set_location_assignment PIN_E32 -to emif_0_mem_mem_a[15] |
set_location_assignment PIN_F32 -to emif_0_mem_mem_a[16] |
|
set_location_assignment PIN_F33 -to emif_0_mem_mem_ba[0] |
set_location_assignment PIN_G35 -to emif_0_mem_mem_ba[1] |
set_location_assignment PIN_H35 -to emif_0_mem_mem_bg[0] |
#set_location_assignment PIN_T34 -to emif_0_mem_mem_bg[1] |
|
set_location_assignment PIN_R30 -to emif_0_mem_mem_ck[0] |
set_location_assignment PIN_R31 -to emif_0_mem_mem_ck_n[0] |
set_location_assignment PIN_U33 -to emif_0_mem_mem_cke[0] |
|
set_location_assignment PIN_R34 -to emif_0_mem_mem_cs_n[0] |
set_location_assignment PIN_P34 -to emif_0_mem_mem_act_n[0] |
set_location_assignment PIN_N33 -to emif_0_mem_mem_odt[0] |
set_location_assignment PIN_T35 -to emif_0_mem_mem_reset_n[0] |
set_location_assignment PIN_T32 -to emif_0_mem_mem_par[0] |
|
set_location_assignment PIN_E35 -to emif_0_mem_mem_alert_n[0] |
|
set_location_assignment PIN_F35 -to "emif_0_pll_ref_clk_clk(n)" |
set_location_assignment PIN_F34 -to emif_0_pll_ref_clk_clk |
|
set_instance_assignment -name IO_STANDARD LVDS -to emif_0_pll_ref_clk_clk |
set_instance_assignment -name IO_STANDARD LVDS -to "emif_0_pll_ref_clk_clk(n)" |
|
|
# -------------------------------------------------------------------------- # |
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Standard Edition" |
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" |
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 |
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" |
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" |
|
|
|
# ############################################################################## |
# set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 |
|
|
|
# -------------------------------------------------------------------------- # |
set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:make_pof.tcl" |
|
|
# -------------------------------------------------------------------------- # |
|
|
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top |
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top |
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top |
set_instance_assignment -name IO_STANDARD "1.8 V" -to clk_50 |
set_instance_assignment -name IO_STANDARD "1.8 V" -to cpu_resetn |
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_led_g |
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_led_r |
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_pb[0] |
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_pb[1] |
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_pb[2] |
set_instance_assignment -name IO_STANDARD "1.8 V" -to pcie_perstn |
set_instance_assignment -name IO_STANDARD CML -to pcie_rx_p |
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie_rx_p |
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p |
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie_tx_p |
set_instance_assignment -name IO_STANDARD HCSL -to pcie_edge_refclk_p |
set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to pcie_edge_refclk_p |
set_global_assignment -name ENABLE_SIGNALTAP ON |
|
# -------------------------------------------------------------------------- # |
|
|
|
|
# -------------------------------------------------------------------------- # |
|
|
|
|
|
set_global_assignment -name SEARCH_PATH ../../../../riffa_2.2.2/src |
set_global_assignment -name SYSTEMVERILOG_FILE a10gx_sys.sv |
set_global_assignment -name SYSTEMVERILOG_FILE a10gx_riffa_top.sv |
set_global_assignment -name SYSTEMVERILOG_FILE a10gx_riffa.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_map_fifo.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../../basal/src/misc/one_hot_encoder.sv |
set_global_assignment -name VERILOG_FILE ../../../basal/src/PRBS/prbs_23_to_8.v |
set_global_assignment -name VERILOG_FILE ../../../basal/src/synchronize/sync_reset.v |
set_global_assignment -name SYSTEMVERILOG_FILE ../../../basal/src/misc/recursive_mux.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_upsizer.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_downsizer.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../../basal/src/FIFOs/tiny_sync_fifo.sv |
set_global_assignment -name VERILOG_FILE ../../../basal/src/FIFOs/bc_sync_fifo.v |
set_global_assignment -name SYSTEMVERILOG_FILE ../../../basal/src/FIFOs/sync_fifo.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_test_patern.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_axis_test_pattern.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_register_slice.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_mux.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_if.sv |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/riffa_async_fifo.v |
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_w.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../../../riffa_2.2.2/src/riffa_pkg.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_register_if.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_register_file.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_tx_fsm.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_tx.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_rx_fsm.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_rx.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_if.sv |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/txr_engine_classic.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/txc_engine_classic.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_writer.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_monitor_128.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_channel_gate_128.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_buffer_128.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_128.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_multiplexer_128.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_multiplexer.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_hdr_fifo.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_engine_selector.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_engine_classic.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_engine.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_data_shift.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_data_pipeline.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_data_fifo.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_alignment_pipeline.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/translation_altera.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/syncff.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/riffa_sync_fifo.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/shiftreg.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/sg_list_requester.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/sg_list_reader_128.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/scsdpram.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rxr_engine_classic.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rxc_engine_classic.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_port_requester_mux.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_port_reader.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_port_channel_gate.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_port_128.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_engine_classic.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rotate.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/riffa.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reset_extender.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reset_controller.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reorder_queue_output.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reorder_queue_input.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reorder_queue.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/registers.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/register.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/recv_credit_flow_ctrl.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/ram_2clk_1w_1r.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/ram_1clk_1w_1r.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/pipeline.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/one_hot_mux.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/offset_to_mask.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/offset_flag_to_one_hot.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/mux.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/interrupt_controller.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/interrupt.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/fifo_packer_128.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/fifo.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/ff.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/engine_layer.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/demux.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/cross_domain_signal.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/counter.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/chnl_tester.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/channel_128.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/channel.v |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/async_fifo_fwft.v |
set_global_assignment -name QSYS_FILE ../../../../riffa_2.2.2/source/fpga/altera/a10ax/A10GXGen2x8If128_PCIe.qsys |
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/source/fpga/altera/a10ax/riffa_wrapper_a10gx.v |
set_global_assignment -name SYSTEMVERILOG_FILE a10gx_riffa_pcie.sv |
set_global_assignment -name QSYS_FILE sys_pll.qsys |
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |
/PCIe/syn/a10gx_riffa/a10gx_riffa.sdc
0,0 → 1,111
# ---------------------------------------------------------------------- |
# Copyright (c) 2016, The Regents of the University of California All |
# rights reserved. |
# |
# Redistribution and use in source and binary forms, with or without |
# modification, are permitted provided that the following conditions are |
# met: |
# |
# * Redistributions of source code must retain the above copyright |
# notice, this list of conditions and the following disclaimer. |
# |
# * Redistributions in binary form must reproduce the above |
# copyright notice, this list of conditions and the following |
# disclaimer in the documentation and/or other materials provided |
# with the distribution. |
# |
# * Neither the name of The Regents of the University of California |
# nor the names of its contributors may be used to endorse or |
# promote products derived from this software without specific |
# prior written permission. |
# |
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE |
# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, |
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR |
# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE |
# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH |
# DAMAGE. |
# ---------------------------------------------------------------------- |
# --------------------------------------------------------------------------- |
# Filename: DE5QGen3x4If128.sdc (Qsys) |
# Version: 1.00.a |
# Verilog Standard: Verilog-2001 |
# Description: Synopsys Design Constraints for the DE5 board. |
# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input |
# Author: Dustin Richmond (@darichmond) |
# ---------------------------------------------------------------------------- |
# create_clock -name PCIE_REFCLK -period 10.000 [get_ports {PCIE_REFCLK}] |
# create_clock -name osc_50MHz -period 20.000 [get_ports {OSC_BANK3D_50MHZ}] |
|
create_clock -name {altera_reserved_tck} -period 33.333 -waveform { 0.000 16.666 } [get_ports {altera_reserved_tck}] |
create_clock -name {clk_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk_50}] |
# create_clock -name {pcie_ob_refclk_p} -period 10.000 [get_ports {pcie_ob_refclk_p}] |
# create_clock -name {emif_0_pll_ref_clk_clk} -period 6.666 [ get_ports emif_0_pll_ref_clk_clk] |
|
# derive_pll_clocks -create_base_clocks |
# derive_clock_uncertainty |
|
#************************************************************** |
# Set Input Delay |
#************************************************************** |
set_input_delay -clock altera_reserved_tck 6 [get_ports altera_reserved_tdi] |
set_input_delay -clock altera_reserved_tck 6 [get_ports altera_reserved_tms] |
|
|
|
#************************************************************** |
# Set Output Delay |
#************************************************************** |
set_output_delay -clock altera_reserved_tck -clock_fall -max 6 [get_ports altera_reserved_tdo] |
|
|
|
#************************************************************** |
# Set Clock Groups |
#************************************************************** |
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] |
set_clock_groups -asynchronous -group [get_clocks { clk_50 }] |
# set_clock_groups -asynchronous -group [get_clocks { pcie_ob_refclk_p }] |
# set_clock_groups -asynchronous -group [get_clocks { emif_0_pll_ref_clk_clk }] |
|
|
#************************************************************** |
# Set False Path |
#************************************************************** |
set_false_path -from * -to [get_ports {user_led_g[*]}] |
set_false_path -from * -to [get_ports {user_led_r[*]}] |
set_false_path -from [get_ports {altera_reserved_ntrst}] |
set_false_path -from [get_ports {cpu_resetn}] |
# set_false_path -from [get_ports {emif_0_oct_oct_rzqin}] |
|
|
#************************************************************** |
# Set Multicycle Path |
#************************************************************** |
|
|
|
#************************************************************** |
# Set Maximum Delay |
#************************************************************** |
|
|
|
#************************************************************** |
# Set Minimum Delay |
#************************************************************** |
|
|
|
#************************************************************** |
# Set Input Transition |
#************************************************************** |
|
|
|
/PCIe/syn/a10gx_riffa/a10gx_riffa.sv
0,0 → 1,159
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2018 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
a10gx_riffa |
#(// Number of RIFFA Channels |
C_NUM_CHNL, |
// Number of PCIe Lanes |
C_NUM_LANES, |
// Settings from Quartus IP Library |
C_PCI_DATA_WIDTH, |
C_MAX_PAYLOAD_BYTES, |
C_LOG_NUM_TAGS, |
C_FPGA_ID |
) |
( |
input [ 7:0] pcie_rx_p, //PCML14 //PCIe Receive Data-req's OCT |
output [ 7:0] pcie_tx_p, //PCML14 //PCIe Transmit Data |
input pcie_edge_refclk_p, //HCSL //PCIe Clock- Terminate on MB |
input pcie_perstn, //1.8V //PCIe Reset |
input npor, |
|
riffa_chnl_if chnl_bus[C_NUM_CHNL], |
|
output chnl_reset, |
output chnl_clk |
); |
|
// -------------------------------------------------------------------- |
import riffa_pkg::*; |
|
// -------------------------------------------------------------------- |
wire [3:0] tl_cfg_add; |
wire [31:0] tl_cfg_ctl; |
wire [52:0] tl_cfg_sts; |
wire [0:0] rx_st_sop; |
wire [0:0] rx_st_eop; |
wire [0:0] rx_st_err; |
wire [0:0] rx_st_valid; |
wire [0:0] rx_st_empty; |
wire rx_st_ready; |
wire [C_PCI_DATA_WIDTH-1:0] rx_st_data; |
wire [0:0] tx_st_sop; |
wire [0:0] tx_st_eop; |
wire [0:0] tx_st_err; |
wire [0:0] tx_st_valid; |
wire tx_st_ready; |
wire [C_PCI_DATA_WIDTH-1:0] tx_st_data; |
wire [0:0] tx_st_empty; |
wire pld_clk; |
wire reset_status; |
wire app_msi_req; |
wire app_msi_ack; |
wire [7:0] ko_cpl_spc_header; |
wire [11:0] ko_cpl_spc_data; |
|
a10gx_riffa_pcie #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) |
a10gx_riffa_pcie_i(.*); |
|
// -------------------------------------------------------------------- |
wire [C_NUM_CHNL-1:0] CHNL_RX_CLK; |
wire [C_NUM_CHNL-1:0] CHNL_RX; |
wire [C_NUM_CHNL-1:0] CHNL_RX_ACK; |
wire [C_NUM_CHNL-1:0] CHNL_RX_LAST; |
wire [(C_NUM_CHNL*32)-1:0] CHNL_RX_LEN; |
wire [(C_NUM_CHNL*31)-1:0] CHNL_RX_OFF; |
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA; |
wire [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID; |
wire [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN; |
wire [C_NUM_CHNL-1:0] CHNL_TX_CLK; |
wire [C_NUM_CHNL-1:0] CHNL_TX; |
wire [C_NUM_CHNL-1:0] CHNL_TX_ACK; |
wire [C_NUM_CHNL-1:0] CHNL_TX_LAST; |
wire [(C_NUM_CHNL*32)-1:0] CHNL_TX_LEN; |
wire [(C_NUM_CHNL*31)-1:0] CHNL_TX_OFF; |
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA; |
wire [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID; |
wire [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN; |
|
riffa_chnl_w |
#( |
.C_NUM_CHNL(C_NUM_CHNL), |
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH), |
.SIG_CHNL_LENGTH_W(SIG_CHNL_LENGTH_W), |
.SIG_CHNL_OFFSET_W(SIG_CHNL_OFFSET_W) |
) |
riffa_chnl_w_i(.*); |
|
// -------------------------------------------------------------------- |
wire rst_out; |
wire riffa_reset; |
wire riffa_clk; |
assign riffa_reset = reset_status; |
assign riffa_clk = pld_clk; |
assign chnl_clk = pld_clk; |
assign chnl_reset = rst_out; |
|
riffa_wrapper_a10gx |
#( |
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS), |
.C_NUM_CHNL (C_NUM_CHNL), |
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), |
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES), |
.C_FPGA_ID (C_FPGA_ID) |
) |
riffa |
( |
.RX_ST_READY (rx_st_ready), |
.TX_ST_DATA (tx_st_data[C_PCI_DATA_WIDTH-1:0]), |
.TX_ST_VALID (tx_st_valid[0:0]), |
.TX_ST_EOP (tx_st_eop[0:0]), |
.TX_ST_SOP (tx_st_sop[0:0]), |
.TX_ST_EMPTY (tx_st_empty[0:0]), |
.APP_MSI_REQ (app_msi_req), |
.RST_OUT (rst_out), |
// Inputs |
.RX_ST_DATA (rx_st_data[C_PCI_DATA_WIDTH-1:0]), |
.RX_ST_EOP (rx_st_eop[0:0]), |
.RX_ST_SOP (rx_st_sop[0:0]), |
.RX_ST_VALID (rx_st_valid[0:0]), |
.RX_ST_EMPTY (rx_st_empty[0:0]), |
.TX_ST_READY (tx_st_ready), |
.TL_CFG_CTL (tl_cfg_ctl[SIG_CFG_CTL_W-1:0]), |
.TL_CFG_ADD (tl_cfg_add[SIG_CFG_ADD_W-1:0]), |
.TL_CFG_STS (tl_cfg_sts[SIG_CFG_STS_W-1:0]), |
.KO_CPL_SPC_HEADER (ko_cpl_spc_header[SIG_KO_CPLH_W-1:0]), |
.KO_CPL_SPC_DATA (ko_cpl_spc_data[SIG_KO_CPLD_W-1:0]), |
.APP_MSI_ACK (app_msi_ack), |
.PLD_CLK (pld_clk), |
.RESET_STATUS (reset_status), |
.* |
); |
|
// -------------------------------------------------------------------- |
endmodule |
/PCIe/syn/a10gx_riffa/a10gx_riffa_pcie.sv
0,0 → 1,370
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2018 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
a10gx_riffa_pcie |
#( |
C_PCI_DATA_WIDTH |
) |
( |
input [ 7:0] pcie_rx_p, //PCML14 //PCIe Receive Data-req's OCT |
output [ 7:0] pcie_tx_p, //PCML14 //PCIe Transmit Data |
input pcie_edge_refclk_p, //HCSL //PCIe Clock- Terminate on MB |
input pcie_perstn, //1.8V //PCIe Reset |
output pld_clk, |
|
input npor, |
output reset_status, |
output [7:0] ko_cpl_spc_header, |
output [11:0] ko_cpl_spc_data, |
input app_msi_req, |
output app_msi_ack, |
|
output [3:0] tl_cfg_add, |
output [31:0] tl_cfg_ctl, |
output [52:0] tl_cfg_sts, |
|
output [0:0] rx_st_sop, |
output [0:0] rx_st_eop, |
output [0:0] rx_st_err, |
output [0:0] rx_st_valid, |
input rx_st_ready, |
output [C_PCI_DATA_WIDTH-1:0] rx_st_data, |
output [0:0] rx_st_empty, |
|
input [0:0] tx_st_sop, |
input [0:0] tx_st_eop, |
input [0:0] tx_st_err, |
input [0:0] tx_st_valid, |
output tx_st_ready, |
input [C_PCI_DATA_WIDTH-1:0] tx_st_data, |
input [0:0] tx_st_empty |
); |
|
// -------------------------------------------------------------------- |
// |
wire pin_perst; |
|
|
// ----------Clocks & Locks---------- |
wire coreclkout_hip; |
wire refclk; |
wire pld_core_ready; |
wire serdes_pll_locked; |
|
// ------------Status Interface------------ |
wire derr_cor_ext_rcv; |
wire derr_cor_ext_rpl; |
wire derr_rpl; |
wire dlup; |
wire dlup_exit; |
wire ev128ns; |
wire ev1us; |
wire hotrst_exit; |
wire [3:0] int_status; |
wire l2_exit; |
wire [3:0] lane_act; |
wire [4:0] ltssmstate; |
wire rx_par_err; |
wire [1:0] tx_par_err; |
wire cfg_par_err; |
|
// ----------Clocks---------- |
assign pld_clk = coreclkout_hip; |
assign refclk = pcie_edge_refclk_p; |
assign pld_core_ready = serdes_pll_locked; |
|
// ----------Resets---------- |
assign pin_perst = pcie_perstn; |
|
|
// -------------------------------------------------------------------- |
// |
wire [31:0] test_in = 32'h00000188; |
wire simu_mode_pipe = 0; |
wire sim_pipe_pclk_in = 0; |
wire [1:0] sim_pipe_rate; |
wire [4:0] sim_ltssmstate; |
wire [2:0] eidleinfersel0; |
wire [2:0] eidleinfersel1; |
wire [2:0] eidleinfersel2; |
wire [2:0] eidleinfersel3; |
wire [2:0] eidleinfersel4; |
wire [2:0] eidleinfersel5; |
wire [2:0] eidleinfersel6; |
wire [2:0] eidleinfersel7; |
wire [1:0] powerdown0; |
wire [1:0] powerdown1; |
wire [1:0] powerdown2; |
wire [1:0] powerdown3; |
wire [1:0] powerdown4; |
wire [1:0] powerdown5; |
wire [1:0] powerdown6; |
wire [1:0] powerdown7; |
wire rxpolarity0; |
wire rxpolarity1; |
wire rxpolarity2; |
wire rxpolarity3; |
wire rxpolarity4; |
wire rxpolarity5; |
wire rxpolarity6; |
wire rxpolarity7; |
wire txcompl0; |
wire txcompl1; |
wire txcompl2; |
wire txcompl3; |
wire txcompl4; |
wire txcompl5; |
wire txcompl6; |
wire txcompl7; |
wire [31:0] txdata0; |
wire [31:0] txdata1; |
wire [31:0] txdata2; |
wire [31:0] txdata3; |
wire [31:0] txdata4; |
wire [31:0] txdata5; |
wire [31:0] txdata6; |
wire [31:0] txdata7; |
wire [3:0] txdatak0; |
wire [3:0] txdatak1; |
wire [3:0] txdatak2; |
wire [3:0] txdatak3; |
wire [3:0] txdatak4; |
wire [3:0] txdatak5; |
wire [3:0] txdatak6; |
wire [3:0] txdatak7; |
wire txdetectrx0; |
wire txdetectrx1; |
wire txdetectrx2; |
wire txdetectrx3; |
wire txdetectrx4; |
wire txdetectrx5; |
wire txdetectrx6; |
wire txdetectrx7; |
wire txelecidle0; |
wire txelecidle1; |
wire txelecidle2; |
wire txelecidle3; |
wire txelecidle4; |
wire txelecidle5; |
wire txelecidle6; |
wire txelecidle7; |
wire txdeemph0; |
wire txdeemph1; |
wire txdeemph2; |
wire txdeemph3; |
wire txdeemph4; |
wire txdeemph5; |
wire txdeemph6; |
wire txdeemph7; |
wire [2:0] txmargin0; |
wire [2:0] txmargin1; |
wire [2:0] txmargin2; |
wire [2:0] txmargin3; |
wire [2:0] txmargin4; |
wire [2:0] txmargin5; |
wire [2:0] txmargin6; |
wire [2:0] txmargin7; |
wire txswing0; |
wire txswing1; |
wire txswing2; |
wire txswing3; |
wire txswing4; |
wire txswing5; |
wire txswing6; |
wire txswing7; |
wire phystatus0 = 0; |
wire phystatus1 = 0; |
wire phystatus2 = 0; |
wire phystatus3 = 0; |
wire phystatus4 = 0; |
wire phystatus5 = 0; |
wire phystatus6 = 0; |
wire phystatus7 = 0; |
wire [31:0] rxdata0 = 0; |
wire [31:0] rxdata1 = 0; |
wire [31:0] rxdata2 = 0; |
wire [31:0] rxdata3 = 0; |
wire [31:0] rxdata4 = 0; |
wire [31:0] rxdata5 = 0; |
wire [31:0] rxdata6 = 0; |
wire [31:0] rxdata7 = 0; |
wire [3:0] rxdatak0 = 0; |
wire [3:0] rxdatak1 = 0; |
wire [3:0] rxdatak2 = 0; |
wire [3:0] rxdatak3 = 0; |
wire [3:0] rxdatak4 = 0; |
wire [3:0] rxdatak5 = 0; |
wire [3:0] rxdatak6 = 0; |
wire [3:0] rxdatak7 = 0; |
wire rxelecidle0 = 0; |
wire rxelecidle1 = 0; |
wire rxelecidle2 = 0; |
wire rxelecidle3 = 0; |
wire rxelecidle4 = 0; |
wire rxelecidle5 = 0; |
wire rxelecidle6 = 0; |
wire rxelecidle7 = 0; |
wire [2:0] rxstatus0 = 0; |
wire [2:0] rxstatus1 = 0; |
wire [2:0] rxstatus2 = 0; |
wire [2:0] rxstatus3 = 0; |
wire [2:0] rxstatus4 = 0; |
wire [2:0] rxstatus5 = 0; |
wire [2:0] rxstatus6 = 0; |
wire [2:0] rxstatus7 = 0; |
wire rxvalid0 = 0; |
wire rxvalid1 = 0; |
wire rxvalid2 = 0; |
wire rxvalid3 = 0; |
wire rxvalid4 = 0; |
wire rxvalid5 = 0; |
wire rxvalid6 = 0; |
wire rxvalid7 = 0; |
wire rxdataskip0 = 0; |
wire rxdataskip1 = 0; |
wire rxdataskip2 = 0; |
wire rxdataskip3 = 0; |
wire rxdataskip4 = 0; |
wire rxdataskip5 = 0; |
wire rxdataskip6 = 0; |
wire rxdataskip7 = 0; |
wire rxblkst0 = 0; |
wire rxblkst1 = 0; |
wire rxblkst2 = 0; |
wire rxblkst3 = 0; |
wire rxblkst4 = 0; |
wire rxblkst5 = 0; |
wire rxblkst6 = 0; |
wire rxblkst7 = 0; |
wire [1:0] rxsynchd0 = 0; |
wire [1:0] rxsynchd1 = 0; |
wire [1:0] rxsynchd2 = 0; |
wire [1:0] rxsynchd3 = 0; |
wire [1:0] rxsynchd4 = 0; |
wire [1:0] rxsynchd5 = 0; |
wire [1:0] rxsynchd6 = 0; |
wire [1:0] rxsynchd7 = 0; |
wire [17:0] currentcoeff0; |
wire [17:0] currentcoeff1; |
wire [17:0] currentcoeff2; |
wire [17:0] currentcoeff3; |
wire [17:0] currentcoeff4; |
wire [17:0] currentcoeff5; |
wire [17:0] currentcoeff6; |
wire [17:0] currentcoeff7; |
wire [2:0] currentrxpreset0; |
wire [2:0] currentrxpreset1; |
wire [2:0] currentrxpreset2; |
wire [2:0] currentrxpreset3; |
wire [2:0] currentrxpreset4; |
wire [2:0] currentrxpreset5; |
wire [2:0] currentrxpreset6; |
wire [2:0] currentrxpreset7; |
wire [1:0] txsynchd0; |
wire [1:0] txsynchd1; |
wire [1:0] txsynchd2; |
wire [1:0] txsynchd3; |
wire [1:0] txsynchd4; |
wire [1:0] txsynchd5; |
wire [1:0] txsynchd6; |
wire [1:0] txsynchd7; |
wire txblkst0; |
wire txblkst1; |
wire txblkst2; |
wire txblkst3; |
wire txblkst4; |
wire txblkst5; |
wire txblkst6; |
wire txblkst7; |
wire txdataskip0; |
wire txdataskip1; |
wire txdataskip2; |
wire txdataskip3; |
wire txdataskip4; |
wire txdataskip5; |
wire txdataskip6; |
wire txdataskip7; |
wire [1:0] rate0; |
wire [1:0] rate1; |
wire [1:0] rate2; |
wire [1:0] rate3; |
wire [1:0] rate4; |
wire [1:0] rate5; |
wire [1:0] rate6; |
wire [1:0] rate7; |
|
wire [1:0] currentspeed; |
wire pld_clk_inuse; |
wire testin_zero; |
wire clr_st; |
wire app_int_sts = 0; |
wire app_int_ack; |
wire [4:0] app_msi_num = 0; |
wire [2:0] app_msi_tc = 0; |
wire [7:0] rx_st_bar; |
wire rx_st_mask = 0; |
wire [11:0] tx_cred_data_fc; |
wire [5:0] tx_cred_fc_hip_cons; |
wire [5:0] tx_cred_fc_infinite; |
wire [7:0] tx_cred_hdr_fc; |
wire [1:0] tx_cred_fc_sel = 0; |
wire pm_auxpwr = 0; |
wire [9:0] pm_data = 0; |
wire pme_to_cr = 0; |
wire pm_event = 0; |
wire pme_to_sr; |
wire [4:0] hpg_ctrler = 0; |
wire [6:0] cpl_err = 0; |
wire cpl_pending = 0; |
|
A10GXGen2x8If128_PCIe |
A10GXGen2x8If128_PCIe_i |
( |
.rx_in0(pcie_rx_p[0]), |
.rx_in1(pcie_rx_p[1]), |
.rx_in2(pcie_rx_p[2]), |
.rx_in3(pcie_rx_p[3]), |
.rx_in4(pcie_rx_p[4]), |
.rx_in5(pcie_rx_p[5]), |
.rx_in6(pcie_rx_p[6]), |
.rx_in7(pcie_rx_p[7]), |
.tx_out0(pcie_tx_p[0]), |
.tx_out1(pcie_tx_p[1]), |
.tx_out2(pcie_tx_p[2]), |
.tx_out3(pcie_tx_p[3]), |
.tx_out4(pcie_tx_p[4]), |
.tx_out5(pcie_tx_p[5]), |
.tx_out6(pcie_tx_p[6]), |
.tx_out7(pcie_tx_p[7]), |
.* |
); |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
/PCIe/syn/a10gx_riffa/a10gx_riffa_top.sv
0,0 → 1,104
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2018 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
a10gx_riffa_top |
#(// Number of RIFFA Channels |
C_NUM_CHNL = 1, |
// Number of PCIe Lanes |
C_NUM_LANES = 8, |
// Settings from Quartus IP Library |
C_PCI_DATA_WIDTH = 128, |
C_MAX_PAYLOAD_BYTES = 256, |
C_LOG_NUM_TAGS = 5, |
C_FPGA_ID = 8'hab |
) |
( |
input clk_50, //1.8V - 50MHz |
|
input cpu_resetn, //1.8V //CPU Reset Pushbutton (TR=0) |
output [ 7:0] user_led_g, //1.8V //User LEDs |
output [ 7:0] user_led_r, //1.8V //User LEDs |
input [ 2:0] user_pb, //1.8V //User Pushbuttons (TR=0) |
|
input [ 7:0] pcie_rx_p, //PCML14 //PCIe Receive Data-req's OCT |
output [ 7:0] pcie_tx_p, //PCML14 //PCIe Transmit Data |
input pcie_edge_refclk_p, //HCSL //PCIe Clock- Terminate on MB |
input pcie_perstn //1.8V //PCIe Reset |
); |
|
// -------------------------------------------------------------------- |
localparam R_N = (C_PCI_DATA_WIDTH / 8); // width of the RIFFA bus in bytes |
localparam RR_B = 4; // number of available registers |
localparam I = 0; // TID width |
localparam D = 0; // TDEST width |
localparam U = 3; // TUSER width |
|
// -------------------------------------------------------------------- |
wire sys_aresetn; |
wire chnl_clk; |
wire chnl_reset; |
wire chnl_reset_s; |
wire clk = chnl_clk; |
wire reset = chnl_reset_s; |
wire aclk = chnl_clk; |
wire aresetn = ~chnl_reset_s; |
|
sync_reset |
sync_reset_i |
( |
.clk_in(chnl_clk), |
.async_reset_in(chnl_reset), |
.sync_reset_out(chnl_reset_s) |
); |
|
// -------------------------------------------------------------------- |
riffa_chnl_if #(.N(R_N)) chnl_bus[C_NUM_CHNL](); |
riffa_register_if #(.N(R_N), .B(RR_B)) r_if(.*); |
|
// -------------------------------------------------------------------- |
wire npor; |
|
a10gx_riffa |
#(// Number of RIFFA Channels |
.C_NUM_CHNL(C_NUM_CHNL), |
// Number of PCIe Lanes |
.C_NUM_LANES(C_NUM_LANES), |
// Settings from Quartus IP Library |
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH), |
.C_MAX_PAYLOAD_BYTES(C_MAX_PAYLOAD_BYTES), |
.C_LOG_NUM_TAGS(C_LOG_NUM_TAGS), |
.C_FPGA_ID(C_FPGA_ID) |
) |
a10gx_riffa_i(.*); |
|
// -------------------------------------------------------------------- |
a10gx_sys #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH), .B(RR_B)) |
a10gx_sys_i(.chnl_bus(chnl_bus[0]), .*); |
|
// -------------------------------------------------------------------- |
endmodule |
/PCIe/syn/a10gx_riffa/a10gx_sys.sv
0,0 → 1,104
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module |
a10gx_sys |
#( |
C_PCI_DATA_WIDTH, |
B, |
N = (C_PCI_DATA_WIDTH / 8), // width of the bus in bytes |
RW = (N/4), // width of the bus in 32 bit words |
RC = RW * B // number of available registers |
) |
( |
input clk_50, //1.8V - 50MHz |
input cpu_resetn, //1.8V //CPU Reset Pushbutton (TR=0) |
output [ 7:0] user_led_g, //1.8V //User LEDs |
output [ 7:0] user_led_r, //1.8V //User LEDs |
input [ 2:0] user_pb, //1.8V //User Pushbuttons (TR=0) |
output npor, |
input pcie_perstn, //1.8V //PCIe Reset |
output sys_aresetn, |
|
riffa_chnl_if chnl_bus, |
riffa_register_if r_if, |
input clk, |
input reset |
); |
|
// -------------------------------------------------------------------- |
// |
wire clk_50mhz; |
|
sys_pll |
sys_pll_i |
( |
.rst(~user_pb[0]), |
.refclk(clk_50), |
.outclk_0(clk_50mhz), |
.locked(sys_aresetn) |
); |
|
|
// -------------------------------------------------------------------- |
// |
riffa_register_file #(.N(N), .B(B)) |
riffa_register_file_i(.*); |
|
|
// -------------------------------------------------------------------- |
// |
reg [31:0] fled_counter; |
|
always_ff @(posedge clk_50mhz) |
fled_counter <= fled_counter + 1; |
|
|
// -------------------------------------------------------------------- |
// |
genvar j; |
|
generate |
for(j = 0; j < RC; j++) |
begin : registers |
assign r_if.register_in[j] = r_if.register_out[j]; |
end |
endgenerate |
|
|
// -------------------------------------------------------------------- |
// |
assign user_led_g[0] = fled_counter[23]; |
assign user_led_g[7:1] = r_if.register_out[0][7:1]; |
assign user_led_r = r_if.register_out[0][15:8]; |
assign npor = pcie_perstn & sys_aresetn; |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
/PCIe/syn/a10gx_riffa/make_pof.tcl
0,0 → 1,3
# |
|
qexec "quartus_cpf -c output_files/a10gx_riffa.cof" |
/PCIe/syn/a10gx_riffa/output_files/a10gx_riffa.cof
0,0 → 1,34
<?xml version="1.0" encoding="US-ASCII" standalone="yes"?> |
<cof> |
<eprom_name>CFI_2GB</eprom_name> |
<output_filename>output_files/a10gx_riffa.pof</output_filename> |
<n_pages>1</n_pages> |
<width>1</width> |
<mode>12</mode> |
<sof_data> |
<start_address>002D0000</start_address> |
<user_name>Page_0</user_name> |
<page_flags>1</page_flags> |
<bit0> |
<sof_filename>D:/qaz/projects/qaz_libs/PCIe/syn/a10gx_riffa/output_files/a10gx_riffa.sof</sof_filename> |
</bit0> |
</sof_data> |
<version>10</version> |
<create_cvp_file>0</create_cvp_file> |
<create_hps_iocsr>0</create_hps_iocsr> |
<auto_create_rpd>0</auto_create_rpd> |
<rpd_little_endian>1</rpd_little_endian> |
<options> |
<map_file>1</map_file> |
<option_start_address>180000</option_start_address> |
<dynamic_compression>0</dynamic_compression> |
</options> |
<advanced_options> |
<ignore_epcs_id_check>2</ignore_epcs_id_check> |
<ignore_condone_check>2</ignore_condone_check> |
<plc_adjustment>0</plc_adjustment> |
<post_chain_bitstream_pad_bytes>-1</post_chain_bitstream_pad_bytes> |
<post_device_bitstream_pad_bytes>-1</post_device_bitstream_pad_bytes> |
<bitslice_pre_padding>1</bitslice_pre_padding> |
</advanced_options> |
</cof> |
/PCIe/syn/a10gx_riffa/sys_pll.qsys
0,0 → 1,286
<?xml version="1.0" encoding="UTF-8"?> |
<system name="$${FILENAME}"> |
<component |
name="$${FILENAME}" |
displayName="$${FILENAME}" |
version="1.0" |
description="" |
tags="INTERNAL_COMPONENT=true" |
categories="" /> |
<parameter name="bonusData"><![CDATA[bonusData |
{ |
element iopll_0 |
{ |
datum _sortIndex |
{ |
value = "0"; |
type = "int"; |
} |
} |
} |
]]></parameter> |
<parameter name="clockCrossingAdapter" value="HANDSHAKE" /> |
<parameter name="device" value="10AX115S2F45I1SG" /> |
<parameter name="deviceFamily" value="Arria 10" /> |
<parameter name="deviceSpeedGrade" value="1" /> |
<parameter name="fabricMode" value="QSYS" /> |
<parameter name="generateLegacySim" value="false" /> |
<parameter name="generationId" value="0" /> |
<parameter name="globalResetBus" value="false" /> |
<parameter name="hdlLanguage" value="VERILOG" /> |
<parameter name="hideFromIPCatalog" value="true" /> |
<parameter name="lockedInterfaceDefinition" value="" /> |
<parameter name="maxAdditionalLatency" value="1" /> |
<parameter name="projectName" value="" /> |
<parameter name="sopcBorderPoints" value="false" /> |
<parameter name="systemHash" value="0" /> |
<parameter name="testBenchDutName" value="" /> |
<parameter name="timeStamp" value="0" /> |
<parameter name="useTestBenchNamingPattern" value="false" /> |
<instanceScript></instanceScript> |
<interface name="locked" internal="iopll_0.locked" type="conduit" dir="end"> |
<port name="locked" internal="locked" /> |
</interface> |
<interface name="outclk0" internal="iopll_0.outclk0" type="clock" dir="start"> |
<port name="outclk_0" internal="outclk_0" /> |
</interface> |
<interface name="refclk" internal="iopll_0.refclk" type="clock" dir="end"> |
<port name="refclk" internal="refclk" /> |
</interface> |
<interface name="reset" internal="iopll_0.reset" type="reset" dir="end"> |
<port name="rst" internal="rst" /> |
</interface> |
<module |
name="iopll_0" |
kind="altera_iopll" |
version="17.1" |
enabled="1" |
autoexport="1"> |
<parameter name="gui_active_clk" value="false" /> |
<parameter name="gui_c_cnt_in_src0">c_m_cnt_in_src_ph_mux_clk</parameter> |
<parameter name="gui_c_cnt_in_src1">c_m_cnt_in_src_ph_mux_clk</parameter> |
<parameter name="gui_c_cnt_in_src2">c_m_cnt_in_src_ph_mux_clk</parameter> |
<parameter name="gui_c_cnt_in_src3">c_m_cnt_in_src_ph_mux_clk</parameter> |
<parameter name="gui_c_cnt_in_src4">c_m_cnt_in_src_ph_mux_clk</parameter> |
<parameter name="gui_c_cnt_in_src5">c_m_cnt_in_src_ph_mux_clk</parameter> |
<parameter name="gui_c_cnt_in_src6">c_m_cnt_in_src_ph_mux_clk</parameter> |
<parameter name="gui_c_cnt_in_src7">c_m_cnt_in_src_ph_mux_clk</parameter> |
<parameter name="gui_c_cnt_in_src8">c_m_cnt_in_src_ph_mux_clk</parameter> |
<parameter name="gui_cal_code_hex_file" value="iossm.hex" /> |
<parameter name="gui_cal_converge" value="false" /> |
<parameter name="gui_cal_error" value="cal_clean" /> |
<parameter name="gui_cascade_counter0" value="false" /> |
<parameter name="gui_cascade_counter1" value="false" /> |
<parameter name="gui_cascade_counter10" value="false" /> |
<parameter name="gui_cascade_counter11" value="false" /> |
<parameter name="gui_cascade_counter12" value="false" /> |
<parameter name="gui_cascade_counter13" value="false" /> |
<parameter name="gui_cascade_counter14" value="false" /> |
<parameter name="gui_cascade_counter15" value="false" /> |
<parameter name="gui_cascade_counter16" value="false" /> |
<parameter name="gui_cascade_counter17" value="false" /> |
<parameter name="gui_cascade_counter2" value="false" /> |
<parameter name="gui_cascade_counter3" value="false" /> |
<parameter name="gui_cascade_counter4" value="false" /> |
<parameter name="gui_cascade_counter5" value="false" /> |
<parameter name="gui_cascade_counter6" value="false" /> |
<parameter name="gui_cascade_counter7" value="false" /> |
<parameter name="gui_cascade_counter8" value="false" /> |
<parameter name="gui_cascade_counter9" value="false" /> |
<parameter name="gui_cascade_outclk_index" value="0" /> |
<parameter name="gui_clk_bad" value="false" /> |
<parameter name="gui_clock_name_global" value="false" /> |
<parameter name="gui_clock_name_string0" value="outclk0" /> |
<parameter name="gui_clock_name_string1" value="outclk1" /> |
<parameter name="gui_clock_name_string10" value="outclk10" /> |
<parameter name="gui_clock_name_string11" value="outclk11" /> |
<parameter name="gui_clock_name_string12" value="outclk12" /> |
<parameter name="gui_clock_name_string13" value="outclk13" /> |
<parameter name="gui_clock_name_string14" value="outclk14" /> |
<parameter name="gui_clock_name_string15" value="outclk15" /> |
<parameter name="gui_clock_name_string16" value="outclk16" /> |
<parameter name="gui_clock_name_string17" value="outclk17" /> |
<parameter name="gui_clock_name_string2" value="outclk2" /> |
<parameter name="gui_clock_name_string3" value="outclk3" /> |
<parameter name="gui_clock_name_string4" value="outclk4" /> |
<parameter name="gui_clock_name_string5" value="outclk5" /> |
<parameter name="gui_clock_name_string6" value="outclk6" /> |
<parameter name="gui_clock_name_string7" value="outclk7" /> |
<parameter name="gui_clock_name_string8" value="outclk8" /> |
<parameter name="gui_clock_name_string9" value="outclk9" /> |
<parameter name="gui_clock_to_compensate" value="0" /> |
<parameter name="gui_debug_mode" value="false" /> |
<parameter name="gui_divide_factor_c0" value="6" /> |
<parameter name="gui_divide_factor_c1" value="6" /> |
<parameter name="gui_divide_factor_c10" value="6" /> |
<parameter name="gui_divide_factor_c11" value="6" /> |
<parameter name="gui_divide_factor_c12" value="6" /> |
<parameter name="gui_divide_factor_c13" value="6" /> |
<parameter name="gui_divide_factor_c14" value="6" /> |
<parameter name="gui_divide_factor_c15" value="6" /> |
<parameter name="gui_divide_factor_c16" value="6" /> |
<parameter name="gui_divide_factor_c17" value="6" /> |
<parameter name="gui_divide_factor_c2" value="6" /> |
<parameter name="gui_divide_factor_c3" value="6" /> |
<parameter name="gui_divide_factor_c4" value="6" /> |
<parameter name="gui_divide_factor_c5" value="6" /> |
<parameter name="gui_divide_factor_c6" value="6" /> |
<parameter name="gui_divide_factor_c7" value="6" /> |
<parameter name="gui_divide_factor_c8" value="6" /> |
<parameter name="gui_divide_factor_c9" value="6" /> |
<parameter name="gui_divide_factor_n" value="1" /> |
<parameter name="gui_dps_cntr" value="C0" /> |
<parameter name="gui_dps_dir" value="Positive" /> |
<parameter name="gui_dps_num" value="1" /> |
<parameter name="gui_dsm_out_sel" value="1st_order" /> |
<parameter name="gui_duty_cycle0" value="50.0" /> |
<parameter name="gui_duty_cycle1" value="50.0" /> |
<parameter name="gui_duty_cycle10" value="50.0" /> |
<parameter name="gui_duty_cycle11" value="50.0" /> |
<parameter name="gui_duty_cycle12" value="50.0" /> |
<parameter name="gui_duty_cycle13" value="50.0" /> |
<parameter name="gui_duty_cycle14" value="50.0" /> |
<parameter name="gui_duty_cycle15" value="50.0" /> |
<parameter name="gui_duty_cycle16" value="50.0" /> |
<parameter name="gui_duty_cycle17" value="50.0" /> |
<parameter name="gui_duty_cycle2" value="50.0" /> |
<parameter name="gui_duty_cycle3" value="50.0" /> |
<parameter name="gui_duty_cycle4" value="50.0" /> |
<parameter name="gui_duty_cycle5" value="50.0" /> |
<parameter name="gui_duty_cycle6" value="50.0" /> |
<parameter name="gui_duty_cycle7" value="50.0" /> |
<parameter name="gui_duty_cycle8" value="50.0" /> |
<parameter name="gui_duty_cycle9" value="50.0" /> |
<parameter name="gui_en_adv_params" value="false" /> |
<parameter name="gui_en_dps_ports" value="false" /> |
<parameter name="gui_en_extclkout_ports" value="false" /> |
<parameter name="gui_en_lvds_ports" value="Disabled" /> |
<parameter name="gui_en_phout_ports" value="false" /> |
<parameter name="gui_en_reconf" value="false" /> |
<parameter name="gui_enable_cascade_in" value="false" /> |
<parameter name="gui_enable_cascade_out" value="false" /> |
<parameter name="gui_enable_mif_dps" value="false" /> |
<parameter name="gui_enable_output_counter_cascading" value="false" /> |
<parameter name="gui_existing_mif_file_path" value="~/pll.mif" /> |
<parameter name="gui_extclkout_0_source" value="C0" /> |
<parameter name="gui_extclkout_1_source" value="C0" /> |
<parameter name="gui_feedback_clock" value="Global Clock" /> |
<parameter name="gui_fix_vco_frequency" value="false" /> |
<parameter name="gui_fixed_vco_frequency" value="600.0" /> |
<parameter name="gui_frac_multiply_factor" value="1" /> |
<parameter name="gui_fractional_cout" value="32" /> |
<parameter name="gui_include_iossm" value="false" /> |
<parameter name="gui_lock_setting" value="Low Lock Time" /> |
<parameter name="gui_mif_config_name" value="unnamed" /> |
<parameter name="gui_mif_gen_options">Generate New MIF File</parameter> |
<parameter name="gui_multiply_factor" value="6" /> |
<parameter name="gui_new_mif_file_path" value="~/pll.mif" /> |
<parameter name="gui_number_of_clocks" value="1" /> |
<parameter name="gui_operation_mode" value="direct" /> |
<parameter name="gui_output_clock_frequency0" value="50.0" /> |
<parameter name="gui_output_clock_frequency1" value="100.0" /> |
<parameter name="gui_output_clock_frequency10" value="100.0" /> |
<parameter name="gui_output_clock_frequency11" value="100.0" /> |
<parameter name="gui_output_clock_frequency12" value="100.0" /> |
<parameter name="gui_output_clock_frequency13" value="100.0" /> |
<parameter name="gui_output_clock_frequency14" value="100.0" /> |
<parameter name="gui_output_clock_frequency15" value="100.0" /> |
<parameter name="gui_output_clock_frequency16" value="100.0" /> |
<parameter name="gui_output_clock_frequency17" value="100.0" /> |
<parameter name="gui_output_clock_frequency2" value="100.0" /> |
<parameter name="gui_output_clock_frequency3" value="100.0" /> |
<parameter name="gui_output_clock_frequency4" value="100.0" /> |
<parameter name="gui_output_clock_frequency5" value="100.0" /> |
<parameter name="gui_output_clock_frequency6" value="100.0" /> |
<parameter name="gui_output_clock_frequency7" value="100.0" /> |
<parameter name="gui_output_clock_frequency8" value="100.0" /> |
<parameter name="gui_output_clock_frequency9" value="100.0" /> |
<parameter name="gui_parameter_table_hex_file" value="seq_params_sim.hex" /> |
<parameter name="gui_phase_shift0" value="0.0" /> |
<parameter name="gui_phase_shift1" value="0.0" /> |
<parameter name="gui_phase_shift10" value="0.0" /> |
<parameter name="gui_phase_shift11" value="0.0" /> |
<parameter name="gui_phase_shift12" value="0.0" /> |
<parameter name="gui_phase_shift13" value="0.0" /> |
<parameter name="gui_phase_shift14" value="0.0" /> |
<parameter name="gui_phase_shift15" value="0.0" /> |
<parameter name="gui_phase_shift16" value="0.0" /> |
<parameter name="gui_phase_shift17" value="0.0" /> |
<parameter name="gui_phase_shift2" value="0.0" /> |
<parameter name="gui_phase_shift3" value="0.0" /> |
<parameter name="gui_phase_shift4" value="0.0" /> |
<parameter name="gui_phase_shift5" value="0.0" /> |
<parameter name="gui_phase_shift6" value="0.0" /> |
<parameter name="gui_phase_shift7" value="0.0" /> |
<parameter name="gui_phase_shift8" value="0.0" /> |
<parameter name="gui_phase_shift9" value="0.0" /> |
<parameter name="gui_phase_shift_deg0" value="0.0" /> |
<parameter name="gui_phase_shift_deg1" value="0.0" /> |
<parameter name="gui_phase_shift_deg10" value="0.0" /> |
<parameter name="gui_phase_shift_deg11" value="0.0" /> |
<parameter name="gui_phase_shift_deg12" value="0.0" /> |
<parameter name="gui_phase_shift_deg13" value="0.0" /> |
<parameter name="gui_phase_shift_deg14" value="0.0" /> |
<parameter name="gui_phase_shift_deg15" value="0.0" /> |
<parameter name="gui_phase_shift_deg16" value="0.0" /> |
<parameter name="gui_phase_shift_deg17" value="0.0" /> |
<parameter name="gui_phase_shift_deg2" value="0.0" /> |
<parameter name="gui_phase_shift_deg3" value="0.0" /> |
<parameter name="gui_phase_shift_deg4" value="0.0" /> |
<parameter name="gui_phase_shift_deg5" value="0.0" /> |
<parameter name="gui_phase_shift_deg6" value="0.0" /> |
<parameter name="gui_phase_shift_deg7" value="0.0" /> |
<parameter name="gui_phase_shift_deg8" value="0.0" /> |
<parameter name="gui_phase_shift_deg9" value="0.0" /> |
<parameter name="gui_phout_division" value="1" /> |
<parameter name="gui_pll_auto_reset" value="false" /> |
<parameter name="gui_pll_bandwidth_preset" value="Low" /> |
<parameter name="gui_pll_cal_done" value="false" /> |
<parameter name="gui_pll_cascading_mode" value="adjpllin" /> |
<parameter name="gui_pll_freqcal_en" value="true" /> |
<parameter name="gui_pll_freqcal_req_flag" value="true" /> |
<parameter name="gui_pll_m_cnt_in_src">c_m_cnt_in_src_ph_mux_clk</parameter> |
<parameter name="gui_pll_mode" value="Integer-N PLL" /> |
<parameter name="gui_pll_tclk_mux_en" value="false" /> |
<parameter name="gui_pll_tclk_sel" value="pll_tclk_m_src" /> |
<parameter name="gui_pll_type" value="S10_Simple" /> |
<parameter name="gui_pll_vco_freq_band_0">pll_freq_clk0_disabled</parameter> |
<parameter name="gui_pll_vco_freq_band_1">pll_freq_clk1_disabled</parameter> |
<parameter name="gui_ps_units0" value="ps" /> |
<parameter name="gui_ps_units1" value="ps" /> |
<parameter name="gui_ps_units10" value="ps" /> |
<parameter name="gui_ps_units11" value="ps" /> |
<parameter name="gui_ps_units12" value="ps" /> |
<parameter name="gui_ps_units13" value="ps" /> |
<parameter name="gui_ps_units14" value="ps" /> |
<parameter name="gui_ps_units15" value="ps" /> |
<parameter name="gui_ps_units16" value="ps" /> |
<parameter name="gui_ps_units17" value="ps" /> |
<parameter name="gui_ps_units2" value="ps" /> |
<parameter name="gui_ps_units3" value="ps" /> |
<parameter name="gui_ps_units4" value="ps" /> |
<parameter name="gui_ps_units5" value="ps" /> |
<parameter name="gui_ps_units6" value="ps" /> |
<parameter name="gui_ps_units7" value="ps" /> |
<parameter name="gui_ps_units8" value="ps" /> |
<parameter name="gui_ps_units9" value="ps" /> |
<parameter name="gui_refclk1_frequency" value="100.0" /> |
<parameter name="gui_refclk_switch" value="false" /> |
<parameter name="gui_reference_clock_frequency" value="50.0" /> |
<parameter name="gui_switchover_delay" value="0" /> |
<parameter name="gui_switchover_mode">Automatic Switchover</parameter> |
<parameter name="gui_use_NDFB_modes" value="false" /> |
<parameter name="gui_use_locked" value="true" /> |
<parameter name="gui_usr_device_speed_grade" value="1" /> |
<parameter name="gui_vco_frequency" value="600.0" /> |
<parameter name="hp_qsys_scripting_mode" value="false" /> |
<parameter name="system_info_device_component" value="10AX115S2F45I1SG" /> |
<parameter name="system_info_device_family" value="Arria 10" /> |
<parameter name="system_info_device_speed_grade" value="1" /> |
<parameter name="system_part_trait_speed_grade" value="1" /> |
</module> |
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> |
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" /> |
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" /> |
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" /> |
</system> |
/axi4_stream_lib/sim/src/legacy/tb_axis_register_slice.sv
0,0 → 1,159
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module tb_top(); |
|
// -------------------------------------------------------------------- |
// test bench clock & reset |
wire clk_200mhz; |
wire tb_clk = clk_200mhz; |
wire tb_rst; |
wire aclk = tb_clk; |
wire aresetn = ~tb_rst; |
|
tb_base #( .PERIOD(5_000) ) tb( clk_200mhz, tb_rst ); |
|
|
// -------------------------------------------------------------------- |
// |
localparam TILES = 1; |
localparam WIDTH = 32; // tile width |
localparam HEIGHT = 16; // tile height |
localparam OUTPUTS_PER_TILE = 1; // outputs per tile |
localparam BYTES_PER_PIXEL = 2; |
localparam BITS_PER_PIXEL = 16; |
localparam VERTICAL_BLANKING = 20; |
|
|
// -------------------------------------------------------------------- |
// |
localparam AVF_N = BYTES_PER_PIXEL * OUTPUTS_PER_TILE; // data bus width in bytes |
localparam AVF_U = 1; // TUSER width |
|
axis_if #(.N(AVF_N), .U(AVF_U)) axis_in[TILES](.*); |
axis_if #(.N(AVF_N), .U(AVF_U)) axis_out[TILES](.*); |
|
|
// -------------------------------------------------------------------- |
// |
axis_register_slice #(.N(AVF_N), .U(AVF_U)) |
dut |
( |
.axis_en(1'b1), |
.axis_in(axis_in.slave[0]), |
.axis_out(axis_out.master[0]), |
.* |
); |
|
|
// -------------------------------------------------------------------- |
// |
import axis_video_frame_bfm_pkg::*; |
import avf_agent_class_pkg::*; |
|
|
// -------------------------------------------------------------------- |
// |
avf_agent_config_class avf_agent_config_h; |
avf_agent_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE) avf_agent_h; |
|
initial |
begin |
|
avf_agent_config_h = new |
( |
.width(WIDTH), |
.height(HEIGHT), |
.bytes_per_pixel(BYTES_PER_PIXEL), |
.bits_per_pixel(BITS_PER_PIXEL), |
.tiles(TILES), |
.outputs_per_tile(OUTPUTS_PER_TILE), |
.name("AVF_"), |
.vertical_blanking(VERTICAL_BLANKING) |
); |
|
avf_agent_config_h.tile[0].direction = RIGHT_DOWN; |
|
avf_agent_h = new |
( |
.avf_agent_config(avf_agent_config_h), |
.avf_axis_in_if(axis_out), |
.avf_axis_out_if(axis_in) |
); |
|
avf_agent_h.init(); |
|
end |
|
|
// -------------------------------------------------------------------- |
// sim models |
// | | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ |
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
|
// -------------------------------------------------------------------- |
// |
|
|
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ |
// | | | | | | | | | | | | | | | | | |
// sim models |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// debug wires |
for(genvar j = 0; j < TILES; j++) |
axis_video_debug #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE) avf_debug(axis_out[j]); |
|
|
// -------------------------------------------------------------------- |
// test |
the_test test( tb_clk, tb_rst ); |
|
initial |
begin |
|
test.run_the_test(); |
|
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench done.", $time); |
$display("^^^---------------------------------"); |
|
$display("^^^---------------------------------"); |
|
$stop(); |
|
end |
|
endmodule |
|
|
|
/axi4_stream_lib/sim/src/legacy/tb_axis_to_axi4_agent_class_pkg.sv
0,0 → 1,158
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
package tb_axis_to_axi4_agent_class_pkg; |
|
// -------------------------------------------------------------------- |
// |
import axi4_memory_pkg::*; |
import axis_bfm_pkg::*; |
|
|
// -------------------------------------------------------------------- |
// |
class tb_axis_to_axi4_agent_class #(N, A, I, D, U); |
|
axi4_memory_class #(A, N, I) m_h; |
axis_tx_bfm_class #(N, I, D, U) s_h; |
memory_tr_class #(A, N, I) m_tr_h; |
axis_tr_class #(N, I, D, U) s_tr_h; |
|
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m; |
virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in; |
|
mailbox #(memory_tr_class #(A, N, I)) q; |
|
|
// -------------------------------------------------------------------- |
// |
task wait_for_sof; |
@(posedge axis_in.cb_s.tuser); |
$display("^^^ %16.t | %m", $time); |
endtask: wait_for_sof |
|
|
// -------------------------------------------------------------------- |
// |
task wait_for_dma_done(int bvalid_count); |
repeat(bvalid_count) |
@(axi4_m.cb_s iff axi4_m.cb_m.bvalid & axi4_m.cb_s.bready); |
$display("^^^ %16.t | %m", $time); |
endtask: wait_for_dma_done |
|
|
// -------------------------------------------------------------------- |
// |
task random_transaction(int addr, int size, int stride); |
m_h.clear_all(); |
m_tr_h = new(); |
m_tr_h.random(addr, size); |
q.put(m_tr_h); |
|
$display("^^^ %16.t | %m | m_tr_h.data.size = %x", $time, m_tr_h.data.size); |
for(int i = 0; i < m_tr_h.data.size; i += N) |
begin |
s_tr_h = new(); |
for(int k = 0; k < N; k++) |
begin |
s_tr_h.tdata[k*8 +: 8] = m_tr_h.data[i + k]; |
end |
|
if(i == 0) |
s_tr_h.tuser = 'b1; |
else |
s_tr_h.tuser = 'b0; |
|
if(i + N < m_tr_h.data.size) |
s_tr_h.tlast = 1'b0; |
else |
s_tr_h.tlast = 1'b1; |
|
s_h.q.put(s_tr_h); |
end |
|
wait_for_dma_done(size / stride); |
endtask: random_transaction |
|
|
// -------------------------------------------------------------------- |
// |
task automatic compare(int offset); |
byte data[]; |
|
$display("^^^ %16.t | %m", $time); |
$display("^^^ %16.t | q.num = %d", $time, q.num); |
$display("^^^ %16.t | s_h.q.num = %d", $time, s_h.q.num); |
$display("^^^ %16.t | m_tr_h.data.size = %d", $time, m_tr_h.data.size); |
|
if(q.try_get(m_tr_h) == 0) |
begin |
$display("!!! %16.t | ERROR!!! try_get(m_tr_h) == 0", $time); |
$stop; |
end |
|
data = new[m_tr_h.data.size]; |
m_h.dump_words(offset, data); |
|
foreach(m_tr_h.data[i]) |
if(data[i] != m_tr_h.data[i]) |
begin |
$display("!!! %16.t | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^", $time); |
$display("!!! %16.t | %x ", $time, i); |
$display("!!! %16.t | %x | %x |", $time, data[i], m_tr_h.data[i]); |
$stop; |
end |
|
$display("^^^ %16.t | %m | done!", $time); |
|
endtask: compare |
|
|
//-------------------------------------------------------------------- |
// |
function new |
( |
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m, |
virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in |
); |
|
this.axi4_m = axi4_m; |
this.axis_in = axis_in; |
m_h = new(axi4_m); |
s_h = new(axis_in); |
q = new(); |
endfunction: new |
|
|
// -------------------------------------------------------------------- |
// |
endclass: tb_axis_to_axi4_agent_class |
|
// -------------------------------------------------------------------- |
// |
endpackage: tb_axis_to_axi4_agent_class_pkg |
/axi4_stream_lib/sim/src/legacy/tb_axis_upsizer.sv
0,0 → 1,144
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module tb_top(); |
|
// -------------------------------------------------------------------- |
// test bench clock & reset |
wire clk_200mhz; |
wire tb_clk = clk_200mhz; |
wire tb_rst; |
|
tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst); |
|
|
// -------------------------------------------------------------------- |
// |
wire tb_rst_s; |
wire aclk = tb_clk; |
wire aresetn = ~tb_rst_s; |
|
sync_reset |
sync_reset_i(aclk, tb_rst, tb_rst_s); |
|
|
// -------------------------------------------------------------------- |
// |
import tb_axis_upsizer_class_pkg::*; |
|
|
// -------------------------------------------------------------------- |
// |
axis_if #(.N(AVF_N), .U(AVF_U)) axis_in(.*); |
axis_if #(.N(AVF_N * S), .U(AVF_U * S)) axis_out(.*); |
|
|
// -------------------------------------------------------------------- |
// |
axis_upsizer |
#( |
.N(AVF_N), // data bus width in bytes |
.I(1), // TID width |
.D(1), // TDEST width |
.U(AVF_U), // TUSER width |
.S(S), // tdata size multiplier |
.USE_TSTRB(0), // set to 1 to enable, 0 to disable |
.USE_TKEEP(0), // set to 1 to enable, 0 to disable |
.BYTES_PER_TUSER(0) // bytes per tuser bit. Set to 0 for transfer based. |
) |
dut(.*); |
|
|
// -------------------------------------------------------------------- |
// sim models |
// | | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ |
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
|
// -------------------------------------------------------------------- |
// |
axis_checker #(.N(AVF_N * S), .I(1), .D(1), .U(AVF_U)) |
axis_checker_i(.*); |
|
|
// -------------------------------------------------------------------- |
// |
axis_if #(.N(AVF_N * S), .U(AVF_U)) avf_axis_in_if(.*); |
|
assign axis_out.tready = avf_axis_in_if.tready; |
assign avf_axis_in_if.tvalid = axis_out.tvalid; |
assign avf_axis_in_if.tdata = axis_out.tdata; |
assign avf_axis_in_if.tuser = {axis_out.tuser[(AVF_U*S)-1], axis_out.tuser[1:0]}; |
assign avf_axis_in_if.tlast = axis_out.tlast; |
|
|
// -------------------------------------------------------------------- |
// |
tb_axis_upsizer_class a_h; |
|
initial |
a_h = new(.avf_axis_in_if(avf_axis_in_if), .avf_axis_out_if(axis_in)); |
|
|
// -------------------------------------------------------------------- |
// |
|
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ |
// | | | | | | | | | | | | | | | | | |
// sim models |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// debug wires |
|
|
// -------------------------------------------------------------------- |
// test |
the_test test( tb_clk, tb_rst ); |
|
initial |
begin |
|
test.run_the_test(); |
|
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench done.", $time); |
$display("^^^---------------------------------"); |
|
$display("^^^---------------------------------"); |
|
$stop(); |
|
end |
|
endmodule |
|
|
|
/axi4_stream_lib/sim/src/legacy/tb_axis_upsizer_agent_class_pkg.sv
0,0 → 1,129
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
package tb_axis_upsizer_agent_class_pkg; |
|
// -------------------------------------------------------------------- |
// |
import video_frame_pkg::*; |
import axis_video_frame_bfm_pkg::*; |
|
|
// -------------------------------------------------------------------- |
// |
class tb_axis_upsizer_agent_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE, AVF_N, AVF_U, S); |
|
virtual axis_if #(.N(AVF_N * S), .U(AVF_U)) avf_axis_in_if; |
virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_out_if; |
|
avf_config_class c_h; |
|
avf_tx_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE, AVF_U) tx_h; |
avf_rx_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE * S, AVF_U) rx_h; |
|
video_frame_class clone_h; |
video_frame_class sent_f_h; |
video_frame_class rx_f_h; |
|
mailbox #(video_frame_class) q; |
|
|
// -------------------------------------------------------------------- |
// |
virtual task |
queue_frame |
( |
string pattern = "", |
int pixel = 0 |
); |
|
if(pattern != "") |
tx_h.make_frame(pattern, pixel); |
|
clone_h = tx_h.tx_bfm_h[0].f_h.clone(); |
tx_h.tx_bfm_h[0].put(clone_h); |
q.put(clone_h); |
|
$display("^^^ %16.t | %m | using %s pattern", $time, pattern); |
|
endtask: queue_frame |
|
|
// -------------------------------------------------------------------- |
// |
virtual task automatic |
compare_frame; |
|
int mismatch_count; |
|
$display("^^^ %16.t | %m", $time); |
|
q.get(sent_f_h); |
rx_h.rx_bfm_h[0].get(rx_f_h); |
mismatch_count = sent_f_h.compare(8, rx_f_h); |
|
endtask: compare_frame |
|
|
//-------------------------------------------------------------------- |
// |
function void init(avf_config_class in_c_h, avf_config_class out_c_h); |
|
rx_h = new(in_c_h, '{avf_axis_in_if}); |
tx_h = new(out_c_h, '{avf_axis_out_if}); |
|
this.q = new(); |
|
endfunction: init |
|
|
//-------------------------------------------------------------------- |
// |
function new |
( |
virtual axis_if #(.N(AVF_N * S), .U(AVF_U)) avf_axis_in_if, |
virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_out_if |
); |
|
this.avf_axis_in_if = avf_axis_in_if; |
this.avf_axis_out_if = avf_axis_out_if; |
endfunction: new |
|
|
// -------------------------------------------------------------------- |
// |
endclass: tb_axis_upsizer_agent_class |
|
// -------------------------------------------------------------------- |
// |
endpackage: tb_axis_upsizer_agent_class_pkg |
|
|
|
|
|
/axi4_stream_lib/sim/src/legacy/tb_axis_upsizer_class_pkg.sv
0,0 → 1,114
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
package tb_axis_upsizer_class_pkg; |
|
// -------------------------------------------------------------------- |
// |
import axis_video_frame_bfm_pkg::*; |
import tb_axis_upsizer_agent_class_pkg::*; |
|
|
// -------------------------------------------------------------------- |
// |
localparam WIDTH = 32; // tile width |
localparam HEIGHT = 16; // tile height |
localparam OUTPUTS_PER_TILE = 1; // outputs per tile |
localparam BYTES_PER_PIXEL = 2; |
localparam BITS_PER_PIXEL = 16; |
localparam VERTICAL_BLANKING = 20; |
|
localparam S = 4; // tdata size multiplier |
localparam AVF_N = BYTES_PER_PIXEL * OUTPUTS_PER_TILE; // data bus width in bytes |
localparam AVF_U = 3; // TUSER width |
|
|
// -------------------------------------------------------------------- |
// |
class tb_axis_upsizer_class |
extends tb_axis_upsizer_agent_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE, AVF_N, AVF_U, S); |
|
avf_config_class in_c_h; |
avf_config_class out_c_h; |
avf_tile_config_t tile_config[]; |
|
|
//-------------------------------------------------------------------- |
// |
function new |
( |
virtual axis_if #(.N(AVF_N * S), .U(AVF_U)) avf_axis_in_if, |
virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_out_if |
); |
|
super.new(avf_axis_in_if, avf_axis_out_if); |
|
this.tile_config = new[1]; |
this.tile_config[0].direction = RIGHT_DOWN; |
|
this.in_c_h = new |
( |
.width(WIDTH), |
.height(HEIGHT), |
.bytes_per_pixel(BYTES_PER_PIXEL), |
.bits_per_pixel(BITS_PER_PIXEL), |
.pixels_per_clk(OUTPUTS_PER_TILE * S), |
.name("IN_"), |
.vertical_blanking(VERTICAL_BLANKING), |
.tile(tile_config) |
); |
|
this.out_c_h = new |
( |
.width(WIDTH), |
.height(HEIGHT), |
.bytes_per_pixel(BYTES_PER_PIXEL), |
.bits_per_pixel(BITS_PER_PIXEL), |
.pixels_per_clk(OUTPUTS_PER_TILE), |
.name("OUT_"), |
.vertical_blanking(VERTICAL_BLANKING), |
.tile(tile_config) |
); |
|
super.init(in_c_h, out_c_h); |
|
endfunction: new |
|
|
// -------------------------------------------------------------------- |
// |
endclass: tb_axis_upsizer_class |
|
// -------------------------------------------------------------------- |
// |
endpackage: tb_axis_upsizer_class_pkg |
|
|
|
|
|
/axi4_stream_lib/src/axis_down_shift.sv
0,0 → 1,178
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2019 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
// -------------------------------------------------------------------- |
module |
axis_down_shift_tuser_mux |
#( |
U = 1, // TUSER width |
logic [U-1:0] TUSER_MASK[3] = '{ {U{1'b0}}, // first |
{U{1'b0}}, // middle |
{U{1'b0}} } // last |
) |
( |
axis_if axis_in, |
axis_if axis_out, |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
endmodule |
|
// -------------------------------------------------------------------- |
module |
axis_down_shift |
#( |
N, // axis_in tdata bus width in bytes |
S, // tdata size divisor |
I = 1, // TID width |
D = 1, // TDEST width |
U = 1, // TUSER width |
logic [U-1:0] TUSER_MASK[3] = '{ {U{1'b0}}, // first |
{U{1'b0}}, // middle |
{U{1'b0}} } // last |
) |
( |
axis_if axis_in, |
axis_if axis_out, |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
// synthesis translate_off |
initial |
begin |
assert(S > 1) else $fatal; |
assert(N % S == 0) else $fatal; |
end |
// synthesis translate_on |
// -------------------------------------------------------------------- |
|
// -------------------------------------------------------------------- |
localparam N_OUT = (N / S); // width of axis_out.tdata in bytes |
localparam W = N_OUT * 8; // width of axis_out.tdata in bits |
localparam UB = (W*(S-1))-1; |
|
// -------------------------------------------------------------------- |
axis_if #(.N(N_OUT), .I(I), .D(D), .U(U)) a_down(.*); |
wire almost_last; |
|
// -------------------------------------------------------------------- |
enum reg [2:0] |
{ |
FIRST = 3'b001, |
MIDDLE = 3'b010, |
LAST = 3'b100 |
} state, next_state; |
|
// -------------------------------------------------------------------- |
always_ff @(posedge aclk) |
if(~aresetn) |
state <= FIRST; |
else |
state <= next_state; |
|
// -------------------------------------------------------------------- |
always_comb |
case(state) |
FIRST: if(axis_in.tvalid & a_down.tready) |
if(almost_last) |
next_state <= LAST; |
else |
next_state <= MIDDLE; |
else |
next_state <= FIRST; |
|
MIDDLE: if(almost_last & a_down.tready) |
next_state <= LAST; |
else |
next_state <= MIDDLE; |
|
LAST: if(a_down.tready) |
next_state <= FIRST; |
else |
next_state <= LAST; |
|
default: next_state <= FIRST; |
endcase |
|
// -------------------------------------------------------------------- |
reg [$clog2(S)-1:0] index; |
assign almost_last = (index >= S - 2); |
|
always_ff @(posedge aclk) |
if(next_state == FIRST) |
index <= 0; |
else if(a_down.tready) |
index <= index + 1; |
|
// -------------------------------------------------------------------- |
reg [UB:0] remainder; |
wire [W-1:0] tdata_pass = axis_in.tdata[W-1:0]; |
wire [W-1:0] tdata_shift = remainder[W-1:0]; |
|
always_ff @(posedge aclk) |
if(state == FIRST) |
remainder <= axis_in.tdata[(N*8)-1:W]; |
else if(a_down.tready) |
remainder <= { {W{1'b0}}, remainder[UB:W]}; |
|
// -------------------------------------------------------------------- |
reg [U-1:0] tuser; |
|
generate |
for(genvar j = 0; j < U; j++) |
begin: tuser_gen |
always_comb |
case(state) |
FIRST: tuser[j] = TUSER_MASK[0][j] ? axis_in.tuser[j] : 0; |
MIDDLE: tuser[j] = TUSER_MASK[1][j] ? axis_in.tuser[j] : 0; |
LAST: tuser[j] = TUSER_MASK[2][j] ? axis_in.tuser[j] : 0; |
default: tuser[j] = 0; |
endcase |
end |
endgenerate |
|
// -------------------------------------------------------------------- |
assign axis_in.tready = (state == LAST) & (next_state != LAST); |
// assign a_down.tstrb = axis_in.tstrb; |
// assign a_down.tkeep = axis_in.tkeep; |
assign a_down.tid = axis_in.tid; |
assign a_down.tdest = axis_in.tdest; |
assign a_down.tvalid = axis_in.tvalid; |
assign a_down.tlast = (state == LAST) ? axis_in.tlast : 0; |
assign a_down.tuser = tuser; |
assign a_down.tdata = (state == FIRST) ? tdata_pass : tdata_shift; |
|
// -------------------------------------------------------------------- |
axis_register_slice #(.N(N_OUT), .I(I), .D(D), .U(U)) |
slice_i(.axis_in(a_down), .*); |
|
// -------------------------------------------------------------------- |
endmodule |
/axi4_stream_lib/src/axis_fanout.sv
0,0 → 1,110
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2019 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
axis_fanout #(F) |
( |
axis_if axis_in, |
axis_if axis_out[F], |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
wire [F-1:0] handshake; |
wire [F-1:0] stalled; |
reg [F-1:0] transfer_stalled; |
wire [F-1:0] out_tready; |
wire all_ready = &out_tready; |
wire [F-1:0] done; |
wire all_done = &done; |
|
// -------------------------------------------------------------------- |
enum reg [1:0] |
{ |
FANOUT = 2'b01, |
STALL = 2'b10 |
} state, next_state; |
|
// -------------------------------------------------------------------- |
always_ff @(posedge aclk) |
if(~aresetn) |
state <= FANOUT; |
else |
state <= next_state; |
|
// -------------------------------------------------------------------- |
always_comb |
case(state) |
FANOUT: if(~axis_in.tvalid) |
next_state = FANOUT; |
else if(all_ready) |
next_state = FANOUT; |
else |
next_state = STALL; |
|
STALL: if(all_done) |
next_state = FANOUT; |
else |
next_state = STALL; |
|
default: next_state = FANOUT; |
endcase |
|
// -------------------------------------------------------------------- |
generate |
for(genvar j = 0; j < F; j++) |
begin: tready_gen |
// -------------------------------------------------------------------- |
assign handshake[j] = axis_in.tvalid & axis_out[j].tready; |
assign stalled[j] = axis_in.tvalid & ~axis_out[j].tready; |
assign done[j] = ~transfer_stalled[j] | handshake[j]; |
|
always_ff @(posedge aclk) |
if(handshake[j]) |
transfer_stalled[j] <= 0; |
else if(stalled[j]) |
transfer_stalled[j] <= 1; |
|
// -------------------------------------------------------------------- |
assign out_tready[j] = axis_out[j].tready; |
assign axis_out[j].tlast = axis_in.tlast; |
assign axis_out[j].tuser = axis_in.tuser; |
assign axis_out[j].tdata = axis_in.tdata; |
assign axis_out[j].tstrb = axis_in.tstrb; |
assign axis_out[j].tkeep = axis_in.tkeep; |
assign axis_out[j].tid = axis_in.tid; |
assign axis_out[j].tdest = axis_in.tdest; |
assign axis_out[j].tvalid = (state == FANOUT) ? axis_in.tvalid : transfer_stalled[j]; |
end |
endgenerate |
|
// -------------------------------------------------------------------- |
assign axis_in.tready = (state == FANOUT) ? all_ready : (next_state == FANOUT); |
|
// -------------------------------------------------------------------- |
endmodule |
/basal/src/ROM/axis_rom.sv
0,0 → 1,128
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2019 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
axis_rom |
#( |
int N, |
int A, |
string FILE_NAME, |
int START=0, |
int STOP=2**A |
) |
( |
axis_if axis_out, |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
wire wr_full; |
wire rd_empty; |
wire rd_en = axis_out.tready & axis_out.tvalid; |
|
// -------------------------------------------------------------------- |
enum reg [2:0] |
{ |
INIT = 3'b001, |
STALLED = 3'b010, |
PRIMED = 3'b100 |
} state, next_state; |
|
// -------------------------------------------------------------------- |
always_ff @(posedge aclk) |
if(~aresetn) |
state <= INIT; |
else |
state <= next_state; |
|
// -------------------------------------------------------------------- |
always_comb |
case(state) |
INIT: next_state <= STALLED; |
|
STALLED: if(~wr_full) |
next_state <= PRIMED; |
else |
next_state <= STALLED; |
|
PRIMED: if(rd_empty | (~wr_full & rd_en)) |
next_state <= PRIMED; |
else |
next_state <= STALLED; |
|
default: next_state <= INIT; |
endcase |
|
// -------------------------------------------------------------------- |
wire [(N*8)-1:0] q; |
reg [(A-1):0] addr; |
|
rom #((N*8), A, FILE_NAME) rom(.clk(aclk), .*); |
|
// -------------------------------------------------------------------- |
wire [N*8:0] wr_data; |
wire [N*8:0] rd_data; |
wire wr_en = (state == PRIMED); |
|
tiny_sync_fifo #((N*8)+1) fifo(.clk(aclk), .reset(~aresetn), .*); |
|
// -------------------------------------------------------------------- |
reg increment; |
|
always_comb |
case({state, next_state}) |
{STALLED, PRIMED}: increment <= 1; |
{PRIMED, PRIMED}: increment <= 1; |
default: increment <= 0; |
endcase |
|
// -------------------------------------------------------------------- |
wire stop = increment & (addr >= STOP - START - 1); |
|
always_ff @(posedge aclk) |
if(~aresetn | stop) |
addr <= 0; |
else if(increment) |
addr <= addr + 1; |
|
// -------------------------------------------------------------------- |
reg tlast; |
|
always_ff @(posedge aclk) |
if(stop) |
tlast <= 1; |
else if(~aresetn | wr_en) |
tlast <= 0; |
|
// -------------------------------------------------------------------- |
assign axis_out.tvalid = ~rd_empty; |
assign {axis_out.tlast, axis_out.tdata} = rd_data; |
assign wr_data = {tlast, q}; |
|
// -------------------------------------------------------------------- |
endmodule |
/basal/src/ROM/rom.sv
0,0 → 1,46
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2019 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
rom |
#( |
int W, |
int A, |
string FILE_NAME |
) |
( |
input [(A-1):0] addr, |
input clk, |
output reg [(W-1):0] q |
); |
reg [W-1:0] rom[2**A-1:0]; |
initial |
$readmemh(FILE_NAME, rom); |
|
always @(posedge clk) |
q <= rom[addr]; |
endmodule |
/sim/libs/axi4_lib_verilog/axi4_stream_base.f
3,19 → 3,14
+define+USE_MOD_PORTS |
|
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_if.sv |
${LIB_BASE_DIR}/axi4_stream_lib/src/data_to_axis_fsm.sv |
|
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_register_slice.sv |
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_map_fifo.sv |
|
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_mux.sv |
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_alias.sv |
|
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_downsizer.sv |
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_upsizer.sv |
|
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_eop_set.sv |
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_eop_mux.sv |
|
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_catenate.sv |
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_switch.sv |
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_fanout.sv |
/video/sim/tests/tb_avf_kernel_1x_buffer/files.f
0,0 → 1,10
# |
|
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_down_shift.sv |
|
${PROJECT_DIR}/src/avf_line_buffer_merge.sv |
${PROJECT_DIR}/src/avf_line_buffer_row.sv |
${PROJECT_DIR}/src/avf_line_buffer.sv |
|
${PROJECT_DIR}/src/avf_kernel_buffer.sv |
${PROJECT_DIR}/src/avf_kernel_1x_buffer.sv |
/video/sim/tests/tb_avf_kernel_1x_buffer/init_test.do
0,0 → 1,31
# ------------------------------------ |
# |
# ------------------------------------ |
|
global env |
|
# setup environment |
do ../../../../scripts/sim_env.do |
set env(SIM_TARGET) fpga |
|
radix -hexadecimal |
|
make_lib work 1 |
|
sim_compile_lib $env(LIB_BASE_DIR) tb_packages |
sim_compile_lib $env(LIB_BASE_DIR) bfm_packages |
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib |
sim_compile_lib $env(LIB_BASE_DIR) axi4_lib |
sim_compile_lib $env(LIB_BASE_DIR) sim |
|
# compile simulation files |
vlog -f ./tb_pkg_files.f |
vlog -f ./tb_files.f |
|
# |
vlog -f ./files.f |
|
# run the sim |
sim_run_test |
|
|
/video/sim/tests/tb_avf_kernel_1x_buffer/s_debug.svh
0,0 → 1,55
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2018 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
class s_debug extends s_avf_base; |
`uvm_object_utils(s_debug) |
|
// -------------------------------------------------------------------- |
task body(); |
fork |
begin |
#(100us); |
$stop; |
end |
join_none |
|
avf_api_h.put_frame("counting"); |
avf_api_h.put_frame("counting"); |
// avf_api_h.put_frame("counting"); |
// avf_api_h.put_frame("counting"); |
// avf_api_h.put_frame("counting"); |
// avf_api_h.put_frame("constant", 16'habba); |
// avf_api_h.put_frame("horizontal"); |
// avf_api_h.put_frame("vertical"); |
// avf_api_h.put_frame("random"); |
|
avf_api_h.send_frame_buffer(m_sequencer, this); |
#(2us); |
endtask: body |
|
// -------------------------------------------------------------------- |
endclass : s_debug |
/video/sim/tests/tb_avf_kernel_1x_buffer/sim.do
0,0 → 1,10
# |
# |
|
quit -sim |
|
# vsim -suppress 12110 -novopt work.tb_top |
vsim -f ./sim.f work.tb_top |
|
# log all signals |
log /* -r |
/video/sim/tests/tb_avf_kernel_1x_buffer/sim.f
0,0 → 1,10
# |
# |
|
-voptargs=+acc=npr+/tb_top |
-voptargs=+acc=npr+/tb_top/dut |
|
-voptargs=+acc=npr+/tb_top/dut/kernel_i/ |
-voptargs=+acc=npr+/tb_top/dut/kernel_i/line_buffer_i/ |
|
-voptargs=+acc=npr+/tb_top/dut/down_i/ |
/video/sim/tests/tb_avf_kernel_1x_buffer/t_debug.svh
0,0 → 1,64
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2018 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
class t_debug extends t_top_base; |
`uvm_component_utils(t_debug) |
|
// -------------------------------------------------------------------- |
function new(string name = "t_debug", uvm_component parent); |
super.new(name, parent); |
endfunction |
|
// -------------------------------------------------------------------- |
function void end_of_elaboration_phase(uvm_phase phase); |
uvm_phase run_phase = uvm_run_phase::get(); |
run_phase.phase_done.set_drain_time(this, 100ns); |
endfunction |
|
// -------------------------------------------------------------------- |
function void final_phase(uvm_phase phase); |
super.final_phase(phase); |
$display("^^^ %16.t | %m | Test Done!!!", $time); |
$stop; |
endfunction : final_phase |
|
// -------------------------------------------------------------------- |
virtual task run_phase(uvm_phase phase); |
s_debug seq = s_debug::type_id::create("seq"); |
s_avf_slave_base s_seq = s_avf_slave_base::type_id::create("s_seq"); |
s_seq.sequencer_h = env_h.s_agent_h.sequencer_h; |
fork |
s_seq.start(env_h.s_agent_h.sequencer_h); |
join_none |
seq.init(env_h.cfg_h.m_cfg_h.c_h); |
phase.raise_objection(this); |
seq.start(env_h.m_agent_h.sequencer_h); |
phase.drop_objection(this); |
endtask : run_phase |
|
// -------------------------------------------------------------------- |
endclass : t_debug |
/video/sim/tests/tb_avf_kernel_1x_buffer/t_top_base.svh
0,0 → 1,43
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2018 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
virtual class t_top_base extends uvm_test; |
`uvm_component_utils(t_top_base); |
tb_env env_h; |
|
// -------------------------------------------------------------------- |
function new (string name, uvm_component parent); |
super.new(name,parent); |
endfunction : new |
|
// -------------------------------------------------------------------- |
function void build_phase(uvm_phase phase); |
env_h = tb_env::type_id::create("env_h",this); |
endfunction : build_phase |
|
// -------------------------------------------------------------------- |
endclass : t_top_base |
/video/sim/tests/tb_avf_kernel_1x_buffer/tb_dut_config.svh
0,0 → 1,58
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2018 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
class tb_dut_config #(N, U); |
|
avf_config #(N, U) m_cfg_h; // master |
avf_config #(N, U) s_cfg_h; // slave |
|
// -------------------------------------------------------------------- |
// |
function void init |
( int pixels_per_line |
, int lines_per_frame |
, int bits_per_pixel |
); |
m_cfg_h.init( pixels_per_line |
, lines_per_frame |
, bits_per_pixel |
); |
s_cfg_h.init( 9 |
, 30 |
, bits_per_pixel |
); |
endfunction: init |
|
|
// -------------------------------------------------------------------- |
function new(virtual axis_if #(.N(N), .U(U)) m_vif, virtual axis_if #(.N(N), .U(U)) s_vif); |
m_cfg_h = new(m_vif, UVM_ACTIVE); |
s_cfg_h = new(s_vif, UVM_ACTIVE); |
endfunction : new |
|
// -------------------------------------------------------------------- |
endclass |
/video/sim/tests/tb_avf_kernel_1x_buffer/tb_env.svh
0,0 → 1,65
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2018 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
class tb_env extends uvm_env; |
`uvm_component_utils(tb_env); |
|
// -------------------------------------------------------------------- |
tb_dut_config #(N, U) cfg_h; |
// coverage coverage_h; |
avf_scoreboard scoreboard_h; |
avf_master_agent #(N, U) m_agent_h; |
avf_slave_agent #(N, U) s_agent_h; |
|
// -------------------------------------------------------------------- |
function new (string name, uvm_component parent); |
super.new(name,parent); |
endfunction : new |
|
// -------------------------------------------------------------------- |
function void build_phase(uvm_phase phase); |
if (!uvm_config_db #(tb_dut_config #(N, U))::get(this, "", "tb_dut_config", cfg_h)) |
`uvm_fatal(get_name(), "Couldn't get config object!") |
|
m_agent_h = avf_master_agent #(N, U)::type_id::create("m_agent_h", this); |
m_agent_h.cfg_h = cfg_h.m_cfg_h; |
m_agent_h.is_active = cfg_h.m_cfg_h.get_is_active(); |
|
s_agent_h = avf_slave_agent #(N, U)::type_id::create("s_agent_h", this); |
s_agent_h.cfg_h = cfg_h.s_cfg_h; |
s_agent_h.is_active = cfg_h.s_cfg_h.get_is_active(); |
|
scoreboard_h = avf_scoreboard::type_id::create("scoreboard_h", this); |
endfunction : build_phase |
|
// -------------------------------------------------------------------- |
function void connect_phase(uvm_phase phase); |
s_agent_h.monitor_h.ap.connect(scoreboard_h.analysis_export); |
endfunction : connect_phase |
|
// -------------------------------------------------------------------- |
endclass |
/video/sim/tests/tb_avf_kernel_1x_buffer/tb_files.f
0,0 → 1,5
# |
|
./tb_top_pkg.sv |
|
./tb_top.sv |
/video/sim/tests/tb_avf_kernel_1x_buffer/tb_pkg_files.f
0,0 → 1,4
# |
|
# +incdir+${LIB_BASE_DIR}/BFM/src/axis_video_frame |
${LIB_BASE_DIR}/BFM/src/axis_video_frame/avf_pkg.sv |
/video/sim/tests/tb_avf_kernel_1x_buffer/tb_top.sv
0,0 → 1,73
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2019 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module tb_top; |
import uvm_pkg::*; |
`include "uvm_macros.svh" |
import tb_top_pkg::*; |
|
// -------------------------------------------------------------------- |
wire clk_100mhz; |
wire tb_clk = clk_100mhz; |
wire tb_rst; |
|
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); |
|
// -------------------------------------------------------------------- |
wire aclk = clk_100mhz; |
wire tb_rst_s; |
wire aresetn = ~tb_rst_s; |
|
sync_reset sync_reset(aclk, tb_rst, tb_rst_s); |
|
// -------------------------------------------------------------------- |
axis_if #(.N(N), .U(U)) axis_in(.*); |
axis_if #(.N(N), .U(U)) axis_out(.*); |
axis_if #(.N(N), .U(U)) axis_stub(.*); |
|
// -------------------------------------------------------------------- |
avf_kernel_1x_buffer #(N, U, L, AW) dut(.*); |
|
// // -------------------------------------------------------------------- |
// bind dut axis_checker #(.N(N), .U(U), .MAXWAITS(256)) dut_in_b(.axis_in(axis_in)); |
// bind dut axis_checker #(.N(N), .U(U), .MAXWAITS(256)) dut_out_b(.axis_in(axis_out)); |
|
// -------------------------------------------------------------------- |
tb_dut_config #(N, U) cfg_h = new(axis_in, axis_out); |
|
initial |
begin |
cfg_h.init( .pixels_per_line(AW) |
, .lines_per_frame(AH) |
, .bits_per_pixel(B * 8) |
); |
uvm_config_db #(tb_dut_config #(N, U))::set(null, "*", "tb_dut_config", cfg_h); |
run_test("t_debug"); |
end |
|
// -------------------------------------------------------------------- |
endmodule |
/video/sim/tests/tb_avf_kernel_1x_buffer/tb_top_pkg.sv
0,0 → 1,50
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2018 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
package tb_top_pkg; |
import uvm_pkg::*; |
`include "uvm_macros.svh" |
import avf_pkg::*; |
|
// -------------------------------------------------------------------- |
localparam L = 3; // number of lines to buffer |
localparam B = 4; // BYTES_PER_PIXEL |
localparam T = 1; // pixels per clock |
localparam AW = 32; // active width |
localparam AH = 16; // active height |
localparam N = B * T; |
localparam U = 3; |
|
// -------------------------------------------------------------------- |
`include "tb_dut_config.svh" |
`include "tb_env.svh" |
`include "s_debug.svh" |
`include "t_top_base.svh" |
`include "t_debug.svh" |
|
// -------------------------------------------------------------------- |
endpackage |
/video/sim/tests/tb_avf_kernel_1x_buffer/wip.do
0,0 → 1,6
# |
|
# compile test bench files |
vlog -f ./tb_files.f |
vlog -f ./files.f |
|
/video/sim/tests/tb_avf_line_buffer/files.f
0,0 → 1,5
# |
|
${PROJECT_DIR}/src/avf_line_buffer_merge.sv |
${PROJECT_DIR}/src/avf_line_buffer_row.sv |
${PROJECT_DIR}/src/avf_line_buffer.sv |
/video/sim/tests/tb_avf_line_buffer/init_test.do
0,0 → 1,31
# ------------------------------------ |
# |
# ------------------------------------ |
|
global env |
|
# setup environment |
do ../../../../scripts/sim_env.do |
set env(SIM_TARGET) fpga |
|
radix -hexadecimal |
|
make_lib work 1 |
|
sim_compile_lib $env(LIB_BASE_DIR) tb_packages |
sim_compile_lib $env(LIB_BASE_DIR) bfm_packages |
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib |
sim_compile_lib $env(LIB_BASE_DIR) axi4_lib |
sim_compile_lib $env(LIB_BASE_DIR) sim |
|
# compile simulation files |
vlog -f ./tb_pkg_files.f |
vlog -f ./tb_files.f |
|
# |
vlog -f ./files.f |
|
# run the sim |
sim_run_test |
|
|
/video/sim/tests/tb_avf_line_buffer/s_debug.svh
0,0 → 1,55
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2018 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
class s_debug extends s_avf_base; |
`uvm_object_utils(s_debug) |
|
// -------------------------------------------------------------------- |
task body(); |
fork |
begin |
#(200us); |
$stop; |
end |
join_none |
|
avf_api_h.put_frame("counting"); |
avf_api_h.put_frame("counting"); |
avf_api_h.put_frame("counting"); |
avf_api_h.put_frame("counting"); |
avf_api_h.put_frame("counting"); |
// avf_api_h.put_frame("constant", 16'habba); |
// avf_api_h.put_frame("horizontal"); |
// avf_api_h.put_frame("vertical"); |
// avf_api_h.put_frame("random"); |
|
avf_api_h.send_frame_buffer(m_sequencer, this); |
#(2us); |
endtask: body |
|
// -------------------------------------------------------------------- |
endclass : s_debug |
/video/sim/tests/tb_avf_line_buffer/sim.do
0,0 → 1,10
# |
# |
|
quit -sim |
|
# vsim -suppress 12110 -novopt work.tb_top |
vsim -f ./sim.f work.tb_top |
|
# log all signals |
log /* -r |
/video/sim/tests/tb_avf_line_buffer/sim.f
0,0 → 1,9
# |
# |
|
-voptargs=+acc=npr+/tb_top |
-voptargs=+acc=npr+/tb_top/dut |
-voptargs=+acc=npr+/tb_top/dut/buffer_gen[0]/row_i/ |
-voptargs=+acc=npr+/tb_top/dut/buffer_gen[1]/row_i/ |
-voptargs=+acc=npr+/tb_top/dut/merge_i/ |
-voptargs=+acc=npr+/tb_top/dut/middle_fanout_gen[1]/fanout_i/ |
/video/sim/tests/tb_avf_line_buffer/t_debug.svh
0,0 → 1,64
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2018 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
class t_debug extends t_top_base; |
`uvm_component_utils(t_debug) |
|
// -------------------------------------------------------------------- |
function new(string name = "t_debug", uvm_component parent); |
super.new(name, parent); |
endfunction |
|
// -------------------------------------------------------------------- |
function void end_of_elaboration_phase(uvm_phase phase); |
uvm_phase run_phase = uvm_run_phase::get(); |
run_phase.phase_done.set_drain_time(this, 100ns); |
endfunction |
|
// -------------------------------------------------------------------- |
function void final_phase(uvm_phase phase); |
super.final_phase(phase); |
$display("^^^ %16.t | %m | Test Done!!!", $time); |
$stop; |
endfunction : final_phase |
|
// -------------------------------------------------------------------- |
virtual task run_phase(uvm_phase phase); |
s_debug seq = s_debug::type_id::create("seq"); |
s_avf_slave_base s_seq = s_avf_slave_base::type_id::create("s_seq"); |
s_seq.sequencer_h = env_h.s_agent_h.sequencer_h; |
fork |
s_seq.start(env_h.s_agent_h.sequencer_h); |
join_none |
seq.init(env_h.cfg_h.m_cfg_h.c_h); |
phase.raise_objection(this); |
seq.start(env_h.m_agent_h.sequencer_h); |
phase.drop_objection(this); |
endtask : run_phase |
|
// -------------------------------------------------------------------- |
endclass : t_debug |
/video/sim/tests/tb_avf_line_buffer/t_top_base.svh
0,0 → 1,43
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2018 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
virtual class t_top_base extends uvm_test; |
`uvm_component_utils(t_top_base); |
tb_env env_h; |
|
// -------------------------------------------------------------------- |
function new (string name, uvm_component parent); |
super.new(name,parent); |
endfunction : new |
|
// -------------------------------------------------------------------- |
function void build_phase(uvm_phase phase); |
env_h = tb_env::type_id::create("env_h",this); |
endfunction : build_phase |
|
// -------------------------------------------------------------------- |
endclass : t_top_base |
/video/sim/tests/tb_avf_line_buffer/tb_dut_config.svh
0,0 → 1,58
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2018 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
class tb_dut_config #(N, U, L); |
|
avf_config #(N/L, U) m_cfg_h; // master |
avf_config #(N, U) s_cfg_h; // slave |
|
// -------------------------------------------------------------------- |
// |
function void init |
( int pixels_per_line |
, int lines_per_frame |
, int bits_per_pixel |
); |
m_cfg_h.init( pixels_per_line |
, lines_per_frame |
, bits_per_pixel |
); |
s_cfg_h.init( pixels_per_line |
, lines_per_frame |
, bits_per_pixel |
); |
endfunction: init |
|
|
// -------------------------------------------------------------------- |
function new(virtual axis_if #(.N(N/L), .U(U)) m_vif, virtual axis_if #(.N(N), .U(U)) s_vif); |
m_cfg_h = new(m_vif, UVM_ACTIVE); |
s_cfg_h = new(s_vif, UVM_ACTIVE); |
endfunction : new |
|
// -------------------------------------------------------------------- |
endclass |
/video/sim/tests/tb_avf_line_buffer/tb_env.svh
0,0 → 1,65
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2018 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
class tb_env extends uvm_env; |
`uvm_component_utils(tb_env); |
|
// -------------------------------------------------------------------- |
tb_dut_config #(N, U, L) cfg_h; |
// coverage coverage_h; |
avf_scoreboard scoreboard_h; |
avf_master_agent #(N/L, U) m_agent_h; |
avf_slave_agent #(N, U) s_agent_h; |
|
// -------------------------------------------------------------------- |
function new (string name, uvm_component parent); |
super.new(name,parent); |
endfunction : new |
|
// -------------------------------------------------------------------- |
function void build_phase(uvm_phase phase); |
if (!uvm_config_db #(tb_dut_config #(N, U, L))::get(this, "", "tb_dut_config", cfg_h)) |
`uvm_fatal(get_name(), "Couldn't get config object!") |
|
m_agent_h = avf_master_agent #(N/L, U)::type_id::create("m_agent_h", this); |
m_agent_h.cfg_h = cfg_h.m_cfg_h; |
m_agent_h.is_active = cfg_h.m_cfg_h.get_is_active(); |
|
s_agent_h = avf_slave_agent #(N, U)::type_id::create("s_agent_h", this); |
s_agent_h.cfg_h = cfg_h.s_cfg_h; |
s_agent_h.is_active = cfg_h.s_cfg_h.get_is_active(); |
|
scoreboard_h = avf_scoreboard::type_id::create("scoreboard_h", this); |
endfunction : build_phase |
|
// -------------------------------------------------------------------- |
function void connect_phase(uvm_phase phase); |
s_agent_h.monitor_h.ap.connect(scoreboard_h.analysis_export); |
endfunction : connect_phase |
|
// -------------------------------------------------------------------- |
endclass |
/video/sim/tests/tb_avf_line_buffer/tb_files.f
0,0 → 1,5
# |
|
./tb_top_pkg.sv |
|
./tb_top.sv |
/video/sim/tests/tb_avf_line_buffer/tb_pkg_files.f
0,0 → 1,4
# |
|
# +incdir+${LIB_BASE_DIR}/BFM/src/axis_video_frame |
${LIB_BASE_DIR}/BFM/src/axis_video_frame/avf_pkg.sv |
/video/sim/tests/tb_avf_line_buffer/tb_top.sv
0,0 → 1,73
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2019 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module tb_top; |
import uvm_pkg::*; |
`include "uvm_macros.svh" |
import tb_top_pkg::*; |
|
// -------------------------------------------------------------------- |
wire clk_100mhz; |
wire tb_clk = clk_100mhz; |
wire tb_rst; |
|
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); |
|
// -------------------------------------------------------------------- |
wire aclk = clk_100mhz; |
wire tb_rst_s; |
wire aresetn = ~tb_rst_s; |
|
sync_reset sync_reset(aclk, tb_rst, tb_rst_s); |
|
// -------------------------------------------------------------------- |
axis_if #(.N(N/L), .U(U)) axis_in(.*); |
axis_if #(.N(N), .U(U)) axis_out(.*); |
axis_if #(.N(N), .U(U)) axis_stub(.*); |
|
// -------------------------------------------------------------------- |
avf_line_buffer #(N/L, U, L, AW) dut(.*); |
|
// -------------------------------------------------------------------- |
bind dut axis_checker #(.N(N), .U(U), .MAXWAITS(256)) dut_in_b(.axis_in(axis_in)); |
bind dut axis_checker #(.N(N), .U(U), .MAXWAITS(256)) dut_out_b(.axis_in(axis_out)); |
|
// -------------------------------------------------------------------- |
tb_dut_config #(N, U, L) cfg_h = new(axis_in, axis_out); |
|
initial |
begin |
cfg_h.init( .pixels_per_line(AW) |
, .lines_per_frame(AH) |
, .bits_per_pixel(B * 8) |
); |
uvm_config_db #(tb_dut_config #(N, U, L))::set(null, "*", "tb_dut_config", cfg_h); |
run_test("t_debug"); |
end |
|
// -------------------------------------------------------------------- |
endmodule |
/video/sim/tests/tb_avf_line_buffer/tb_top_pkg.sv
0,0 → 1,50
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2018 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
package tb_top_pkg; |
import uvm_pkg::*; |
`include "uvm_macros.svh" |
import avf_pkg::*; |
|
// -------------------------------------------------------------------- |
localparam L = 3; // number of lines to buffer |
localparam B = 4; // BYTES_PER_PIXEL |
localparam T = L; // pixels per clock |
localparam AW = 15; // active width |
localparam AH = 16; // active height |
localparam N = B * T; |
localparam U = 3; |
|
// -------------------------------------------------------------------- |
`include "tb_dut_config.svh" |
`include "tb_env.svh" |
`include "s_debug.svh" |
`include "t_top_base.svh" |
`include "t_debug.svh" |
|
// -------------------------------------------------------------------- |
endpackage |
/video/sim/tests/tb_avf_line_buffer/wip.do
0,0 → 1,6
# |
|
# compile test bench files |
vlog -f ./tb_files.f |
vlog -f ./files.f |
|
/video/src/avf_kernel_1x_buffer.sv
0,0 → 1,69
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2019 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
avf_kernel_1x_buffer #(N, U, L, AW) |
( |
axis_if axis_in, |
axis_if axis_out, |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
axis_if #(.N(N*L*L), .U(U+1)) a_buffer(.*); |
|
avf_kernel_buffer #(N, U, L, AW) |
kernel_i(.axis_out(a_buffer), .*); |
|
// -------------------------------------------------------------------- |
reg [(N*8)-1:0] kernel[L][L]; |
|
generate |
for(genvar j = 0; j < L * L; j++) |
begin: kernel_gen |
assign kernel[j/L][j%L] = a_buffer.tdata[j*N*8 +: N*8]; |
end |
endgenerate |
|
// -------------------------------------------------------------------- |
axis_if #(.N(N), .U(U+1)) a_out(.*); |
|
axis_alias alias_i(.axis_in(a_out), .*); |
|
// -------------------------------------------------------------------- |
assign a_buffer.tuser[3] = a_buffer.tvalid & a_buffer.tready; |
// EOF SOL SOF |
localparam logic[U:0] TUSER_MASK[3] = '{ {1'b0, 1'b0, 1'b1, 1'b1}, // first |
{1'b0, 1'b0, 1'b0, 1'b0}, // middle |
{1'b1, 1'b1, 1'b0, 1'b0} }; // last |
|
axis_down_shift #(.N(N*L*L), .S(L*L), .U(U+1), .TUSER_MASK(TUSER_MASK)) |
down_i(.axis_in(a_buffer), .axis_out(a_out), .*); |
|
// -------------------------------------------------------------------- |
endmodule |
/video/src/avf_kernel_buffer.sv
0,0 → 1,144
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2019 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
avf_kernel_buffer #(N, U, L, AW) |
( |
axis_if axis_in, |
axis_if axis_out, |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
axis_if #(.N(N*L), .U(U)) a_buffer(.*); |
|
avf_line_buffer #(N, U, L, AW) line_buffer_i(.axis_out(a_buffer), .*); |
|
// -------------------------------------------------------------------- |
localparam W = N * L * 8; |
localparam UB = (W*L) - 1; |
reg [UB:0] column; |
|
always_ff @(posedge aclk) |
if(a_buffer.tvalid & a_buffer.tready) |
column <= {a_buffer.tdata, column[UB:W]}; |
|
// -------------------------------------------------------------------- |
reg [(N*8)-1:0] kernel[L][L]; |
|
generate |
for(genvar j = 0; j < L * L; j++) |
begin: kernel_gen |
assign kernel[j/L][j%L] = column[j*N*8 +: N*8]; |
end |
endgenerate |
|
// -------------------------------------------------------------------- |
wire sof = a_buffer.tvalid & a_buffer.tready & a_buffer.tuser[0]; |
wire sol = a_buffer.tvalid & a_buffer.tready & a_buffer.tuser[1]; |
wire eol = a_buffer.tvalid & a_buffer.tready & a_buffer.tlast; |
wire eof = a_buffer.tvalid & a_buffer.tready & a_buffer.tuser[2]; |
wire primed; |
|
// -------------------------------------------------------------------- |
enum reg [4:0] |
{ |
PRIME = 5'b0_0001, |
SOL = 5'b0_0010, |
INITIALIZED = 5'b0_0100, |
READY = 5'b0_1000, |
EOL = 5'b1_0000 |
} state, next_state; |
|
// -------------------------------------------------------------------- |
always_ff @(posedge aclk) |
if(~aresetn) |
state <= PRIME; |
else |
state <= next_state; |
|
// -------------------------------------------------------------------- |
always_comb |
case(state) |
PRIME: if(primed) |
next_state = SOL; |
else |
next_state = PRIME; |
|
SOL: if(axis_out.tready) |
next_state = READY; |
else |
next_state = SOL; |
|
READY: if(eol) |
next_state = EOL; |
else |
next_state = READY; |
|
EOL: if(axis_out.tready) |
next_state = PRIME; |
else |
next_state = EOL; |
|
default: next_state = PRIME; |
endcase |
|
// -------------------------------------------------------------------- |
reg [$clog2(L)-1:0] count; |
assign primed = (count >= L - 1) & a_buffer.tvalid & a_buffer.tready; |
wire changing_state = (next_state != state); |
wire reset_counter = changing_state & (state != EOL); |
|
always_ff @(posedge aclk) |
if(~aresetn | reset_counter) |
count <= 0; |
else if(a_buffer.tvalid & a_buffer.tready) |
count <= count + 1; |
|
// -------------------------------------------------------------------- |
reg sof_r; |
|
always_ff @(posedge aclk) |
if(~aresetn | (state == READY)) |
sof_r <= 0; |
else if(sof) |
sof_r <= 1; |
|
// -------------------------------------------------------------------- |
assign a_buffer.tready = (state == PRIME) | axis_out.tready; |
assign axis_out.tvalid = (state != PRIME) & a_buffer.tvalid; |
assign axis_out.tdata = column; |
// assign axis_out.tlast = a_buffer.tlast; |
assign axis_out.tlast = (state == EOL); |
// assign axis_out.tuser = a_buffer.tuser; |
assign axis_out.tuser[0] = (state == SOL) & sof_r; |
assign axis_out.tuser[1] = (state == SOL); |
assign axis_out.tuser[2] = (state == EOL) & eof; |
|
// -------------------------------------------------------------------- |
endmodule |
/video/src/avf_line_buffer.sv
0,0 → 1,137
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2019 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
avf_line_buffer #(N, U, L, AW) |
( |
axis_if axis_in, |
axis_if axis_out, |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
localparam W = (N*8) + U + 1; // tdata + tuser + tlast |
localparam F = 2; // fanout for the buffer row output |
|
// -------------------------------------------------------------------- |
axis_if #(.N(N), .U(U)) row_out[L][F](.*); |
axis_if #(.N(N), .U(U)) buffer_out[L-1](.*); |
wire [L-2:0] zero_pad; |
wire [L-2:0] initialized; |
wire all_initialized = &initialized; |
wire enable; |
wire eof_trailing = row_out[0][0].tready & row_out[0][0].tvalid & row_out[0][0].tuser[2]; |
wire eof_leading = row_out[L-1][0].tready & row_out[L-1][0].tvalid & row_out[L-1][0].tuser[2]; |
|
// -------------------------------------------------------------------- |
generate |
for(genvar j = 0; j < L-1; j++) |
begin: buffer_gen |
avf_line_buffer_row #(N, W, AW, j) |
row_i |
( |
.axis_in(row_out[j+1][1]), |
.axis_out(buffer_out[j]), |
.zero_pad(zero_pad[j]), |
.initialized(initialized[j]), |
.* |
); |
end |
endgenerate |
|
// -------------------------------------------------------------------- |
generate |
for(genvar j = 1; j < L-1; j++) |
begin: middle_fanout_gen |
axis_fanout #(F) |
fanout_i(.axis_in(buffer_out[j]), .axis_out(row_out[j]), .*); |
end |
endgenerate |
|
// -------------------------------------------------------------------- |
axis_fanout #(F) trailing_row_i(.axis_out(row_out[L-1]), .*); |
axis_alias leading_row_i(buffer_out[0], row_out[0][0]); |
|
// -------------------------------------------------------------------- |
enum reg [3:0] |
{ |
INITIALIZE = 4'b0001, |
ACTIVE = 4'b0010, |
// READY = 4'b0100, |
FLUSH = 4'b1000 |
} state, next_state; |
|
// -------------------------------------------------------------------- |
always_ff @(posedge aclk) |
if(~aresetn) |
state <= INITIALIZE; |
else |
state <= next_state; |
|
// -------------------------------------------------------------------- |
always_comb |
case(state) |
INITIALIZE: if(all_initialized) |
next_state = ACTIVE; |
else |
next_state = INITIALIZE; |
|
ACTIVE: if(eof_leading) |
next_state = FLUSH; |
else |
next_state = ACTIVE; |
|
FLUSH: if(eof_trailing) |
next_state = INITIALIZE; |
else |
next_state = FLUSH; |
|
default: next_state = INITIALIZE; |
endcase |
|
// -------------------------------------------------------------------- |
assign enable = (state == ACTIVE); |
|
// -------------------------------------------------------------------- |
wire init = ((state == INITIALIZE) & (next_state == INITIALIZE)); |
wire flush = ((state == FLUSH) & (next_state == FLUSH)); |
axis_if #(.N(N), .U(U)) merge_in[L](.*); |
|
generate |
for(genvar j = 0; j < L; j++) |
begin: merge_gen |
axis_alias row_i(row_out[j][0], merge_in[j]); |
end |
endgenerate |
|
avf_line_buffer_merge #(N, U, L) merge_i(.*); |
|
// -------------------------------------------------------------------- |
endmodule |
|
|
/video/src/avf_line_buffer_merge.sv
0,0 → 1,103
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2019 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
avf_line_buffer_merge #(N, U, L) |
( |
axis_if merge_in[L], |
axis_if axis_out, |
input [L-2:0] initialized, |
input init, |
input flush, |
input enable, |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
localparam W = (N*8) + U + 1; // tdata + tuser + tlast |
|
// -------------------------------------------------------------------- |
wire int_done[L]; |
assign int_done[0] = ~init; |
|
generate |
for(genvar j = 1; j < L; j++) |
begin: trailing_gen |
assign int_done[j] = initialized[j-1]; |
end |
endgenerate |
|
// -------------------------------------------------------------------- |
wire [L-1:0] wr_full; |
wire wr_en[L]; |
wire [L-1:0] rd_empty; |
wire [W-1:0] rd_data[L]; |
wire rd_en = axis_out.tready & axis_out.tvalid; |
wire [L-1:0] valid; |
wire all_valid = &valid; |
wire all_not_full = ~(|wr_full); |
wire all_not_empty = ~(|rd_empty); |
wire tlast[L]; |
wire [U-1:0] tuser[L]; |
wire [(N*8)-1:0] tdata[L]; |
|
generate |
for(genvar j = 0; j < L; j++) |
begin: row_gen |
tiny_sync_fifo #(W) |
tiny_sync_fifo_i |
( |
.wr_full(wr_full[j]), |
.wr_data({merge_in[j].tlast, merge_in[j].tuser, merge_in[j].tdata}), |
.wr_en(wr_en[j]), |
.rd_empty(rd_empty[j]), |
.rd_data(rd_data[j]), |
// .rd_en(rd_en[j]), |
.rd_en(rd_en), |
.clk(aclk), |
.reset(~aresetn), |
.* |
); |
|
assign wr_en[j] = ~init & ~flush & merge_in[j].tready & merge_in[j].tvalid; |
// assign merge_in[j].tready = flush | (init & ~int_done[j]) | (all_valid & all_not_full); // fixme |
assign merge_in[j].tready = (init & ~int_done[j]) | (all_valid & all_not_full); |
assign valid[j] = merge_in[j].tvalid; |
assign {tlast[j], tuser[j], tdata[j]} = rd_data[j]; |
end |
endgenerate |
|
// -------------------------------------------------------------------- |
assign axis_out.tvalid = all_not_empty; |
assign axis_out.tdata = {tdata[2], tdata[1], tdata[0]}; |
assign axis_out.tlast = tlast[0]; |
assign axis_out.tuser[1:0] = tuser[0][1:0]; |
assign axis_out.tuser[2] = tuser[0][2]; |
|
// -------------------------------------------------------------------- |
endmodule |
/video/src/avf_line_buffer_row.sv
0,0 → 1,144
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2019 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
avf_line_buffer_row #(N, W, AW, EOL_TO_PASS) |
( |
axis_if axis_in, |
axis_if axis_out, |
input enable, |
output zero_pad, |
output initialized, |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
wire in_eol = axis_in.tlast & axis_in.tready & axis_in.tvalid; |
wire in_eof = axis_in.tuser[2] & axis_in.tready & axis_in.tvalid; |
wire primed; |
|
// -------------------------------------------------------------------- |
generate |
begin: counter_gen |
if(EOL_TO_PASS == 0) |
begin: first_line_gen // don't let any EOL pass through. |
// ---------------- // The trailing FIFO is primed by the first line. |
assign primed = in_eol; |
end |
else |
begin: remainder_lines_gen |
// -------------------------------------------------------------------- |
reg [$clog2(EOL_TO_PASS)-1:0] eol_count; |
assign primed = (eol_count == EOL_TO_PASS) & in_eol; |
|
always_ff @(posedge aclk) |
if(~aresetn | primed) |
eol_count <= 0; |
else if(in_eol) |
eol_count <= eol_count + 1; |
end |
end |
endgenerate |
|
// -------------------------------------------------------------------- |
localparam UB = $clog2(AW*2); |
localparam D = 2**UB; |
|
// -------------------------------------------------------------------- |
wire [UB:0] count; |
wire wr_full; |
wire rd_empty; |
wire [W-1:0] wr_data = {axis_in.tlast, axis_in.tuser, axis_in.tdata}; |
wire wr_en = axis_in.tready & axis_in.tvalid; |
wire rd_en = axis_out.tready & axis_out.tvalid; |
wire [W-1:0] rd_data; |
assign {axis_out.tlast, axis_out.tuser, axis_out.tdata} = rd_data; |
|
sync_fifo #(W, D) fifo_i(.clk(aclk), .reset(~aresetn), .*); |
|
// -------------------------------------------------------------------- |
enum reg [3:0] |
{ |
PRIME = 4'b0001, |
INITIALIZED = 4'b0010, |
READY = 4'b0100, |
FLUSH = 4'b1000 |
} state, next_state; |
|
// -------------------------------------------------------------------- |
always_ff @(posedge aclk) |
if(~aresetn) |
state <= PRIME; |
else |
state <= next_state; |
|
// -------------------------------------------------------------------- |
always_comb |
case(state) |
PRIME: if(primed) |
next_state = INITIALIZED; |
else |
next_state = PRIME; |
|
INITIALIZED: if(enable) |
next_state = READY; |
else |
next_state = INITIALIZED; |
|
READY: if(in_eof) |
next_state = FLUSH; |
else |
next_state = READY; |
|
FLUSH: if(rd_empty) |
next_state = PRIME; |
else |
next_state = FLUSH; |
|
default: next_state = PRIME; |
endcase |
|
// -------------------------------------------------------------------- |
generate |
if(EOL_TO_PASS == 0) // no pass through for trailing FIFO |
begin: first_line_gen |
assign axis_out.tvalid = ~rd_empty & ((state == READY) | (state == FLUSH)); |
end |
else |
begin: remainder_lines_gen |
assign axis_out.tvalid = ~rd_empty & ((state == PRIME) | (state == READY) | (state == FLUSH)); |
end |
endgenerate |
|
// -------------------------------------------------------------------- |
assign axis_in.tready = ~wr_full & ((state == PRIME) | (state == READY)); |
assign zero_pad = (state == PRIME) | (state == INITIALIZED); |
assign initialized = (state == INITIALIZED); |
|
// -------------------------------------------------------------------- |
endmodule |
/video/src/fifo_to_avf.sv
0,0 → 1,151
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2019 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
fifo_to_avf #(AW, AH, D, B=2, T=1, N=B*T) |
( |
input [(N*8)-1:0] tdata, |
input wr_en, |
output wr_full, |
output sof, |
output sol, |
output eol, |
output eof, |
output reg [$clog2(AW)-1:0] n, |
output reg [$clog2(AH)-1:0] m, |
wire error, |
axis_if axis_out, |
input aclk, |
input aresetn |
); |
// -------------------------------------------------------------------- |
// synthesis translate_off |
initial |
assert(AW % T == 0) else $fatal; |
// synthesis translate_on |
// -------------------------------------------------------------------- |
|
// -------------------------------------------------------------------- |
// / \ |
// | A_00 A_01 .... A_0n | |
// | A_10 A_11 .... A_1n | |
// | .... .... .... .... | |
// | A_m0 A_m1 .... A_mn | |
// \ / |
|
// -------------------------------------------------------------------- |
localparam U = 3; |
localparam W = (N*8) + U + 1; // tdata + tuser + tlast |
|
// -------------------------------------------------------------------- |
// tuser[0] = SOF; tuser[1] = SOL; tlast = EOL; tuser[2] = EOF; |
wire tlast = eol; |
wire [U-1:0] tuser = {eof, sol, sof}; |
wire [W-1:0] wr_data = {tlast, tuser, tdata}; |
wire rd_empty; |
wire [W-1:0] rd_data; |
wire rd_en; |
wire [$clog2(D):0] count; |
|
sync_fifo #(W, D) fifo_i(.clk(aclk), .reset(~aresetn), .*); |
|
// -------------------------------------------------------------------- |
wire almost_eol = (n == AW - (2*T)); |
|
always_ff @(posedge aclk) |
if(~aresetn | (wr_en & eol)) |
n <= 0; |
else if(wr_en) |
n <= n + T; |
|
// -------------------------------------------------------------------- |
wire last_pixel = (m == AH - 1); |
|
always_ff @(posedge aclk) |
if(~aresetn | (wr_en & eof)) |
m <= 0; |
else if(wr_en & eol) |
m <= m + 1; |
|
// -------------------------------------------------------------------- |
enum reg [2:0] |
{ |
SOF = 3'b001, |
LINE = 3'b010, |
EOL = 3'b100 |
} prior_state, state, next_state; |
|
// -------------------------------------------------------------------- |
always_ff @(posedge aclk) |
if(~aresetn) |
state <= SOF; |
else |
state <= next_state; |
|
// -------------------------------------------------------------------- |
always_ff @(posedge aclk) |
if(wr_en) |
prior_state <= state; |
|
// -------------------------------------------------------------------- |
always_comb |
case(state) |
SOF: if(wr_en) |
next_state <= LINE; |
else |
next_state <= SOF; |
|
LINE: if(wr_en & almost_eol) |
next_state <= EOL; |
else |
next_state <= LINE; |
|
EOL: if(wr_en) |
if(last_pixel) // EOF |
next_state <= SOF; |
else |
next_state <= LINE; |
else |
next_state <= EOL; |
|
default: next_state <= SOF; |
endcase |
|
// -------------------------------------------------------------------- |
assign error = (wr_en & wr_full); |
assign sof = (state == SOF); |
assign sol = (state == SOF) | ((state == LINE) & (prior_state == EOL)); |
assign eof = (state == EOL) & last_pixel; |
assign eol = (state == EOL); |
|
// -------------------------------------------------------------------- |
assign rd_en = axis_out.tvalid & axis_out.tready; |
assign axis_out.tvalid = ~rd_empty; |
assign {axis_out.tlast, axis_out.tuser[U-1:0], axis_out.tdata} = rd_data; |
|
// -------------------------------------------------------------------- |
endmodule |