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    /qaz_libs/trunk
    from Rev 50 to Rev 51
    Reverse comparison

Rev 50 → Rev 51

/axi4_stream_lib/src/axis_catenate.sv
25,7 → 25,6
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
axis_catenate
#(
41,9 → 40,7
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
//
wire select;
wire axis_eop;
 
53,18 → 50,13
// axis_eop_mux #(.U_IS_EOP(U_IS_EOP), .MA(1))
axis_eop_mux_i(.axis_in(axis_in), .*);
 
 
// --------------------------------------------------------------------
// state machine binary definitions
enum reg [1:0]
{
HEAD = 2'b01,
{ HEAD = 2'b01,
TAIL = 2'b10
} state, next_state;
 
 
// --------------------------------------------------------------------
// state machine flop
always_ff @(posedge aclk)
if(~aresetn)
state <= HEAD;
71,9 → 63,7
else
state <= next_state;
 
 
// --------------------------------------------------------------------
// state machine
always_comb
case(state)
HEAD: if(axis_eop)
89,58 → 79,42
default: next_state <= HEAD;
endcase
 
 
// --------------------------------------------------------------------
//
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_bus[1:0](.*);
genvar j;
 
generate
if(U_IS_EOP > -1)
begin: u_is_eop_gen
for(j = 0; j < U; j++)
begin: for_tuser_gen
if(j == U_IS_EOP)
begin: choped_tuser_gen
if(U_IS_EOP > -1) begin: u_is_eop_gen
for(j = 0; j < U; j++) begin: for_tuser_gen
if(j == U_IS_EOP) begin: choped_tuser_gen
assign axis_bus[0].tuser[j] = 0;
end
else
begin: tuser_gen
else begin: tuser_gen
assign axis_bus[0].tuser[j] = axis_in[0].tuser[j];
end
end
end
else
if(U_IS_EOP > -1)
begin: tlast_gen
else begin: u_not_eop_gen
assign axis_bus[0].tuser = axis_in[0].tuser;
end
 
if(U_IS_EOP > -1) begin: tlast_gen
assign axis_bus[0].tlast = axis_in[0].tlast;
end
else
begin: choped_tlast_gen
else begin: choped_tlast_gen
assign axis_bus[0].tlast = 0;
end
endgenerate
 
 
// --------------------------------------------------------------------
//
assign axis_in[0].tready = axis_bus[0].tready;
assign axis_bus[0].tvalid = axis_in[0].tvalid;
assign axis_bus[0].tdata = axis_in[0].tdata;
assign axis_bus[0].tstrb = axis_in[0].tstrb;
assign axis_bus[0].tkeep = axis_in[0].tkeep;
assign axis_bus[0].tid = axis_in[0].tid;
assign axis_bus[0].tdest = axis_in[0].tdest;
axis_alias #(.CONNECT_TLAST(0), .CONNECT_TUSER(0))
axis_alias(axis_in[0], axis_bus[0]);
 
 
// --------------------------------------------------------------------
//
axis_alias
axis_alias_i(axis_in[1], axis_bus[1]);
axis_alias_hi(axis_in[1], axis_bus[1]);
 
 
// --------------------------------------------------------------------
//
defparam axis_mux_i.N = N; // why are these needed for recursive modules?
defparam axis_mux_i.I = I;
defparam axis_mux_i.D = D;
149,13 → 123,8
// axis_mux #(.N(N), .I(I), .D(D), .U(U))
axis_mux_i(.axis_in(axis_bus), .*);
 
 
// --------------------------------------------------------------------
//
assign select = (state == HEAD) ? 0 : 1;
 
 
// --------------------------------------------------------------------
//
endmodule
 
/axi4_stream_lib/src/recursive_axis_catenate.sv
34,80 → 34,81
D = 1, // TDEST width
U = 1, // TUSER width
U_IS_EOP = -1,
MA, // mux select width
MD = 2 ** MA
MN // number of inputs to mux
)
(
axis_if axis_in [MD-1:0],
axis_if axis_out,
input aclk,
input aresetn
axis_if axis_in[MN-1:0],
axis_if axis_out,
input aclk,
input aresetn
);
// --------------------------------------------------------------------
// synthesis translate_off
initial begin
assert(MN > 0) else $fatal;
end
// synthesis translate_on
// --------------------------------------------------------------------
 
// --------------------------------------------------------------------
//
localparam MA = $clog2(MN); // mux select width
localparam MH = 2 ** (MA - 1); // half of ceil(number of inputs)
localparam MR = MN - MH; // upper remainder
 
// --------------------------------------------------------------------
generate
if(MA == 1)
begin: catenate_gen
if(MN == 1) begin : one
axis_alias axis_alias_i(axis_in[0], axis_out);
end
else if(MN == 2) begin : two
axis_catenate #(.N(N), .I(I), .D(D), .U(U), .U_IS_EOP(U_IS_EOP))
axis_catenate_i(.*);
end
else
begin: recursive_catenate_gen
// --------------------------------------------------------------------
//
else begin: recurse
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_catenate_out[1:0](.*);
 
recursive_axis_catenate
#(
.N(N),
.I(I),
.D(D),
.U(U),
.U_IS_EOP(U_IS_EOP),
.MA(MA - 1)
#( .N(N)
, .I(I)
, .D(D)
, .U(U)
, .U_IS_EOP(U_IS_EOP)
, .MN(MH)
)
catenate_lo
(
.axis_in(axis_in[(MD/2)-1:0]),
( .axis_in(axis_in[MH-1:0]),
.axis_out(axis_catenate_out[0]),
.*
);
.* );
 
// --------------------------------------------------------------------
//
recursive_axis_catenate
#(
.N(N),
.I(I),
.D(D),
.U(U),
.U_IS_EOP(U_IS_EOP),
.MA(MA - 1)
)
catenate_hi
(
.axis_in(axis_in[MD-1:(MD/2)]),
.axis_out(axis_catenate_out[1]),
.*
);
if(MR == 1) begin : one
axis_alias axis_alias_i(axis_in[MH], axis_catenate_out[1]);
end
else if(MR == 2) begin : two
axis_catenate #(.N(N), .I(I), .D(D), .U(U), .U_IS_EOP(U_IS_EOP))
axis_catenate_i
( .axis_in(axis_in[MH+1:MH]),
.axis_out(axis_catenate_out[1]),
.* );
end
else begin : more
recursive_axis_catenate
#( .N(N)
, .I(I)
, .D(D)
, .U(U)
, .U_IS_EOP(U_IS_EOP)
, .MN(MR)
)
catenate_hi
( .axis_in(axis_in[MN-1:MN-MR]),
.axis_out(axis_catenate_out[1]),
.* );
end
 
// --------------------------------------------------------------------
//
axis_catenate
#(
.N(N),
.I(I),
.D(D),
.U(U),
.U_IS_EOP(U_IS_EOP)
)
axis_catenate #(.N(N), .I(I), .D(D), .U(U), .U_IS_EOP(U_IS_EOP))
axis_catenate_i(.axis_in(axis_catenate_out), .*);
end
endgenerate
 
 
// --------------------------------------------------------------------
//
endmodule
 
/sim/libs/axi4_checker_verilog/axi4_checker.f
0,0 → 1,12
#
 
+incdir+${LIB_BASE_DIR}/axi4_lib/sim/src/BP065-BU-01000-r0p1-00rel0/sva
 
${LIB_BASE_DIR}/axi4_lib/sim/src/BP065-BU-01000-r0p1-00rel0/axi4_checker.sv
${LIB_BASE_DIR}/axi4_lib/sim/src/BP065-BU-01000-r0p1-00rel0/sva/Axi4PC_ace.sv
 
 
 
 
 
 
/sim/libs/axi4_checker_verilog/axis_checker.f
0,0 → 1,12
#
 
+incdir+${LIB_BASE_DIR}/axi4_stream_lib/sim/src/BP063-BU-01000-r0p1-00rel0/sva
 
${LIB_BASE_DIR}/axi4_stream_lib/sim/src/BP063-BU-01000-r0p1-00rel0/axis_checker.sv
${LIB_BASE_DIR}/axi4_stream_lib/sim/src/BP063-BU-01000-r0p1-00rel0/sva/Axi4StreamPC.sv
 
 
 
 
 
 
/sim/libs/axi4_lib_verilog/axi4_stream_base.f
14,3 → 14,5
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_catenate.sv
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_switch.sv
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_fanout.sv
 
${LIB_BASE_DIR}/axi4_stream_lib/src/recursive_axis_catenate.sv
/sim/libs/qaz_lib_verilog/basal.f
12,4 → 12,3
 
${LIB_BASE_DIR}/basal/src/synchronize/synchronizer.v
${LIB_BASE_DIR}/basal/src/synchronize/sync_reset.v
 

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