OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

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Rev 14 → Rev 15

/trunk/zed_board/block_diagrams/zync.tcl
0,0 → 1,198
 
################################################################
# This is a generated script based on design: zync
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
 
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2014.4
set current_vivado_version [version -short]
 
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."
 
return 1
}
 
################################################################
# START
################################################################
 
# To test this script, run the following commands from Vivado Tcl console:
# source zync_script.tcl
 
# If you do not already have a project created,
# you can create a project using the following command:
# create_project project_1 myproj -part xc7z020clg484-1
# set_property BOARD_PART em.avnet.com:zed:part0:1.2 [current_project]
 
 
# CHANGE DESIGN NAME HERE
set design_name zync
 
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
 
# CHECKING IF PROJECT EXISTS
if { [get_projects -quiet] eq "" } {
puts "ERROR: Please open or create a project!"
return 1
}
 
 
# Creating design if needed
set errMsg ""
set nRet 0
 
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
 
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
 
set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."
set nRet 1
 
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
 
if { $cur_design ne $design_name } {
puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
puts "INFO: Constructing design in IPI design <$cur_design>..."
 
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
 
set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
 
set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
 
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
 
puts "INFO: Currently there is no design <$design_name> in project, so creating one..."
 
create_bd_design $design_name
 
puts "INFO: Making design <$design_name> as current_bd_design."
current_bd_design $design_name
 
}
 
puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."
 
if { $nRet != 0 } {
puts $errMsg
return $nRet
}
 
##################################################################
# DESIGN PROCs
##################################################################
 
 
 
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
 
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
 
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
puts "ERROR: Unable to find parent cell <$parentCell>!"
return
}
 
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
return
}
 
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
 
# Set parent object as current
current_bd_instance $parentObj
 
 
# Create interface ports
set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.NUM_READ_OUTSTANDING {8} CONFIG.NUM_WRITE_OUTSTANDING {8} CONFIG.PROTOCOL {AXI4LITE} ] $M00_AXI
 
# Create ports
set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ]
set_property -dict [ list CONFIG.ASSOCIATED_BUSIF {M00_AXI} ] $FCLK_CLK0
set peripheral_aresetn [ create_bd_port -dir O -from 0 -to 0 -type rst peripheral_aresetn ]
 
# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_interconnect_0
 
# Create instance: proc_sys_reset_0, and set properties
set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
 
# Create instance: processing_system7_0, and set properties
set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
set_property -dict [ list CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} CONFIG.preset {ZedBoard*} ] $processing_system7_0
 
# Create interface connections
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
 
# Create port connections
connect_bd_net -net ARESETN_1 [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins proc_sys_reset_0/interconnect_aresetn]
connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_ports peripheral_aresetn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FCLK_CLK0] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N]
 
# Create address segments
create_bd_addr_seg -range 0x10000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M00_AXI/Reg] SEG_M00_AXI_Reg
 
# Restore current instance
current_bd_instance $oldCurInst
 
save_bd_design
}
# End of create_root_design()
 
 
##################################################################
# MAIN FLOW
##################################################################
 
create_root_design ""
 
 
/trunk/zed_board/src/top.v
0,0 → 1,564
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
module
top
(
inout [14:0]DDR_Addr,
inout [2:0]DDR_BankAddr,
inout DDR_CAS_n,
inout DDR_Clk,
inout DDR_Clk_n,
inout DDR_CKE,
inout DDR_CS_n,
inout [3:0]DDR_DM,
inout [31:0]DDR_DQ,
inout [3:0]DDR_DQS,
inout [3:0]DDR_DQS_n,
inout DDR_ODT,
inout DDR_RAS_n,
inout DDR_DRSTB,
inout DDR_WEB,
inout DDR_VRN,
inout DDR_VRP,
inout [53:0]MIO,
inout PS_CLK,
inout PS_PORB,
inout PS_SRSTB,
 
input AC_ADR0, // Audio Codec - Bank 13
output AC_ADR1,
inout AC_GPIO0,
inout AC_GPIO1,
inout AC_GPIO2,
inout AC_GPIO3,
input AC_MCLK,
input AC_SCK,
inout AC_SDA,
 
input GCLK, // Clock Source - Bank 13
 
inout JA1, // JA Pmod - Bank 13
inout JA10,
inout JA2,
inout JA3,
inout JA4,
inout JA7,
inout JA8,
inout JA9,
 
inout JB1, // JB Pmod - Bank 13
inout JB10,
inout JB2,
inout JB3,
inout JB4,
inout JB7,
inout JB8,
inout JB9,
 
inout JC1_N, // JC Pmod - Bank 13
inout JC1_P,
inout JC2_N,
inout JC2_P,
inout JC3_N,
inout JC3_P,
inout JC4_N,
inout JC4_P,
 
inout JD1_N, // JA Pmod - Bank 13
inout JD1_P,
inout JD2_N,
inout JD2_P,
inout JD3_N,
inout JD3_P,
inout JD4_N,
inout JD4_P,
 
output OLED_DC, // OLED Display - Bank 13
output OLED_RES,
output OLED_SCLK,
output OLED_SDIN,
output OLED_VBAT,
output OLED_VDD,
 
output HD_CLK, // HDMI Output - Bank 33
output HD_D0,
output HD_D1,
output HD_D10,
output HD_D11,
output HD_D12,
output HD_D13,
output HD_D14,
output HS_D15,
output HD_D2,
output HD_D3,
output HD_D4,
output HD_D5,
output HD_D6,
output HD_D7,
output HD_D8,
output HD_D9,
output HD_DE,
output HD_HSYNC,
output HD_INT,
output HD_SCL,
inout HD_SDA,
output HD_SPDIF,
input HD_SPDIFO,
output HD_VSYNC,
 
output LD0, // User LEDs - Bank 33
output LD1,
output LD2,
output LD3,
output LD4,
output LD5,
output LD6,
output LD7,
 
output VGA_B1, // VGA Output - Bank 33
output VGA_B2,
output VGA_B3,
output VGA_B4,
output VGA_G1,
output VGA_G2,
output VGA_G3,
output VGA_G4,
output VGA_HS,
output VGA_R1,
output VGA_R2,
output VGA_R3,
output VGA_R4,
output VGA_VS,
 
input BTNC, // User Push Buttons - Bank 34
input BTND,
input BTNL,
input BTNR,
input BTNU,
 
input OTG_VBUSOC, // USB OTG Reset - Bank 34
 
// inout XADC_GIO0, // XADC GIO - Bank 34
// inout XADC_GIO1,
// inout XADC_GIO2,
// inout XADC_GIO3,
 
inout PUDC_B, // Miscellaneous - Bank 34
 
output OTG_RESETN, // USB OTG Reset - Bank 35
 
input SW0, // User DIP Switches - Bank 35
input SW1,
input SW2,
input SW3,
input SW4,
input SW5,
input SW6,
input SW7,
 
// input AD0N_R, // XADC AD Channels - Bank 35
// input AD0P_R,
// input AD8N_N,
// input AD8P_R,
 
output FMC_SCL, // FMC Expansion Connector - Bank 13
inout FMC_SDA,
 
inout FMC_PRSNT, // FMC Expansion Connector - Bank 33
 
input FMC_CLK0_N, // FMC Expansion Connector - Bank 34
input FMC_CLK0_P,
input FMC_LA00_CC_N,
input FMC_LA00_CC_P,
input FMC_LA01_CC_N,
input FMC_LA01_CC_P,
inout FMC_LA02_N,
inout FMC_LA02_P,
inout FMC_LA03_N,
inout FMC_LA03_P,
inout FMC_LA04_N,
inout FMC_LA04_P,
inout FMC_LA05_N,
inout FMC_LA05_P,
inout FMC_LA06_N,
inout FMC_LA06_P,
inout FMC_LA07_N,
inout FMC_LA07_P,
inout FMC_LA08_N,
inout FMC_LA08_P,
inout FMC_LA09_N,
inout FMC_LA09_P,
inout FMC_LA10_N,
inout FMC_LA10_P,
inout FMC_LA11_N,
inout FMC_LA11_P,
inout FMC_LA12_N,
inout FMC_LA12_P,
inout FMC_LA13_N,
inout FMC_LA13_P,
inout FMC_LA14_N,
inout FMC_LA14_P,
inout FMC_LA15_N,
inout FMC_LA15_P,
inout FMC_LA16_N,
inout FMC_LA16_P,
 
input FMC_CLK1_N, // FMC Expansion Connector - Bank 35
input FMC_CLK1_P,
input FMC_LA17_CC_N,
input FMC_LA17_CC_P,
input FMC_LA18_CC_N,
input FMC_LA18_CC_P,
inout FMC_LA19_N,
inout FMC_LA19_P,
inout FMC_LA20_N,
inout FMC_LA20_P,
inout FMC_LA21_N,
inout FMC_LA21_P,
inout FMC_LA22_N,
inout FMC_LA22_P,
inout FMC_LA23_N,
inout FMC_LA23_P,
inout FMC_LA24_N,
inout FMC_LA24_P,
inout FMC_LA25_N,
inout FMC_LA25_P,
inout FMC_LA26_N,
inout FMC_LA26_P,
inout FMC_LA27_N,
inout FMC_LA27_P,
inout FMC_LA28_N,
inout FMC_LA28_P,
inout FMC_LA29_N,
inout FMC_LA29_P,
inout FMC_LA30_N,
inout FMC_LA30_P,
inout FMC_LA31_N,
inout FMC_LA31_P,
inout FMC_LA32_N,
inout FMC_LA32_P,
inout FMC_LA33_N,
inout FMC_LA33_P
);
 
// --------------------------------------------------------------------
//
// (* KEEP = "TRUE" *) wire [31:0] M00_AXI_araddr;
// (* KEEP = "TRUE" *) wire [2:0] M00_AXI_arprot;
// (* KEEP = "TRUE" *) wire M00_AXI_arready;
// (* KEEP = "TRUE" *) wire M00_AXI_arvalid;
// (* KEEP = "TRUE" *) wire [31:0] M00_AXI_awaddr;
// (* KEEP = "TRUE" *) wire [2:0] M00_AXI_awprot;
// (* KEEP = "TRUE" *) wire M00_AXI_awready;
// (* KEEP = "TRUE" *) wire M00_AXI_awvalid;
// (* KEEP = "TRUE" *) wire M00_AXI_bready;
// (* KEEP = "TRUE" *) wire [1:0] M00_AXI_bresp;
// (* KEEP = "TRUE" *) wire M00_AXI_bvalid;
// (* KEEP = "TRUE" *) wire [31:0] M00_AXI_rdata;
// (* KEEP = "TRUE" *) wire M00_AXI_rready;
// (* KEEP = "TRUE" *) wire [1:0] M00_AXI_rresp;
// (* KEEP = "TRUE" *) wire M00_AXI_rvalid;
// (* KEEP = "TRUE" *) wire [31:0] M00_AXI_wdata;
// (* KEEP = "TRUE" *) wire M00_AXI_wready;
// (* KEEP = "TRUE" *) wire [3:0] M00_AXI_wstrb;
// (* KEEP = "TRUE" *) wire M00_AXI_wvalid;
 
wire [31:0] M00_AXI_araddr;
wire [2:0] M00_AXI_arprot;
wire M00_AXI_arready;
wire M00_AXI_arvalid;
wire [31:0] M00_AXI_awaddr;
wire [2:0] M00_AXI_awprot;
wire M00_AXI_awready;
wire M00_AXI_awvalid;
wire M00_AXI_bready;
wire [1:0] M00_AXI_bresp;
wire M00_AXI_bvalid;
wire [31:0] M00_AXI_rdata;
wire M00_AXI_rready;
wire [1:0] M00_AXI_rresp;
wire M00_AXI_rvalid;
wire [31:0] M00_AXI_wdata;
wire M00_AXI_wready;
wire [3:0] M00_AXI_wstrb;
wire M00_AXI_wvalid;
 
wire FCLK_CLK0;
 
zync
zync_i
(
.DDR_addr(DDR_Addr),
.DDR_ba(DDR_BankAddr),
.DDR_cas_n(DDR_CAS_n),
.DDR_ck_n(DDR_Clk_n),
.DDR_ck_p(DDR_Clk),
.DDR_cke(DDR_CKE),
.DDR_cs_n(DDR_CS_n),
.DDR_dm(DDR_DM),
.DDR_dq(DDR_DQ),
.DDR_dqs_n(DDR_DQS_n),
.DDR_dqs_p(DDR_DQS),
.DDR_odt(DDR_ODT),
.DDR_ras_n(DDR_RAS_n),
.DDR_reset_n(DDR_DRSTB),
.DDR_we_n(DDR_WEB),
.FIXED_IO_ddr_vrn(DDR_VRN),
.FIXED_IO_ddr_vrp(DDR_VRP),
.FIXED_IO_mio(MIO),
.FIXED_IO_ps_clk(PS_CLK),
.FIXED_IO_ps_porb(PS_PORB),
.FIXED_IO_ps_srstb(PS_SRSTB),
.FCLK_CLK0(FCLK_CLK0),
.M00_AXI_araddr(M00_AXI_araddr),
.M00_AXI_arprot(M00_AXI_arprot),
.M00_AXI_arready(M00_AXI_arready),
.M00_AXI_arvalid(M00_AXI_arvalid),
.M00_AXI_awaddr(M00_AXI_awaddr),
.M00_AXI_awprot(M00_AXI_awprot),
.M00_AXI_awready(M00_AXI_awready),
.M00_AXI_awvalid(M00_AXI_awvalid),
.M00_AXI_bready(M00_AXI_bready),
.M00_AXI_bresp(M00_AXI_bresp),
.M00_AXI_bvalid(M00_AXI_bvalid),
.M00_AXI_rdata(M00_AXI_rdata),
.M00_AXI_rready(M00_AXI_rready),
.M00_AXI_rresp(M00_AXI_rresp),
.M00_AXI_rvalid(M00_AXI_rvalid),
.M00_AXI_wdata(M00_AXI_wdata),
.M00_AXI_wready(M00_AXI_wready),
.M00_AXI_wstrb(M00_AXI_wstrb),
.M00_AXI_wvalid(M00_AXI_wvalid),
.peripheral_aresetn(peripheral_aresetn)
);
 
 
// --------------------------------------------------------------------
//
wire [31:0] slv_reg0;
wire [31:0] slv_reg1;
wire [31:0] slv_reg2;
wire [31:0] slv_reg3;
 
reg_file_v1_0_S00_AXI
#(
.C_S_AXI_DATA_WIDTH(32),
.C_S_AXI_ADDR_WIDTH(4)
)
reg_file_v1_0_S00_AXI_inst
(
.S_AXI_ACLK(FCLK_CLK0),
.S_AXI_ARESETN(peripheral_aresetn),
.S_AXI_AWADDR(M00_AXI_awaddr[3:0]),
.S_AXI_AWPROT(M00_AXI_awprot),
.S_AXI_AWVALID(M00_AXI_awvalid),
.S_AXI_AWREADY(M00_AXI_awready),
.S_AXI_WDATA(M00_AXI_wdata),
.S_AXI_WSTRB(M00_AXI_wstrb),
.S_AXI_WVALID(M00_AXI_wvalid),
.S_AXI_WREADY(M00_AXI_wready),
.S_AXI_BRESP(M00_AXI_bresp),
.S_AXI_BVALID(M00_AXI_bvalid),
.S_AXI_BREADY(M00_AXI_bready),
.S_AXI_ARADDR(M00_AXI_araddr[3:0]),
.S_AXI_ARPROT(M00_AXI_arprot),
.S_AXI_ARVALID(M00_AXI_arvalid),
.S_AXI_ARREADY(M00_AXI_arready),
.S_AXI_RDATA(M00_AXI_rdata),
.S_AXI_RRESP(M00_AXI_rresp),
.S_AXI_RVALID(M00_AXI_rvalid),
.S_AXI_RREADY(M00_AXI_rready),
 
.slv_reg0(slv_reg0),
.slv_reg1(slv_reg1),
.slv_reg2(slv_reg2),
.slv_reg3(slv_reg3)
 
);
 
 
// --------------------------------------------------------------------
// outputs
assign LD0 = slv_reg0[0];
assign LD1 = slv_reg0[1];
assign LD2 = slv_reg0[2];
assign LD3 = slv_reg0[3];
assign LD4 = slv_reg0[4];
assign LD5 = slv_reg0[5];
assign LD6 = slv_reg0[6];
assign LD7 = slv_reg0[7];
 
assign AC_ADR1 = 0;
assign AC_GPIO0 = 'bz;
assign AC_GPIO1 = 'bz;
assign AC_GPIO2 = 'bz;
assign AC_GPIO3 = 'bz;
assign AC_SDA = 'bz;
 
assign JA1 = 'bz; // JA Pmod - Bank 13
assign JA10 = 'bz;
assign JA2 = 'bz;
assign JA3 = 'bz;
assign JA4 = 'bz;
assign JA7 = 'bz;
assign JA8 = 'bz;
assign JA9 = 'bz;
 
assign JB1 = 'bz; // JB Pmod - Bank 13
assign JB10 = 'bz;
assign JB2 = 'bz;
assign JB3 = 'bz;
assign JB4 = 'bz;
assign JB7 = 'bz;
assign JB8 = 'bz;
assign JB9 = 'bz;
 
assign JC1_N = 'bz; // JC Pmod - Bank 13
assign JC1_P = 'bz;
assign JC2_N = 'bz;
assign JC2_P = 'bz;
assign JC3_N = 'bz;
assign JC3_P = 'bz;
assign JC4_N = 'bz;
assign JC4_P = 'bz;
 
assign JD1_N = 'bz; // JA Pmod - Bank 13
assign JD1_P = 'bz;
assign JD2_N = 'bz;
assign JD2_P = 'bz;
assign JD3_N = 'bz;
assign JD3_P = 'bz;
assign JD4_N = 'bz;
assign JD4_P = 'bz;
 
assign OLED_DC = 0; // OLED Display - Bank 13
assign OLED_RES = 0;
assign OLED_SCLK = 0;
assign OLED_SDIN = 0;
assign OLED_VBAT = 0;
assign OLED_VDD = 0;
 
assign HD_CLK = 0; // HDMI assign - = 0;Bank 33
assign HD_D0 = 0;
assign HD_D1 = 0;
assign HD_D10 = 0;
assign HD_D11 = 0;
assign HD_D12 = 0;
assign HD_D13 = 0;
assign HD_D14 = 0;
assign HS_D15 = 0;
assign HD_D2 = 0;
assign HD_D3 = 0;
assign HD_D4 = 0;
assign HD_D5 = 0;
assign HD_D6 = 0;
assign HD_D7 = 0;
assign HD_D8 = 0;
assign HD_D9 = 0;
assign HD_DE = 0;
assign HD_HSYNC = 0;
assign HD_INT = 0;
assign HD_SCL = 0;
assign HD_SDA = 'bz;
assign HD_SPDIF = 0;
assign HD_VSYNC = 0;
 
assign VGA_B1 = 0; // VGA assign - = 0;Bank 33
assign VGA_B2 = 0;
assign VGA_B3 = 0;
assign VGA_B4 = 0;
assign VGA_G1 = 0;
assign VGA_G2 = 0;
assign VGA_G3 = 0;
assign VGA_G4 = 0;
assign VGA_HS = 0;
assign VGA_R1 = 0;
assign VGA_R2 = 0;
assign VGA_R3 = 0;
assign VGA_R4 = 0;
assign VGA_VS = 0;
 
// assign XADC_GIO0 = 'bz; // XADC GIO - Bank 34
// assign XADC_GIO1 = 'bz;
// assign XADC_GIO2 = 'bz;
// assign XADC_GIO3 = 'bz;
 
assign PUDC_B = 'bz; // Miscellaneous - Bank 34
 
assign OTG_RESETN = 0; // USB OTG Reset - Bank 35
 
assign FMC_SCL = 0; // FMC Expansion Connector - Bank 13
assign FMC_SDA = 'bz;
 
assign FMC_PRSNT = 'bz; // FMC Expansion Connector - Bank 33
 
assign FMC_LA02_N = 'bz;
assign FMC_LA02_P = 'bz;
assign FMC_LA03_N = 'bz;
assign FMC_LA03_P = 'bz;
assign FMC_LA04_N = 'bz;
assign FMC_LA04_P = 'bz;
assign FMC_LA05_N = 'bz;
assign FMC_LA05_P = 'bz;
assign FMC_LA06_N = 'bz;
assign FMC_LA06_P = 'bz;
assign FMC_LA07_N = 'bz;
assign FMC_LA07_P = 'bz;
assign FMC_LA08_N = 'bz;
assign FMC_LA08_P = 'bz;
assign FMC_LA09_N = 'bz;
assign FMC_LA09_P = 'bz;
assign FMC_LA10_N = 'bz;
assign FMC_LA10_P = 'bz;
assign FMC_LA11_N = 'bz;
assign FMC_LA11_P = 'bz;
assign FMC_LA12_N = 'bz;
assign FMC_LA12_P = 'bz;
assign FMC_LA13_N = 'bz;
assign FMC_LA13_P = 'bz;
assign FMC_LA14_N = 'bz;
assign FMC_LA14_P = 'bz;
assign FMC_LA15_N = 'bz;
assign FMC_LA15_P = 'bz;
assign FMC_LA16_N = 'bz;
assign FMC_LA16_P = 'bz;
 
assign FMC_LA19_N = 'bz;
assign FMC_LA19_P = 'bz;
assign FMC_LA20_N = 'bz;
assign FMC_LA20_P = 'bz;
assign FMC_LA21_N = 'bz;
assign FMC_LA21_P = 'bz;
assign FMC_LA22_N = 'bz;
assign FMC_LA22_P = 'bz;
assign FMC_LA23_N = 'bz;
assign FMC_LA23_P = 'bz;
assign FMC_LA24_N = 'bz;
assign FMC_LA24_P = 'bz;
assign FMC_LA25_N = 'bz;
assign FMC_LA25_P = 'bz;
assign FMC_LA26_N = 'bz;
assign FMC_LA26_P = 'bz;
assign FMC_LA27_N = 'bz;
assign FMC_LA27_P = 'bz;
assign FMC_LA28_N = 'bz;
assign FMC_LA28_P = 'bz;
assign FMC_LA29_N = 'bz;
assign FMC_LA29_P = 'bz;
assign FMC_LA30_N = 'bz;
assign FMC_LA30_P = 'bz;
assign FMC_LA31_N = 'bz;
assign FMC_LA31_P = 'bz;
assign FMC_LA32_N = 'bz;
assign FMC_LA32_P = 'bz;
assign FMC_LA33_N = 'bz;
assign FMC_LA33_P = 'bz;
 
 
endmodule
 
 
 
/trunk/zed_board/src/reg_file_v1_0_S00_AXI.v
0,0 → 1,402
 
`timescale 1 ns / 1 ps
 
module reg_file_v1_0_S00_AXI #
(
// Users to add parameters here
 
// User parameters ends
// Do not modify the parameters beyond this line
 
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
 
// User ports ends
// Do not modify the ports beyond this line
 
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY,
output reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0,
output reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1,
output reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2,
output reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3
);
 
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
 
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 1;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 4
// reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
// reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
// reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
// reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
 
// I/O Connections assignments
 
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
 
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
 
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
 
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
 
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
 
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
 
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
 
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h1:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h2:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h3:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end
endcase
end
end
end
 
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
 
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
 
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
 
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
 
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
 
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0 : reg_data_out <= slv_reg0;
2'h1 : reg_data_out <= slv_reg1;
2'h2 : reg_data_out <= slv_reg2;
2'h3 : reg_data_out <= slv_reg3;
default : reg_data_out <= 0;
endcase
end
 
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
 
// Add user logic here
 
// User logic ends
 
endmodule
/trunk/zed_board/src/zedboard_master_XDC_RevC_D_v2.xdc
0,0 → 1,378
# ----------------------------------------------------------------------------
# _____
# / \
# /____ \____
# / \===\ \==/
# /___\===\___\/ AVNET Design Resource Center
# \======/ www.em.avnet.com/drc
# \====/
# ----------------------------------------------------------------------------
#
# Created With Avnet UCF Generator V0.4.0
# Date: Saturday, June 30, 2012
# Time: 12:18:55 AM
#
# This design is the property of Avnet. Publication of this
# design is not authorized without written consent from Avnet.
#
# Please direct any questions to:
# ZedBoard.org Community Forums
# http://www.zedboard.org
#
# Disclaimer:
# Avnet, Inc. makes no warranty for the use of this code or design.
# This code is provided "As Is". Avnet, Inc assumes no responsibility for
# any errors, which may appear in this code, nor does it make a commitment
# to update the information contained herein. Avnet, Inc specifically
# disclaims any implied warranties of fitness for a particular purpose.
# Copyright(c) 2012 Avnet, Inc.
# All rights reserved.
#
# ----------------------------------------------------------------------------
#
# Notes:
#
# 10 August 2012
# IO standards based upon Bank 34 and Bank 35 Vcco supply options of 1.8V,
# 2.5V, or 3.3V are possible based upon the Vadj jumper (J18) settings.
# By default, Vadj is expected to be set to 1.8V but if a different
# voltage is used for a particular design, then the corresponding IO
# standard within this UCF should also be updated to reflect the actual
# Vadj jumper selection.
#
# 09 September 2012
# Net names are not allowed to contain hyphen characters '-' since this
# is not a legal VHDL87 or Verilog character within an identifier.
# HDL net names are adjusted to contain no hyphen characters '-' but
# rather use underscore '_' characters. Comment net name with the hyphen
# characters will remain in place since these are intended to match the
# schematic net names in order to better enable schematic search.
#
# 17 April 2014
# Pin constraint for toggle switch SW7 was corrected to M15 location.
#
# 16 April 2015
# Corrected the way that entire banks are assigned to a particular IO
# standard so that it works with more recent versions of Vivado Design
# Suite and moved the IO standard constraints to the end of the file
# along with some better organization and notes like we do with our SOMs.
#
# ----------------------------------------------------------------------------
 
# ----------------------------------------------------------------------------
# Audio Codec - Bank 13
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN AB1 [get_ports {AC_ADR0}]; # "AC-ADR0"
set_property PACKAGE_PIN Y5 [get_ports {AC_ADR1}]; # "AC-ADR1"
set_property PACKAGE_PIN Y8 [get_ports {AC_GPIO0}]; # "AC-GPIO0"
set_property PACKAGE_PIN AA7 [get_ports {AC_GPIO1}]; # "AC-GPIO1"
set_property PACKAGE_PIN AA6 [get_ports {AC_GPIO2}]; # "AC-GPIO2"
set_property PACKAGE_PIN Y6 [get_ports {AC_GPIO3}]; # "AC-GPIO3"
set_property PACKAGE_PIN AB2 [get_ports {AC_MCLK}]; # "AC-MCLK"
set_property PACKAGE_PIN AB4 [get_ports {AC_SCK}]; # "AC-SCK"
set_property PACKAGE_PIN AB5 [get_ports {AC_SDA}]; # "AC-SDA"
 
# ----------------------------------------------------------------------------
# Clock Source - Bank 13
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN Y9 [get_ports {GCLK}]; # "GCLK"
 
# ----------------------------------------------------------------------------
# JA Pmod - Bank 13
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN Y11 [get_ports {JA1}]; # "JA1"
set_property PACKAGE_PIN AA8 [get_ports {JA10}]; # "JA10"
set_property PACKAGE_PIN AA11 [get_ports {JA2}]; # "JA2"
set_property PACKAGE_PIN Y10 [get_ports {JA3}]; # "JA3"
set_property PACKAGE_PIN AA9 [get_ports {JA4}]; # "JA4"
set_property PACKAGE_PIN AB11 [get_ports {JA7}]; # "JA7"
set_property PACKAGE_PIN AB10 [get_ports {JA8}]; # "JA8"
set_property PACKAGE_PIN AB9 [get_ports {JA9}]; # "JA9"
 
 
# ----------------------------------------------------------------------------
# JB Pmod - Bank 13
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN W12 [get_ports {JB1}]; # "JB1"
set_property PACKAGE_PIN V8 [get_ports {JB10}]; # "JB10"
set_property PACKAGE_PIN W11 [get_ports {JB2}]; # "JB2"
set_property PACKAGE_PIN V10 [get_ports {JB3}]; # "JB3"
set_property PACKAGE_PIN W8 [get_ports {JB4}]; # "JB4"
set_property PACKAGE_PIN V12 [get_ports {JB7}]; # "JB7"
set_property PACKAGE_PIN W10 [get_ports {JB8}]; # "JB8"
set_property PACKAGE_PIN V9 [get_ports {JB9}]; # "JB9"
 
# ----------------------------------------------------------------------------
# JC Pmod - Bank 13
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN AB6 [get_ports {JC1_N}]; # "JC1_N"
set_property PACKAGE_PIN AB7 [get_ports {JC1_P}]; # "JC1_P"
set_property PACKAGE_PIN AA4 [get_ports {JC2_N}]; # "JC2_N"
set_property PACKAGE_PIN Y4 [get_ports {JC2_P}]; # "JC2_P"
set_property PACKAGE_PIN T6 [get_ports {JC3_N}]; # "JC3_N"
set_property PACKAGE_PIN R6 [get_ports {JC3_P}]; # "JC3_P"
set_property PACKAGE_PIN U4 [get_ports {JC4_N}]; # "JC4_N"
set_property PACKAGE_PIN T4 [get_ports {JC4_P}]; # "JC4_P"
 
# ----------------------------------------------------------------------------
# JA Pmod - Bank 13
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN W7 [get_ports {JD1_N}]; # "JD1_N"
set_property PACKAGE_PIN V7 [get_ports {JD1_P}]; # "JD1_P"
set_property PACKAGE_PIN V4 [get_ports {JD2_N}]; # "JD2_N"
set_property PACKAGE_PIN V5 [get_ports {JD2_P}]; # "JD2_P"
set_property PACKAGE_PIN W5 [get_ports {JD3_N}]; # "JD3_N"
set_property PACKAGE_PIN W6 [get_ports {JD3_P}]; # "JD3_P"
set_property PACKAGE_PIN U5 [get_ports {JD4_N}]; # "JD4_N"
set_property PACKAGE_PIN U6 [get_ports {JD4_P}]; # "JD4_P"
 
# ----------------------------------------------------------------------------
# OLED Display - Bank 13
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN U10 [get_ports {OLED_DC}]; # "OLED-DC"
set_property PACKAGE_PIN U9 [get_ports {OLED_RES}]; # "OLED-RES"
set_property PACKAGE_PIN AB12 [get_ports {OLED_SCLK}]; # "OLED-SCLK"
set_property PACKAGE_PIN AA12 [get_ports {OLED_SDIN}]; # "OLED-SDIN"
set_property PACKAGE_PIN U11 [get_ports {OLED_VBAT}]; # "OLED-VBAT"
set_property PACKAGE_PIN U12 [get_ports {OLED_VDD}]; # "OLED-VDD"
 
# ----------------------------------------------------------------------------
# HDMI Output - Bank 33
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN W18 [get_ports {HD_CLK}]; # "HD-CLK"
set_property PACKAGE_PIN Y13 [get_ports {HD_D0}]; # "HD-D0"
set_property PACKAGE_PIN AA13 [get_ports {HD_D1}]; # "HD-D1"
set_property PACKAGE_PIN W13 [get_ports {HD_D10}]; # "HD-D10"
set_property PACKAGE_PIN W15 [get_ports {HD_D11}]; # "HD-D11"
set_property PACKAGE_PIN V15 [get_ports {HD_D12}]; # "HD-D12"
set_property PACKAGE_PIN U17 [get_ports {HD_D13}]; # "HD-D13"
set_property PACKAGE_PIN V14 [get_ports {HD_D14}]; # "HD-D14"
set_property PACKAGE_PIN V13 [get_ports {HS_D15}]; # "HD-D15"
set_property PACKAGE_PIN AA14 [get_ports {HD_D2}]; # "HD-D2"
set_property PACKAGE_PIN Y14 [get_ports {HD_D3}]; # "HD-D3"
set_property PACKAGE_PIN AB15 [get_ports {HD_D4}]; # "HD-D4"
set_property PACKAGE_PIN AB16 [get_ports {HD_D5}]; # "HD-D5"
set_property PACKAGE_PIN AA16 [get_ports {HD_D6}]; # "HD-D6"
set_property PACKAGE_PIN AB17 [get_ports {HD_D7}]; # "HD-D7"
set_property PACKAGE_PIN AA17 [get_ports {HD_D8}]; # "HD-D8"
set_property PACKAGE_PIN Y15 [get_ports {HD_D9}]; # "HD-D9"
set_property PACKAGE_PIN U16 [get_ports {HD_DE}]; # "HD-DE"
set_property PACKAGE_PIN V17 [get_ports {HD_HSYNC}]; # "HD-HSYNC"
set_property PACKAGE_PIN W16 [get_ports {HD_INT}]; # "HD-INT"
set_property PACKAGE_PIN AA18 [get_ports {HD_SCL}]; # "HD-SCL"
set_property PACKAGE_PIN Y16 [get_ports {HD_SDA}]; # "HD-SDA"
set_property PACKAGE_PIN U15 [get_ports {HD_SPDIF}]; # "HD-SPDIF"
set_property PACKAGE_PIN Y18 [get_ports {HD_SPDIFO}]; # "HD-SPDIFO"
set_property PACKAGE_PIN W17 [get_ports {HD_VSYNC}]; # "HD-VSYNC"
 
# ----------------------------------------------------------------------------
# User LEDs - Bank 33
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN T22 [get_ports {LD0}]; # "LD0"
set_property PACKAGE_PIN T21 [get_ports {LD1}]; # "LD1"
set_property PACKAGE_PIN U22 [get_ports {LD2}]; # "LD2"
set_property PACKAGE_PIN U21 [get_ports {LD3}]; # "LD3"
set_property PACKAGE_PIN V22 [get_ports {LD4}]; # "LD4"
set_property PACKAGE_PIN W22 [get_ports {LD5}]; # "LD5"
set_property PACKAGE_PIN U19 [get_ports {LD6}]; # "LD6"
set_property PACKAGE_PIN U14 [get_ports {LD7}]; # "LD7"
 
# ----------------------------------------------------------------------------
# VGA Output - Bank 33
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN Y21 [get_ports {VGA_B1}]; # "VGA-B1"
set_property PACKAGE_PIN Y20 [get_ports {VGA_B2}]; # "VGA-B2"
set_property PACKAGE_PIN AB20 [get_ports {VGA_B3}]; # "VGA-B3"
set_property PACKAGE_PIN AB19 [get_ports {VGA_B4}]; # "VGA-B4"
set_property PACKAGE_PIN AB22 [get_ports {VGA_G1}]; # "VGA-G1"
set_property PACKAGE_PIN AA22 [get_ports {VGA_G2}]; # "VGA-G2"
set_property PACKAGE_PIN AB21 [get_ports {VGA_G3}]; # "VGA-G3"
set_property PACKAGE_PIN AA21 [get_ports {VGA_G4}]; # "VGA-G4"
set_property PACKAGE_PIN AA19 [get_ports {VGA_HS}]; # "VGA-HS"
set_property PACKAGE_PIN V20 [get_ports {VGA_R1}]; # "VGA-R1"
set_property PACKAGE_PIN U20 [get_ports {VGA_R2}]; # "VGA-R2"
set_property PACKAGE_PIN V19 [get_ports {VGA_R3}]; # "VGA-R3"
set_property PACKAGE_PIN V18 [get_ports {VGA_R4}]; # "VGA-R4"
set_property PACKAGE_PIN Y19 [get_ports {VGA_VS}]; # "VGA-VS"
 
# ----------------------------------------------------------------------------
# User Push Buttons - Bank 34
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN P16 [get_ports {BTNC}]; # "BTNC"
set_property PACKAGE_PIN R16 [get_ports {BTND}]; # "BTND"
set_property PACKAGE_PIN N15 [get_ports {BTNL}]; # "BTNL"
set_property PACKAGE_PIN R18 [get_ports {BTNR}]; # "BTNR"
set_property PACKAGE_PIN T18 [get_ports {BTNU}]; # "BTNU"
 
# ----------------------------------------------------------------------------
# USB OTG Reset - Bank 34
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN L16 [get_ports {OTG_VBUSOC}]; # "OTG-VBUSOC"
 
# # ----------------------------------------------------------------------------
# # XADC GIO - Bank 34
# # ----------------------------------------------------------------------------
# set_property PACKAGE_PIN H15 [get_ports {XADC_GIO0}]; # "XADC-GIO0"
# set_property PACKAGE_PIN R15 [get_ports {XADC_GIO1}]; # "XADC-GIO1"
# set_property PACKAGE_PIN K15 [get_ports {XADC_GIO2}]; # "XADC-GIO2"
# set_property PACKAGE_PIN J15 [get_ports {XADC_GIO3}]; # "XADC-GIO3"
 
# ----------------------------------------------------------------------------
# Miscellaneous - Bank 34
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN K16 [get_ports {PUDC_B}]; # "PUDC_B"
 
# ----------------------------------------------------------------------------
# USB OTG Reset - Bank 35
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN G17 [get_ports {OTG_RESETN}]; # "OTG-RESETN"
 
# ----------------------------------------------------------------------------
# User DIP Switches - Bank 35
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN F22 [get_ports {SW0}]; # "SW0"
set_property PACKAGE_PIN G22 [get_ports {SW1}]; # "SW1"
set_property PACKAGE_PIN H22 [get_ports {SW2}]; # "SW2"
set_property PACKAGE_PIN F21 [get_ports {SW3}]; # "SW3"
set_property PACKAGE_PIN H19 [get_ports {SW4}]; # "SW4"
set_property PACKAGE_PIN H18 [get_ports {SW5}]; # "SW5"
set_property PACKAGE_PIN H17 [get_ports {SW6}]; # "SW6"
set_property PACKAGE_PIN M15 [get_ports {SW7}]; # "SW7"
 
# # ----------------------------------------------------------------------------
# # XADC AD Channels - Bank 35
# # ----------------------------------------------------------------------------
# set_property PACKAGE_PIN E16 [get_ports {AD0N_R}]; # "XADC-AD0N-R"
# set_property PACKAGE_PIN F16 [get_ports {AD0P_R}]; # "XADC-AD0P-R"
# set_property PACKAGE_PIN D17 [get_ports {AD8N_N}]; # "XADC-AD8N-R"
# set_property PACKAGE_PIN D16 [get_ports {AD8P_R}]; # "XADC-AD8P-R"
 
# ----------------------------------------------------------------------------
# FMC Expansion Connector - Bank 13
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN R7 [get_ports {FMC_SCL}]; # "FMC-SCL"
set_property PACKAGE_PIN U7 [get_ports {FMC_SDA}]; # "FMC-SDA"
 
# ----------------------------------------------------------------------------
# FMC Expansion Connector - Bank 33
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN AB14 [get_ports {FMC_PRSNT}]; # "FMC-PRSNT"
 
# ----------------------------------------------------------------------------
# FMC Expansion Connector - Bank 34
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN L19 [get_ports {FMC_CLK0_N}]; # "FMC-CLK0_N"
set_property PACKAGE_PIN L18 [get_ports {FMC_CLK0_P}]; # "FMC-CLK0_P"
set_property PACKAGE_PIN M20 [get_ports {FMC_LA00_CC_N}]; # "FMC-LA00_CC_N"
set_property PACKAGE_PIN M19 [get_ports {FMC_LA00_CC_P}]; # "FMC-LA00_CC_P"
set_property PACKAGE_PIN N20 [get_ports {FMC_LA01_CC_N}]; # "FMC-LA01_CC_N"
set_property PACKAGE_PIN N19 [get_ports {FMC_LA01_CC_P}]; # "FMC-LA01_CC_P"
set_property PACKAGE_PIN P18 [get_ports {FMC_LA02_N}]; # "FMC-LA02_N"
set_property PACKAGE_PIN P17 [get_ports {FMC_LA02_P}]; # "FMC-LA02_P"
set_property PACKAGE_PIN P22 [get_ports {FMC_LA03_N}]; # "FMC-LA03_N"
set_property PACKAGE_PIN N22 [get_ports {FMC_LA03_P}]; # "FMC-LA03_P"
set_property PACKAGE_PIN M22 [get_ports {FMC_LA04_N}]; # "FMC-LA04_N"
set_property PACKAGE_PIN M21 [get_ports {FMC_LA04_P}]; # "FMC-LA04_P"
set_property PACKAGE_PIN K18 [get_ports {FMC_LA05_N}]; # "FMC-LA05_N"
set_property PACKAGE_PIN J18 [get_ports {FMC_LA05_P}]; # "FMC-LA05_P"
set_property PACKAGE_PIN L22 [get_ports {FMC_LA06_N}]; # "FMC-LA06_N"
set_property PACKAGE_PIN L21 [get_ports {FMC_LA06_P}]; # "FMC-LA06_P"
set_property PACKAGE_PIN T17 [get_ports {FMC_LA07_N}]; # "FMC-LA07_N"
set_property PACKAGE_PIN T16 [get_ports {FMC_LA07_P}]; # "FMC-LA07_P"
set_property PACKAGE_PIN J22 [get_ports {FMC_LA08_N}]; # "FMC-LA08_N"
set_property PACKAGE_PIN J21 [get_ports {FMC_LA08_P}]; # "FMC-LA08_P"
set_property PACKAGE_PIN R21 [get_ports {FMC_LA09_N}]; # "FMC-LA09_N"
set_property PACKAGE_PIN R20 [get_ports {FMC_LA09_P}]; # "FMC-LA09_P"
set_property PACKAGE_PIN T19 [get_ports {FMC_LA10_N}]; # "FMC-LA10_N"
set_property PACKAGE_PIN R19 [get_ports {FMC_LA10_P}]; # "FMC-LA10_P"
set_property PACKAGE_PIN N18 [get_ports {FMC_LA11_N}]; # "FMC-LA11_N"
set_property PACKAGE_PIN N17 [get_ports {FMC_LA11_P}]; # "FMC-LA11_P"
set_property PACKAGE_PIN P21 [get_ports {FMC_LA12_N}]; # "FMC-LA12_N"
set_property PACKAGE_PIN P20 [get_ports {FMC_LA12_P}]; # "FMC-LA12_P"
set_property PACKAGE_PIN M17 [get_ports {FMC_LA13_N}]; # "FMC-LA13_N"
set_property PACKAGE_PIN L17 [get_ports {FMC_LA13_P}]; # "FMC-LA13_P"
set_property PACKAGE_PIN K20 [get_ports {FMC_LA14_N}]; # "FMC-LA14_N"
set_property PACKAGE_PIN K19 [get_ports {FMC_LA14_P}]; # "FMC-LA14_P"
set_property PACKAGE_PIN J17 [get_ports {FMC_LA15_N}]; # "FMC-LA15_N"
set_property PACKAGE_PIN J16 [get_ports {FMC_LA15_P}]; # "FMC-LA15_P"
set_property PACKAGE_PIN K21 [get_ports {FMC_LA16_N}]; # "FMC-LA16_N"
set_property PACKAGE_PIN J20 [get_ports {FMC_LA16_P}]; # "FMC-LA16_P"
 
# ----------------------------------------------------------------------------
# FMC Expansion Connector - Bank 35
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN C19 [get_ports {FMC_CLK1_N}]; # "FMC-CLK1_N"
set_property PACKAGE_PIN D18 [get_ports {FMC_CLK1_P}]; # "FMC-CLK1_P"
set_property PACKAGE_PIN B20 [get_ports {FMC_LA17_CC_N}]; # "FMC-LA17_CC_N"
set_property PACKAGE_PIN B19 [get_ports {FMC_LA17_CC_P}]; # "FMC-LA17_CC_P"
set_property PACKAGE_PIN C20 [get_ports {FMC_LA18_CC_N}]; # "FMC-LA18_CC_N"
set_property PACKAGE_PIN D20 [get_ports {FMC_LA18_CC_P}]; # "FMC-LA18_CC_P"
set_property PACKAGE_PIN G16 [get_ports {FMC_LA19_N}]; # "FMC-LA19_N"
set_property PACKAGE_PIN G15 [get_ports {FMC_LA19_P}]; # "FMC-LA19_P"
set_property PACKAGE_PIN G21 [get_ports {FMC_LA20_N}]; # "FMC-LA20_N"
set_property PACKAGE_PIN G20 [get_ports {FMC_LA20_P}]; # "FMC-LA20_P"
set_property PACKAGE_PIN E20 [get_ports {FMC_LA21_N}]; # "FMC-LA21_N"
set_property PACKAGE_PIN E19 [get_ports {FMC_LA21_P}]; # "FMC-LA21_P"
set_property PACKAGE_PIN F19 [get_ports {FMC_LA22_N}]; # "FMC-LA22_N"
set_property PACKAGE_PIN G19 [get_ports {FMC_LA22_P}]; # "FMC-LA22_P"
set_property PACKAGE_PIN D15 [get_ports {FMC_LA23_N}]; # "FMC-LA23_N"
set_property PACKAGE_PIN E15 [get_ports {FMC_LA23_P}]; # "FMC-LA23_P"
set_property PACKAGE_PIN A19 [get_ports {FMC_LA24_N}]; # "FMC-LA24_N"
set_property PACKAGE_PIN A18 [get_ports {FMC_LA24_P}]; # "FMC-LA24_P"
set_property PACKAGE_PIN C22 [get_ports {FMC_LA25_N}]; # "FMC-LA25_N"
set_property PACKAGE_PIN D22 [get_ports {FMC_LA25_P}]; # "FMC-LA25_P"
set_property PACKAGE_PIN E18 [get_ports {FMC_LA26_N}]; # "FMC-LA26_N"
set_property PACKAGE_PIN F18 [get_ports {FMC_LA26_P}]; # "FMC-LA26_P"
set_property PACKAGE_PIN D21 [get_ports {FMC_LA27_N}]; # "FMC-LA27_N"
set_property PACKAGE_PIN E21 [get_ports {FMC_LA27_P}]; # "FMC-LA27_P"
set_property PACKAGE_PIN A17 [get_ports {FMC_LA28_N}]; # "FMC-LA28_N"
set_property PACKAGE_PIN A16 [get_ports {FMC_LA28_P}]; # "FMC-LA28_P"
set_property PACKAGE_PIN C18 [get_ports {FMC_LA29_N}]; # "FMC-LA29_N"
set_property PACKAGE_PIN C17 [get_ports {FMC_LA29_P}]; # "FMC-LA29_P"
set_property PACKAGE_PIN B15 [get_ports {FMC_LA30_N}]; # "FMC-LA30_N"
set_property PACKAGE_PIN C15 [get_ports {FMC_LA30_P}]; # "FMC-LA30_P"
set_property PACKAGE_PIN B17 [get_ports {FMC_LA31_N}]; # "FMC-LA31_N"
set_property PACKAGE_PIN B16 [get_ports {FMC_LA31_P}]; # "FMC-LA31_P"
set_property PACKAGE_PIN A22 [get_ports {FMC_LA32_N}]; # "FMC-LA32_N"
set_property PACKAGE_PIN A21 [get_ports {FMC_LA32_P}]; # "FMC-LA32_P"
set_property PACKAGE_PIN B22 [get_ports {FMC_LA33_N}]; # "FMC-LA33_N"
set_property PACKAGE_PIN B21 [get_ports {FMC_LA33_P}]; # "FMC-LA33_P"
 
 
# ----------------------------------------------------------------------------
# IOSTANDARD Constraints
#
# Note that these IOSTANDARD constraints are applied to all IOs currently
# assigned within an I/O bank. If these IOSTANDARD constraints are
# evaluated prior to other PACKAGE_PIN constraints being applied, then
# the IOSTANDARD specified will likely not be applied properly to those
# pins. Therefore, bank wide IOSTANDARD constraints should be placed
# within the XDC file in a location that is evaluated AFTER all
# PACKAGE_PIN constraints within the target bank have been evaluated.
#
# Un-comment one or more of the following IOSTANDARD constraints according to
# the bank pin assignments that are required within a design.
# ----------------------------------------------------------------------------
 
# Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard.
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]];
 
# Set the bank voltage for IO Bank 34 to 1.8V by default.
# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 34]];
# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 34]];
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]];
 
# Set the bank voltage for IO Bank 35 to 1.8V by default.
# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 35]];
# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 35]];
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]];
 
# Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard.
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]];
 
 
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
 
/trunk/zed_board/syn/axi_lite_to_wbl.tcl
0,0 → 1,101
#
#*****************************************************************************************
#
#*****************************************************************************************
 
close_project -quiet
 
# set variables for project
set PROJECT_NAME axi_lite_to_wb
 
# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir [file dirname [info script] ]
 
# Create project
create_project -force $PROJECT_NAME $origin_dir/$PROJECT_NAME
 
# Set project properties
set obj [get_projects $PROJECT_NAME]
set_property "board_part" "em.avnet.com:zed:part0:1.2" $obj
set_property "default_lib" "xil_defaultlib" $obj
 
# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
create_fileset -srcset sources_1
}
 
add_files -fileset sources_1 -norecurse $origin_dir/../src/top.v
add_files -fileset sources_1 -norecurse $origin_dir/../src/reg_file_v1_0_S00_AXI.v
 
update_compile_order -fileset sources_1
 
# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property "top" "top" $obj
 
# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
create_fileset -constrset constrs_1
}
 
# Set 'constrs_1' fileset object
set obj [get_filesets constrs_1]
 
# Add/Import constrs file and set constrs file properties
set file "[file normalize "$origin_dir/../src/zedboard_master_XDC_RevC_D_v2.xdc"]"
set file_added [add_files -norecurse -fileset $obj $file]
set file "$origin_dir/../src/zedboard_master_XDC_RevC_D_v2.xdc"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
set_property "file_type" "XDC" $file_obj
 
# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]
set_property "target_constrs_file" "[file normalize "$origin_dir/../src/zedboard_master_XDC_RevC_D_v2.xdc"]" $obj
 
# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets -quiet sim_1] ""]} {
create_fileset -simset sim_1
}
 
# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
# Empty (no sources present)
 
# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property "top" "top" $obj
 
# Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} {
create_run -name synth_1 -part xc7z020clg484-1 -flow {Vivado Synthesis 2014} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
} else {
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
set_property flow "Vivado Synthesis 2014" [get_runs synth_1]
}
set obj [get_runs synth_1]
 
# set the current synth run
current_run -synthesis [get_runs synth_1]
 
# Create 'impl_1' run (if not found)
if {[string equal [get_runs -quiet impl_1] ""]} {
create_run -name impl_1 -part xc7z020clg484-1 -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
} else {
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
set_property flow "Vivado Implementation 2014" [get_runs impl_1]
}
set obj [get_runs impl_1]
 
# set the current impl run
current_run -implementation [get_runs impl_1]
 
# regenerate block diagrams
source $origin_dir/../block_diagrams/zync.tcl
 
close_project -quiet
 
puts "INFO: Project created:$PROJECT_NAME"
 
 
 
/trunk/zed_board/syn/precompiled_elfs/u-boot.elf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/zed_board/syn/precompiled_elfs/u-boot.elf
trunk/zed_board/syn/precompiled_elfs/u-boot.elf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/zed_board/syn/precompiled_elfs/zynq_fsbl_0.elf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/zed_board/syn/precompiled_elfs/zynq_fsbl_0.elf =================================================================== --- trunk/zed_board/syn/precompiled_elfs/zynq_fsbl_0.elf (nonexistent) +++ trunk/zed_board/syn/precompiled_elfs/zynq_fsbl_0.elf (revision 15)
trunk/zed_board/syn/precompiled_elfs/zynq_fsbl_0.elf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property

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