URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
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/qaz_libs
- from Rev 19 to Rev 20
- ↔ Reverse comparison
Rev 19 → Rev 20
/trunk/AXI/src/register_file.v
0,0 → 1,116
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
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module |
register_file |
( |
input [31:0] sys_data_i, |
output reg [31:0] sys_data_o, |
input [31:0] sys_addr_i, |
input [3:0] sys_sel_i, |
input sys_we_i, |
input sys_cyc_i, |
input sys_stb_i, |
output sys_ack_o, |
output sys_err_o, |
output sys_rty_o, |
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output reg soft_reset, |
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output reg [31:0] reg_scratch, |
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input sys_clk, |
input sys_reset |
); |
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//--------------------------------------------------- |
// |
wire reg_write_en = sys_cyc_i & sys_stb_i & sys_we_i; |
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//--------------------------------------------------- |
// register encoder |
reg [3:0] register_index; |
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always @( * ) |
case( sys_addr_i[25:2] ) |
24'h00_0000: register_index = 4'h0; |
24'h00_0001: register_index = 4'h1; |
24'h00_0002: register_index = 4'h2; |
24'h00_0003: register_index = 4'h3; |
24'h00_0004: register_index = 4'h4; |
24'h00_0005: register_index = 4'h5; |
24'h00_0006: register_index = 4'h6; |
24'h00_0007: register_index = 4'h7; |
24'h00_0008: register_index = 4'h8; |
24'h00_0009: register_index = 4'h9; |
24'h00_000a: register_index = 4'ha; |
24'h00_000b: register_index = 4'hb; |
24'h00_000c: register_index = 4'hc; |
24'h00_000d: register_index = 4'hd; |
24'h00_000e: register_index = 4'he; |
24'h00_000f: register_index = 4'hf; |
default: register_index = 4'h1; |
endcase |
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//--------------------------------------------------- |
// register index: 0x0 -- offset: 0x0 -- system control register |
wire register_0_wr_en = reg_write_en & (register_index == 4'h0); |
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always @( posedge sys_clk ) |
if( sys_reset ) |
soft_reset <= 0; |
else if( register_0_wr_en ) |
soft_reset <= sys_data_i[0]; |
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wire [31:0] sys_register_0 = { |
31'b0, // [31:1] |
soft_reset // [0] |
}; |
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//--------------------------------------------------- |
// register index: 0x1 -- offset: 0x4 -- version register |
wire register_1_wr_en = reg_write_en & (register_index == 4'h1); |
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wire [31:0] sys_register_1 = 32'habba_beef; |
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//--------------------------------------------------- |
// register index: 0xf -- offset: 0x3c -- scratch register |
wire register_f_wr_en = reg_write_en & (register_index == 4'hf); |
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always @( posedge sys_clk ) |
if( sys_reset ) |
reg_scratch <= 0; |
else if( register_f_wr_en ) |
reg_scratch <= sys_data_i; |
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wire [31:0] sys_register_f = reg_scratch; |
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//--------------------------------------------------- |
// register mux |
always @( * ) |
case( register_index ) |
4'h0: sys_data_o = sys_register_0; |
4'h1: sys_data_o = sys_register_1; |
4'hf: sys_data_o = sys_register_f; |
default: sys_data_o = 32'h0bad_c0de; |
endcase |
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//--------------------------------------------------- |
// outputs |
assign sys_ack_o = sys_cyc_i & sys_stb_i; |
assign sys_err_o = 1'b0; |
assign sys_rty_o = 1'b0; |
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endmodule |
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