OpenCores
URL https://opencores.org/ocsvn/qspiflash/qspiflash/trunk

Subversion Repositories qspiflash

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 21 to Rev 22
    Reverse comparison

Rev 21 → Rev 22

/qspiflash/trunk/rtl/wbqspiflash.v
2,7 → 2,7
//
// Filename: wbspiflash.v
//
// Project: Wishbone Controlled Quad SPI Flash Controller
// Project: A Set of Wishbone Controlled SPI Flash Controllers
//
// Purpose: Access a Quad SPI flash via a WISHBONE interface. This
// includes both read and write (and erase) commands to the SPI
29,31 → 29,34
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
// Copyright (C) 2015-2019, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// This file is part of the set of Wishbone controlled SPI flash controllers
// project
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
// The Wishbone SPI flash controller project is free software (firmware):
// you can redistribute it and/or modify it under the terms of the GNU Lesser
// General Public License as published by the Free Software Foundation, either
// version 3 of the License, or (at your option) any later version.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// The Wishbone SPI flash controller project is distributed in the hope
// that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this program. (It's in the $(ROOT)/doc directory. Run make
// with no target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
// License: LGPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/lgpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`include "flashconfig.v"
//
`default_nettype none
//
`define WBQSPI_RESET 5'd0
74,8 → 77,6
`define WBQSPI_WAIT_TIL_IDLE 5'd15
//
//
`ifndef READ_ONLY
//
`define WBQSPI_WAIT_WIP_CLEAR 5'd16
`define WBQSPI_CHECK_WIP_CLEAR 5'd17
`define WBQSPI_CHECK_WIP_DONE 5'd18
92,8 → 93,6
`define WBQSPI_CLEAR_STATUS 5'd29
`define WBQSPI_IDLE_CHECK_WIP 5'd30
//
`endif
 
module wbqspiflash(i_clk,
// Internal wishbone connections
i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
104,6 → 103,7
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
o_interrupt);
parameter ADDRESS_WIDTH=22;
parameter [0:0] OPT_READ_ONLY = 1'b0;
localparam AW = ADDRESS_WIDTH-2;
input wire i_clk;
// Wishbone, inputs first
251,7 → 251,7
spif_cmd <= i_wb_we;
spif_addr <= i_wb_addr;
spif_data <= i_wb_data;
spif_ctrl <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
spif_ctrl <= (i_wb_ctrl_stb)&&(!i_wb_data_stb);
spif_req <= (i_wb_ctrl_stb)||(i_wb_data_stb);
spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
spi_hold <= 1'b0;
261,14 → 261,13
if (i_wb_data_stb)
begin
 
if (i_wb_we) // Request to write a page
if ((OPT_READ_ONLY)&&(i_wb_we)) // Write request
begin
`ifdef READ_ONLY
o_wb_ack <= 1'b1;
o_wb_stall <= 1'b0;
end else
`else
if((~write_protect)&&(~write_in_progress))
end else if (i_wb_we) // Request to write a page
begin
if((!write_protect)&&(!write_in_progress))
begin // 00
spi_wr <= 1'b1;
spi_len <= 2'b00; // 8 bits
291,8 → 290,7
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
end
end else if (~write_in_progress)
`endif
end else if (!write_in_progress)
begin // Read access, normal mode(s)
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
307,21 → 305,19
state <= `WBQSPI_RD_DUMMY;
spi_len <= 2'b11; // cmd+addr,32bits
end
`ifndef READ_ONLY
end else begin
end else if (!OPT_READ_ONLY) begin
// A write is in progress ... need to stall
// the bus until the write is complete.
state <= `WBQSPI_WAIT_WIP_CLEAR;
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
`endif
end
end else if ((i_wb_ctrl_stb)&&(i_wb_we))
end else if ((OPT_READ_ONLY)&&(i_wb_ctrl_stb)&&(i_wb_we))
begin
`ifdef READ_ONLY
o_wb_ack <= 1'b1;
o_wb_stall <= 1'b0;
`else
end else if ((i_wb_ctrl_stb)&&(i_wb_we))
begin
o_wb_stall <= 1'b1;
case(i_wb_addr[1:0])
2'b00: begin // Erase command register
335,7 → 331,7
o_wb_ack <= 1'b1;
o_wb_stall <= 1'b0;
 
if ((i_wb_data[31])&&(~write_protect))
if ((i_wb_data[31])&&(!write_protect))
begin
spi_wr <= 1'b1;
spi_len <= 2'b00;
349,10 → 345,10
state <= `WBQSPI_WAIT_WIP_CLEAR;
o_wb_ack <= 1'b1;
o_wb_stall <= 1'b1;
end else
end else begin
o_wb_ack <= 1'b1;
o_wb_stall <= 1'b0;
end
end end
2'b01: begin
// Write the configuration register
o_wb_ack <= 1'b1;
381,7 → 377,6
o_wb_stall <= 1'b0;
end
endcase
`endif
end else if (i_wb_ctrl_stb) // &&(!i_wb_we))
begin
case(i_wb_addr[1:0])
433,8 → 428,7
o_wb_stall <= 1'b1;
end
endcase
`ifndef READ_ONLY
end else if ((~i_wb_cyc)&&(write_in_progress))
end else if ((!OPT_READ_ONLY)&&(!i_wb_cyc)&&(write_in_progress))
begin
state <= `WBQSPI_IDLE_CHECK_WIP;
spi_wr <= 1'b1;
443,7 → 437,6
 
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
`endif
end
end else if (state == `WBQSPI_RDIDLE)
begin
453,7 → 446,7
spif_cmd <= i_wb_we;
spif_addr <= i_wb_addr;
spif_data <= i_wb_data;
spif_ctrl <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
spif_ctrl <= (i_wb_ctrl_stb)&&(!i_wb_data_stb);
spif_req <= (i_wb_ctrl_stb)||(i_wb_data_stb);
spi_hold <= 1'b0;
spi_spd<= 1'b1;
501,19 → 494,19
spi_spd <= 1'b0;
spi_dir <= 1'b0;
spif_req<= (spif_req) && (i_wb_cyc);
if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // only in full idle ...
if ((!spi_busy)&&(o_qspi_cs_n)&&(!spi_wr)) // only in full idle ...
begin
// Data register access
if (~spif_ctrl)
if (!spif_ctrl)
begin
if (spif_cmd) // Request to write a page
if ((OPT_READ_ONLY)&&(spif_cmd)) // Request to write a page
begin
`ifdef READ_ONLY
o_wb_ack <= spif_req;
o_wb_stall <= 1'b0;
state <= `WBQSPI_IDLE;
`else
if((~write_protect)&&(~write_in_progress))
end else if (spif_cmd)
begin
if((!write_protect)&&(!write_in_progress))
begin // 00
spi_wr <= 1'b1;
spi_len <= 2'b00; // 8 bits
537,9 → 530,8
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
end
// end else if (~write_in_progress) // always true
// end else if (!write_in_progress) // always true
// but ... we wouldn't get here on a normal read access
`endif
end else begin
// Something's wrong, we should never
// get here
546,13 → 538,12
// Attempt to go to idle to recover
state <= `WBQSPI_IDLE;
end
end else if ((spif_ctrl)&&(spif_cmd))
end else if ((OPT_READ_ONLY)&&(spif_ctrl)&&(spif_cmd))
begin
`ifdef READ_ONLY
o_wb_ack <= spif_req;
o_wb_stall <= 1'b0;
state <= `WBQSPI_IDLE;
`else
end else if ((spif_ctrl)&&(spif_cmd)) begin
o_wb_stall <= 1'b1;
case(spif_addr[1:0])
2'b00: begin // Erase command register
604,8 → 595,7
state <= `WBQSPI_IDLE;
end
endcase
`endif
end else begin // on (~spif_we)
end else begin // on (!spif_we)
case(spif_addr[1:0])
2'b00: begin // Read local register
// Nonsense case--would've done this
662,7 → 652,7
spi_hold <= 1'b0;
spif_req<= (spif_req) && (i_wb_cyc);
if ((~spi_busy)&&(~o_qspi_cs_n))
if ((!spi_busy)&&(!o_qspi_cs_n))
// Our command was accepted
state <= `WBQSPI_READ_CMD;
end else if (state == `WBQSPI_QRD_ADDRESS)
681,7 → 671,7
spi_hold <= 1'b0;
spif_req<= (spif_req) && (i_wb_cyc);
if ((~spi_busy)&&(spi_spd))
if ((!spi_busy)&&(spi_spd))
// Our command was accepted
state <= `WBQSPI_QRD_DUMMY;
end else if (state == `WBQSPI_QRD_DUMMY)
697,7 → 687,7
spi_hold <= 1'b0;
spif_req<= (spif_req) && (i_wb_cyc);
if ((~spi_busy)&&(spi_in[31:28] == 4'ha))
if ((!spi_busy)&&(spi_in[31:28] == 4'ha))
// Our command was accepted
state <= `WBQSPI_READ_CMD;
end else if (state == `WBQSPI_READ_CMD)
716,7 → 706,7
end else if (state == `WBQSPI_READ_DATA)
begin
// Pipelined read support
spi_wr <=((i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1)));
spi_wr <=((i_wb_data_stb)&&(!i_wb_we)&&(i_wb_addr== (spif_addr+1)))&&(spif_req);
spi_in <= 32'h00;
spi_len <= 2'b11;
// Don't adjust the speed here, it was set in the setup
735,19 → 725,19
// owns the bus to realize their command went through.
spi_hold <= 1'b1;
spif_req<= (spif_req) && (i_wb_cyc);
if ((spi_valid)&&(~spi_in[31]))
if ((spi_valid)&&(!spi_in[31]))
begin // Single pulse acknowledge and write data out
o_wb_ack <= spif_req;
o_wb_stall <= (~spi_wr);
o_wb_stall <= (!spi_wr);
// adjust endian-ness to match the PC
o_wb_data <= spi_out;
state <= (spi_wr)?`WBQSPI_READ_DATA
: ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
spif_req <= spi_wr;
spi_hold <= (~spi_wr);
spi_hold <= (!spi_wr);
if (spi_wr)
spif_addr <= i_wb_addr;
end else if (~i_wb_cyc)
end else if ((!spif_req)||(!i_wb_cyc))
begin // FAIL SAFE: If the bus cycle ends, forget why we're
// here, just go back to idle
state <= ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
765,7 → 755,7
o_wb_stall <= 1'b1;
o_wb_ack <= 1'b0;
spif_req <= 1'b0;
if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
if ((!spi_busy)&&(o_qspi_cs_n)&&(!spi_wr)) // Wait for a full
begin // clearing of the SPI port before moving on
state <= `WBQSPI_RDIDLE;
o_wb_stall <= 1'b0;
786,7 → 776,7
spi_dir <= 1'b1; // Reading
spi_hold <= 1'b0;
spif_req <= (spif_req) && (i_wb_cyc);
if ((~spi_busy)&&(~o_qspi_cs_n)&&(spi_len == 2'b11))
if ((!spi_busy)&&(!o_qspi_cs_n)&&(spi_len == 2'b11))
// Our command was accepted, now go read the result
state <= `WBQSPI_READ_ID;
end else if (state == `WBQSPI_READ_ID)
807,7 → 797,7
o_wb_data <= spi_out[31:0];
o_wb_ack <= spif_req;
spif_req <= 1'b0;
end else if ((~spi_busy)&&(o_qspi_cs_n))
end else if ((!spi_busy)&&(o_qspi_cs_n))
begin
state <= `WBQSPI_IDLE;
o_wb_stall <= 1'b0;
839,7 → 829,7
end
end
 
if ((~spi_busy)&&(~spi_wr))
if ((!spi_busy)&&(!spi_wr))
state <= `WBQSPI_IDLE;
end else if (state == `WBQSPI_READ_CONFIG)
begin // We enter after the command has been given, for now just
856,7 → 846,7
quad_mode_enabled <= spi_out[1];
end
 
if ((~spi_busy)&&(~spi_wr))
if ((!spi_busy)&&(!spi_wr))
begin
state <= `WBQSPI_IDLE;
o_wb_ack <= spif_req;
868,14 → 858,13
//
// Write/erase data section
//
`ifndef READ_ONLY
end else if (state == `WBQSPI_WAIT_WIP_CLEAR)
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_WAIT_WIP_CLEAR))
begin
o_wb_stall <= 1'b1;
o_wb_ack <= 1'b0;
spi_wr <= 1'b0;
spif_req<= (spif_req) && (i_wb_cyc);
if (~spi_busy)
if (!spi_busy)
begin
spi_wr <= 1'b1;
spi_in <= { 8'h05, 24'h0000 };
885,7 → 874,7
spi_spd <= 1'b0; // Slow speed
spi_dir <= 1'b0;
end
end else if (state == `WBQSPI_CHECK_WIP_CLEAR)
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_CHECK_WIP_CLEAR))
begin
o_wb_stall <= 1'b1;
o_wb_ack <= 1'b0;
897,7 → 886,7
spi_spd <= 1'b0; // Slow speed
spi_dir <= 1'b0;
spif_req<= (spif_req) && (i_wb_cyc);
if ((spi_valid)&&(~spi_out[0]))
if ((spi_valid)&&(!spi_out[0]))
begin
state <= `WBQSPI_CHECK_WIP_DONE;
spi_wr <= 1'b0;
905,7 → 894,7
write_in_progress <= 1'b0;
last_status <= spi_out[7:0];
end
end else if (state == `WBQSPI_CHECK_WIP_DONE)
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_CHECK_WIP_DONE))
begin
o_wb_stall <= 1'b1;
o_wb_ack <= 1'b0;
917,7 → 906,7
spi_spd <= 1'b0; // Slow speed
spi_dir <= 1'b0;
spif_req<= (spif_req) && (i_wb_cyc);
if ((o_qspi_cs_n)&&(~spi_busy)) // Chip select line is high, we can continue
if ((o_qspi_cs_n)&&(!spi_busy)) // Chip select line is high, we can continue
begin
spi_wr <= 1'b0;
spi_hold <= 1'b0;
963,19 → 952,19
// spif_cmd <= i_wb_we;
// spif_addr <= i_wb_addr;
// spif_data <= i_wb_data;
// spif_ctrl <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
// spif_ctrl <= (i_wb_ctrl_stb)&&(!i_wb_data_stb);
// spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
end
end else if (state == `WBQSPI_WEN)
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_WEN))
begin // We came here after issuing a write enable command
spi_wr <= 1'b0;
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
spif_req<= (spif_req) && (i_wb_cyc);
if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Let's come to a full stop
if ((!spi_busy)&&(o_qspi_cs_n)&&(!spi_wr)) // Let's come to a full stop
state <= (quad_mode_enabled)?`WBQSPI_QPP:`WBQSPI_PP;
// state <= `WBQSPI_PP;
end else if (state == `WBQSPI_PP)
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_PP))
begin // We come here under a full stop / full port idle mode
// Issue our command immediately
spi_wr <= 1'b1;
991,7 → 980,7
state <= `WBQSPI_WR_DATA;
if (spif_sector == erased_sector)
dirty_sector <= 1'b1;
end else if (state == `WBQSPI_QPP)
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_QPP))
begin // We come here under a full stop / full port idle mode
// Issue our command immediately
spi_wr <= 1'b1;
1013,7 → 1002,7
end
if (spif_sector == erased_sector)
dirty_sector <= 1'b1;
end else if (state == `WBQSPI_WR_DATA)
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_WR_DATA))
begin
o_wb_stall <= 1'b1;
o_wb_ack <= 1'b0;
1021,13 → 1010,13
spi_in <= spif_data;
spi_len <= 2'b11; // Write 4 bytes
spi_hold <= 1'b1;
if (~spi_busy)
if (!spi_busy)
begin
o_wb_ack <= spif_req; // Ack when command given
state <= `WBQSPI_WR_BUS_CYCLE;
end
spif_req<= (spif_req) && (i_wb_cyc);
end else if (state == `WBQSPI_WR_BUS_CYCLE)
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_WR_BUS_CYCLE))
begin
o_wb_ack <= 1'b0; // Turn off our ack and stall flags
o_wb_stall <= 1'b1;
1035,7 → 1024,7
spi_hold <= 1'b1;
write_in_progress <= 1'b1;
spif_req<= (spif_req) && (i_wb_cyc);
if (~i_wb_cyc)
if (!i_wb_cyc)
begin
state <= `WBQSPI_WAIT_TIL_IDLE;
spi_hold <= 1'b0;
1042,7 → 1031,7
end else if (spi_wr)
begin // Give the SPI a chance to get busy on the last write
// Do nothing here.
end else if ((i_wb_data_stb)&&(i_wb_we)
end else if ((spif_req)&&(i_wb_data_stb)&&(i_wb_we)
&&(i_wb_addr == (spif_addr+1))
&&(i_wb_addr[(AW-1):6]==spif_addr[(AW-1):6]))
begin
1056,13 → 1045,13
state <= `WBQSPI_WR_DATA;
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b0;
end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(~o_wb_ack)) // Writing out of bounds
end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(!o_wb_ack)) // Writing out of bounds
begin
spi_hold <= 1'b0;
spi_wr <= 1'b0;
state <= `WBQSPI_WAIT_TIL_IDLE;
end // Otherwise we stay here
end else if (state == `WBQSPI_WRITE_CONFIG)
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_WRITE_CONFIG))
begin // We enter immediately after commanding a WEN
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
1072,7 → 1061,7
spi_wr <= 1'b0;
spi_hold <= 1'b0;
spif_req <= (spif_req) && (i_wb_cyc);
if ((~spi_busy)&&(~spi_wr))
if ((!spi_busy)&&(!spi_wr))
begin
spi_wr <= 1'b1;
state <= `WBQSPI_WAIT_TIL_IDLE;
1079,7 → 1068,7
write_in_progress <= 1'b1;
quad_mode_enabled <= spif_data[1];
end
end else if (state == `WBQSPI_WRITE_STATUS)
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_WRITE_STATUS))
begin // We enter immediately after commanding a WEN
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
1090,18 → 1079,18
spi_wr <= 1'b0;
spi_hold <= 1'b0;
spif_req <= (spif_req) && (i_wb_cyc);
if ((~spi_busy)&&(~spi_wr))
if ((!spi_busy)&&(!spi_wr))
begin
spi_wr <= 1'b1;
last_status <= spif_data[7:0];
write_in_progress <= 1'b1;
if(((last_status[6])||(last_status[5]))
&&((~spif_data[6])&&(~spif_data[5])))
&&((!spif_data[6])&&(!spif_data[5])))
state <= `WBQSPI_CLEAR_STATUS;
else
state <= `WBQSPI_WAIT_TIL_IDLE;
end
end else if (state == `WBQSPI_ERASE_CMD)
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_ERASE_CMD))
begin // Know that WIP is clear on entry, WEN has just been commanded
spi_wr <= 1'b0;
o_wb_ack <= 1'b0;
1122,12 → 1111,12
dirty_sector <= 1'b0;
 
// Wait for a full stop before issuing this command
if ((~spi_busy)&&(~spi_wr)&&(o_qspi_cs_n))
if ((!spi_busy)&&(!spi_wr)&&(o_qspi_cs_n))
begin // When our command is accepted, move to the next state
spi_wr <= 1'b1;
state <= `WBQSPI_ERASE_BLOCK;
end
end else if (state == `WBQSPI_ERASE_BLOCK)
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_ERASE_BLOCK))
begin
spi_wr <= 1'b0;
spi_hold <= 1'b0;
1137,9 → 1126,9
// When the port clears, we can head back to idle
// No ack necessary, we ackd before getting
// here.
if ((~spi_busy)&&(~spi_wr))
if ((!spi_busy)&&(!spi_wr))
state <= `WBQSPI_IDLE;
end else if (state == `WBQSPI_CLEAR_STATUS)
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_CLEAR_STATUS))
begin // Issue a clear status command
spi_wr <= 1'b1;
spi_hold <= 1'b0;
1149,9 → 1138,9
spi_dir <= 1'b0;
last_status[6:5] <= 2'b00;
spif_req <= (spif_req) && (i_wb_cyc);
if ((spi_wr)&&(~spi_busy))
if ((spi_wr)&&(!spi_busy))
state <= `WBQSPI_WAIT_TIL_IDLE;
end else if (state == `WBQSPI_IDLE_CHECK_WIP)
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_IDLE_CHECK_WIP))
begin // We are now in read status register mode
 
// No bus commands have (yet) been given
1161,7 → 1150,7
 
// Stay in this mode unless/until we get a command, or
// the write is over
spi_wr <= (((~i_wb_cyc)||((~i_wb_data_stb)&&(~i_wb_ctrl_stb)))
spi_wr <= (((!i_wb_cyc)||((!i_wb_data_stb)&&(!i_wb_ctrl_stb)))
&&(write_in_progress));
spi_len <= 2'b00; // 8 bit reads
spi_spd <= 1'b0; // SPI, not quad
1169,18 → 1158,17
if (spi_valid)
begin
write_in_progress <= spi_out[0];
if ((~spi_out[0])&&(write_in_progress))
if ((!spi_out[0])&&(write_in_progress))
o_interrupt <= 1'b1;
end else
o_interrupt <= 1'b0;
 
if ((~spi_wr)&&(~spi_busy)&&(o_qspi_cs_n))
if ((!spi_wr)&&(!spi_busy)&&(o_qspi_cs_n))
begin // We can now go to idle and process a command
o_wb_stall <= 1'b0;
o_wb_ack <= 1'b0;
state <= `WBQSPI_IDLE;
end
`endif // !READ_ONLY
end else // if (state == `WBQSPI_WAIT_TIL_IDLE) or anything else
begin
spi_wr <= 1'b0;
1188,7 → 1176,7
o_wb_stall <= 1'b1;
o_wb_ack <= 1'b0;
spif_req <= 1'b0;
if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
if ((!spi_busy)&&(o_qspi_cs_n)&&(!spi_wr)) // Wait for a full
begin // clearing of the SPI port before moving on
state <= `WBQSPI_IDLE;
o_wb_stall <= 1'b0;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.