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URL https://opencores.org/ocsvn/qspiflash/qspiflash/trunk

Subversion Repositories qspiflash

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  • This comparison shows the changes necessary to convert path
    /qspiflash/trunk/rtl
    from Rev 9 to Rev 10
    Reverse comparison

Rev 9 → Rev 10

/eqspiflash.v
144,7 → 144,7
always @(posedge i_clk_200mhz)
o_cmd_accepted=((i_wb_data_stb)||(i_wb_ctrl_stb))&&(~o_wb_stall);
//
// llqspi
// lleqspi
//
// Providing the low-level SPI interface
//
153,7 → 153,7
reg [1:0] spi_len;
wire [31:0] spi_out;
wire spi_valid, spi_busy, spi_stopped;
llqspi lowlvl(i_clk_200mhz, spi_wr, spi_hold, spi_word, spi_len,
lleqspi lowlvl(i_clk_200mhz, spi_wr, spi_hold, spi_word, spi_len,
spi_spd, spi_dir, spi_recycle, spi_out, spi_valid, spi_busy,
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat);
assign spi_stopped = (o_qspi_cs_n)&&(~spi_busy)&&(~spi_wr);
1254,7 → 1254,7
endcase
end
 
assign o_quad = 1'b0;
assign o_quad = 1'b1;
 
reg nxt_data_ack;
 
/lleqspi.v
15,7 → 15,7
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
37,21 → 37,21
//
//
///////////////////////////////////////////////////////////////////////////
`define QSPI_IDLE 3'h0
`define QSPI_START 3'h1
`define QSPI_BITS 3'h2
`define QSPI_READY 3'h3
`define QSPI_HOLDING 3'h4
`define QSPI_STOP 3'h5
`define QSPI_STOP_B 3'h6
`define QSPI_RECYCLE 3'h7
`define EQSPI_IDLE 3'h0
`define EQSPI_START 3'h1
`define EQSPI_BITS 3'h2
`define EQSPI_READY 3'h3
`define EQSPI_HOLDING 3'h4
`define EQSPI_STOP 3'h5
`define EQSPI_STOP_B 3'h6
`define EQSPI_RECYCLE 3'h7
 
// Modes
`define QSPI_MOD_SPI 2'b00
`define QSPI_MOD_QOUT 2'b10 // Write
`define QSPI_MOD_QIN 2'b11 // Read
`define EQSPI_MOD_SPI 2'b00
`define EQSPI_MOD_QOUT 2'b10 // Write
`define EQSPI_MOD_QIN 2'b11 // Read
 
module llqspi(i_clk,
module lleqspi(i_clk,
// Module interface
i_wr, i_hold, i_word, i_len, i_spd, i_dir, i_recycle,
o_word, o_valid, o_busy,
189,7 → 189,7
reg [31:0] r_word;
reg [30:0] r_input;
reg [2:0] state;
initial state = `QSPI_IDLE;
initial state = `EQSPI_IDLE;
initial o_sck = 1'b1;
initial o_cs_n = 1'b1;
initial o_dat = 4'hd;
203,11 → 203,11
rd_spd <= r_spd;
rd_valid <= 1'b0;
if ((state == `QSPI_IDLE)&&(o_sck))
if ((state == `EQSPI_IDLE)&&(o_sck))
begin
o_cs_n <= 1'b1;
o_busy <= 1'b0;
o_mod <= `QSPI_MOD_SPI;
o_mod <= `EQSPI_MOD_SPI;
r_word <= i_word;
r_spd <= i_spd;
r_dir <= i_dir;
217,16 → 217,16
o_sck <= 1'b1;
if (i_wr)
begin
state <= `QSPI_START;
state <= `EQSPI_START;
o_cs_n <= 1'b0;
o_busy <= 1'b1;
end
end else if (state == `QSPI_START)
end else if (state == `EQSPI_START)
begin // We come in here with sck high, stay here 'til sck is low
o_sck <= 1'b0;
if (o_sck == 1'b0)
begin
state <= `QSPI_BITS;
state <= `EQSPI_BITS;
spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );
if (r_spd)
r_word <= { r_word[27:0], 4'h0 };
233,7 → 233,7
else
r_word <= { r_word[30:0], 1'b0 };
end
o_mod <= (r_spd) ? { 1'b1, r_dir } : `QSPI_MOD_SPI;
o_mod <= (r_spd) ? { 1'b1, r_dir } : `EQSPI_MOD_SPI;
o_cs_n <= 1'b0;
o_busy <= 1'b1;
if (r_spd)
243,8 → 243,8
end else if (~o_sck)
begin
o_sck <= 1'b1;
o_busy <= ((state != `QSPI_READY)||(~i_wr));
end else if (state == `QSPI_BITS)
o_busy <= ((state != `EQSPI_READY)||(~i_wr));
end else if (state == `EQSPI_BITS)
begin
// Should enter into here with at least a spi_len
// of one, perhaps more
256,17 → 256,17
r_word <= { r_word[27:0], 4'h0 };
spi_len <= spi_len - 6'h4;
if (spi_len == 6'h4)
state <= `QSPI_READY;
state <= `EQSPI_READY;
end else begin
o_dat <= { 3'b110, r_word[31] };
r_word <= { r_word[30:0], 1'b0 };
spi_len <= spi_len - 6'h1;
if (spi_len == 6'h1)
state <= `QSPI_READY;
state <= `EQSPI_READY;
end
 
rd_input <= 1'b1;
end else if (state == `QSPI_READY)
end else if (state == `EQSPI_READY)
begin
o_cs_n <= 1'b0;
o_busy <= 1'b1;
277,7 → 277,7
o_sck <= (i_hold); // No clocks while holding
if((~o_busy)&&(i_wr))// Acknowledge a new request
begin
state <= `QSPI_BITS;
state <= `EQSPI_BITS;
o_busy <= 1'b1;
o_sck <= 1'b0;
 
285,7 → 285,7
r_spd <= i_spd;
r_dir <= i_dir;
// Set up the first bits on the bus
o_mod <= (i_spd) ? { 1'b1, i_dir } : `QSPI_MOD_SPI;
o_mod <= (i_spd) ? { 1'b1, i_dir } : `EQSPI_MOD_SPI;
if (i_spd)
begin
o_dat <= i_word[31:28];
305,7 → 305,7
rd_valid <= 1'b1;
end else begin
o_sck <= 1'b1;
state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
o_busy <= (~i_hold);
 
// Read a bit upon any transition
312,7 → 312,7
rd_valid <= 1'b1;
rd_input <= 1'b1;
end
end else if (state == `QSPI_HOLDING)
end else if (state == `EQSPI_HOLDING)
begin
// We need this state so that the o_valid signal
// can get strobed with our last result. Otherwise
327,7 → 327,7
o_busy <= 1'b0;
if((~o_busy)&&(i_wr))// Acknowledge a new request
begin
state <= `QSPI_BITS;
state <= `EQSPI_BITS;
o_busy <= 1'b1;
o_sck <= 1'b0;
 
335,7 → 335,7
r_spd <= i_spd;
r_dir <= i_dir;
// Set up the first bits on the bus
o_mod<=(i_spd)?{ 1'b1, i_dir } : `QSPI_MOD_SPI;
o_mod<=(i_spd)?{ 1'b1, i_dir } : `EQSPI_MOD_SPI;
if (i_spd)
begin
o_dat <= i_word[31:28];
348,43 → 348,44
end
end else begin
o_sck <= 1'b1;
state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
o_busy <= (~i_hold);
end
end else if (state == `QSPI_STOP)
end else if (state == `EQSPI_STOP)
begin
o_sck <= 1'b1; // Stop the clock
rd_valid <= 1'b0; // Output may have just been valid, but no more
o_busy <= 1'b1; // Still busy till port is clear
state <= `QSPI_STOP_B;
o_mod <= `QSPI_MOD_SPI;
end else if (state == `QSPI_STOP_B)
state <= `EQSPI_STOP_B;
// Can't change modes for at least one cycle
// o_mod <= `EQSPI_MOD_SPI;
end else if (state == `EQSPI_STOP_B)
begin
o_cs_n <= 1'b1;
o_sck <= 1'b1;
// Do I need this????
// spi_len <= 3; // Minimum CS high time before next cmd
state <= `QSPI_RECYCLE;
state <= `EQSPI_RECYCLE;
o_busy <= 1'b1;
o_mod <= `QSPI_MOD_SPI;
o_mod <= `EQSPI_MOD_SPI;
end else begin // Recycle state
r_recycle <= r_recycle - 1'b1;
o_cs_n <= 1'b1;
o_sck <= 1'b1;
o_busy <= 1'b1;
o_mod <= `QSPI_MOD_SPI;
o_mod <= `EQSPI_MOD_SPI;
o_dat <= 4'hc;
if (r_recycle[3:1] == 3'h0)
state <= `QSPI_IDLE;
state <= `EQSPI_IDLE;
end
/*
end else begin // Invalid states, should never get here
state <= `QSPI_STOP;
state <= `EQSPI_STOP;
o_valid <= 1'b0;
o_busy <= 1'b1;
o_cs_n <= 1'b1;
o_sck <= 1'b1;
o_mod <= `QSPI_MOD_SPI;
o_mod <= `EQSPI_MOD_SPI;
o_dat <= 4'hd;
end
*/
392,7 → 393,7
 
always @(posedge i_clk)
begin
if ((state == `QSPI_IDLE)||(rd_valid))
if ((state == `EQSPI_IDLE)||(rd_valid))
r_input <= 31'h00;
else if ((rd_input)&&(r_spd))
r_input <= { r_input[26:0], i_dat };

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