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URL https://opencores.org/ocsvn/robust_axi_fabric/robust_axi_fabric/trunk

Subversion Repositories robust_axi_fabric

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  • This comparison shows the changes necessary to convert path 
    /robust_axi_fabric/trunk/src/base
    from Rev 19 to Rev 20
    ↔ Reverse comparison
  •

Rev 19 → Rev 20

/ic_registry_wr.v
65,6 → 65,7
wire cmd_pop_MMX;
wire cmd_pop_MMX_IDGROUP_MMX_ID.IDX;
 
wire slave_empty_MMX;
wire [SLV_BITS-1:0] slave_in_MMX_IDGROUP_MMX_ID.IDX;
wire [SLV_BITS-1:0] slave_out_MMX_IDGROUP_MMX_ID.IDX;
wire slave_empty_MMX_IDGROUP_MMX_ID.IDX;
80,6 → 81,9
reg [SLV_BITS-1:0] MMX_WSLV;
reg MMX_WOK;
 
reg MMX_pending;
reg MMX_pending_d;
wire MMX_pending_rise;
88,7 → 92,7
assign Wmatch_MMX_IDGROUP_MMX_ID.IDX = MMX_WID == ID_BITS'bADD_IDGROUP_MMX_ID;
assign cmd_push_MMX = MMX_AWVALID & MMX_AWREADY;
assign cmd_push_MMX = MMX_AWVALID & (MMX_pending ? MMX_pending_rise : MMX_AWREADY);
assign cmd_push_MMX_IDGROUP_MMX_ID.IDX = cmd_push_MMX & AWmatch_MMX_IDGROUP_MMX_ID.IDX;
assign cmd_pop_MMX = MMX_WVALID & MMX_WREADY & MMX_WLAST;
assign cmd_pop_MMX_IDGROUP_MMX_ID.IDX = cmd_pop_MMX & Wmatch_MMX_IDGROUP_MMX_ID.IDX;
99,7 → 103,22
assign slave_in_MMX_IDGROUP_MMX_ID.IDX = MMX_AWSLV;
 
 
assign MMX_pending_rise = MMX_pending & (~MMX_pending_d);
always @(posedge clk or posedge reset)
if (reset)
begin
MMX_pending <= #FFD 1'b0;
MMX_pending_d <= #FFD 1'b0;
end
else
begin
MMX_pending <= #FFD MMX_AWVALID & (~MMX_AWREADY);
MMX_pending_d <= #FFD MMX_pending;
end
LOOP MX
always @(*)
begin
112,7 → 131,7
always @(*)
begin
case (MMX_WSLV)
SLV_BITS'dSX : MMX_WOK = master_out_SSX == MSTR_BITS'dMX;
SLV_BITS'dSX : MMX_WOK = (master_out_SSX == MSTR_BITS'dMX) & (~slave_empty_MMX);
default : MMX_WOK = 1'b0;
endcase
end
120,7 → 139,9
ENDLOOP MX
LOOP MX
assign slave_empty_MMX = GONCAT(slave_empty_MMX_IDGROUP_MMX_ID.IDX &);
LOOP IX GROUP_MMX_ID.NUM
prgen_fifo #(SLV_BITS, CMD_DEPTH)
slave_fifo_MMX_IDIX(
.clk(clk),
139,7 → 160,7
LOOP SX
prgen_fifo #(MSTR_BITS, 32) //TBD SLV_DEPTH
prgen_fifo #(MSTR_BITS, SLV_DEPTH)
master_fifo_SSX(
.clk(clk),
.reset(reset),
/ic_wdata.v
37,28 → 37,28
 
parameter STRB_BITS = DATA_BITS/8;
input clk;
input reset;
input clk;
input reset;
port MMX_AWGROUP_IC_AXI_CMD;
port MMX_WGROUP_IC_AXI_W;
revport SSX_WGROUP_IC_AXI_W;
input SSX_AWVALID;
input SSX_AWREADY;
input [MSTR_BITS-1:0] SSX_AWMSTR;
port MMX_AWGROUP_IC_AXI_CMD;
port MMX_WGROUP_IC_AXI_W;
revport SSX_WGROUP_IC_AXI_W;
input SSX_AWVALID;
input SSX_AWREADY;
input [MSTR_BITS-1:0] SSX_AWMSTR;
 
 
parameter WBUS_WIDTH = GONCAT(GROUP_IC_AXI_W.IN.WIDTH +);
parameter WBUS_WIDTH = GONCAT(GROUP_IC_AXI_W.IN.WIDTH +);
 
wire [WBUS_WIDTH-1:0] SSX_WBUS;
wire [WBUS_WIDTH-1:0] SSX_WBUS;
wire [WBUS_WIDTH-1:0] MMX_WBUS;
wire [WBUS_WIDTH-1:0] MMX_WBUS;
wire [SLV_BITS-1:0] MMX_WSLV;
wire MMX_WOK;
wire [SLV_BITS-1:0] MMX_WSLV;
wire MMX_WOK;
wire SSX_MMX;
wire SSX_MMX;
 
 
78,12 → 78,12
.MMX_WLAST(MMX_WLAST),
.MMX_WSLV(MMX_WSLV),
.MMX_WOK(MMX_WOK),
.SSX_AWVALID(SSX_AWVALID),
.SSX_AWREADY(SSX_AWREADY),
.SSX_AWVALID(SSX_AWVALID),
.SSX_AWREADY(SSX_AWREADY),
.SSX_AWMSTR(SSX_AWMSTR),
.SSX_WVALID(SSX_WVALID),
.SSX_WREADY(SSX_WREADY),
.SSX_WLAST(SSX_WLAST),
.SSX_WVALID(SSX_WVALID),
.SSX_WREADY(SSX_WREADY),
.SSX_WLAST(SSX_WLAST),
STOMP ,
);
 
/def_ic.txt
38,8 → 38,9
SWAP.USER MASTER_NUM 3 ##number of masters
SWAP.USER SLAVE_NUM 6 ##number of slaves
 
SWAP.USER CMD_DEPTH 8 ##AXI command depth for read and write
 
SWAP.USER CMD_DEPTH 4 ##AXI master command depth for read and write
SWAP.USER SLV_DEPTH 8 ##AXI slave command depth for read and write
SWAP.USER DATA_BITS 64 ##AXI data bits
SWAP.USER ADDR_BITS 32 ##AXI address bits
 
/ic_dec.v
45,6 → 45,11
reg [SLV_BITS-1:0] MMX_ASLV;
reg MMX_AIDOK;
wire [DEC_MSB:DEC_LSB] MMX_AADDR_DEC;
 
 
assign MMX_AADDR_DEC = MMX_AADDR[DEC_MSB:DEC_LSB];
LOOP MX
always @(MMX_AADDR or MMX_AIDOK)
begin
52,7 → 57,7
case (MMX_AIDOK)
1'b1 : MMX_ASLV = SLV_BITS'd0;
ELSE TRUE(SLAVE_NUM==1)
case ({MMX_AIDOK, MMX_AADDR[DEC_MSB:DEC_LSB]})
case ({MMX_AIDOK, MMX_AADDR_DEC})
{1'b1, BIN(SX SLV_BITS)} : MMX_ASLV = SLV_BITS'dSX;
ENDIF TRUE(SLAVE_NUM==1)
default : MMX_ASLV = SLV_BITS'dSERR;

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