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URL https://opencores.org/ocsvn/robust_axi_fabric/robust_axi_fabric/trunk

Subversion Repositories robust_axi_fabric

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  • This comparison shows the changes necessary to convert path 
    /robust_axi_fabric/trunk
    from Rev 17 to Rev 18
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  •

Rev 17 → Rev 18

/run/robust_axi_fabric.pro File deleted
/run/run.bat
1,6 → 1,6
 
echo off
 
::..\..\..\robust.exe ../src/base/ic.v -od out -I ../src/gen -list list.txt -listpath -header -gui
::..\..\..\..\robust.exe ../src/base/ic.v -od out -I ../src/gen -list list.txt -listpath -header -gui
 
..\..\..\robust.exe robust_axi_fabric.pro -gui %1 %2 %3
..\..\..\..\robust.exe ../robust_axi_fabric.pro -gui %1 %2 %3
/run/run.sh
1,12 → 1,12
#!/bin/bash
 
../../../robust -null
../../../../robust -null
if [ $? -eq 0 ];then
ROBUST=../../../robust
ROBUST=../../../../robust
else
echo "RobustVerilog warning: GUI version not supported - using non-GUI version robust-lite"
ROBUST=../../../robust-lite
ROBUST=../../../../robust-lite
fi
 
#$ROBUST ../src/base/ic.v -od out -I ../src/gen -list list.txt -listpath -header -gui ${@}
$ROBUST robust_axi_fabric.pro -gui ${@}
#$ROBUST src/base/ic.v -od out -I ../src/gen -list list.txt -listpath -header -gui ${@}
$ROBUST ../robust_axi_fabric.pro -gui ${@}
/robust_axi_fabric.pro
0,0 → 1,14
PROJDIR = run
 
SRCFILE = ic.v
DEFFILE =
 
OUTDIR = out
 
INCDIR += ../src/base
INCDIR += ../src/gen
 
LIST = list.txt
+LISTPATH
 
+HEADER
/src/gen/prgen_fifo.v
1,36 → 1,40
<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
IFDEF STUB
OUTFILE prgen_fifo_stub.v
module prgen_fifo_stub(PORTS);
ELSE STUB
OUTFILE prgen_fifo.v
 
module prgen_fifo(PORTS);
 
ENDIF STUB
parameter WIDTH = 8;
parameter DEPTH_FULL = 8;
 
44,7 → 48,8
(DEPTH <= 32) ? 5 :
(DEPTH <= 64) ? 6 :
(DEPTH <= 128) ? 7 :
(DEPTH <= 256) ? 8 : 0; //0 is ilegal
(DEPTH <= 256) ? 8 :
(DEPTH <= 512) ? 9 : 0; //0 is ilegal
 
parameter LAST_LINE = DEPTH-1;
57,7 → 62,7
input pop;
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout;
//output next;
IF STUB output [DEPTH_BITS:0] fullness;
output empty;
output full;
67,9 → 72,9
wire fifo_push;
wire fifo_pop;
reg [DEPTH-1:0] fullness_in;
reg [DEPTH-1:0] fullness_out;
reg [DEPTH-1:0] fullness;
reg [DEPTH-1:0] full_mask_in;
reg [DEPTH-1:0] full_mask_out;
reg [DEPTH-1:0] full_mask;
reg [WIDTH-1:0] fifo [DEPTH-1:0];
wire fifo_empty;
wire next;
128,28 → 133,64
always @(/*AUTOSENSE*/fifo_push or ptr_in)
begin
fullness_in = {DEPTH{1'b0}};
fullness_in[ptr_in] = fifo_push;
full_mask_in = {DEPTH{1'b0}};
full_mask_in[ptr_in] = fifo_push;
end
always @(/*AUTOSENSE*/fifo_pop or ptr_out)
begin
fullness_out = {DEPTH{1'b0}};
fullness_out[ptr_out] = fifo_pop;
full_mask_out = {DEPTH{1'b0}};
full_mask_out[ptr_out] = fifo_pop;
end
always @(posedge clk or posedge reset)
if (reset)
fullness <= #FFD {DEPTH{1'b0}};
full_mask <= #FFD {DEPTH{1'b0}};
else if (fifo_push | fifo_pop)
fullness <= #FFD (fullness & (~fullness_out)) | fullness_in;
full_mask <= #FFD (full_mask & (~full_mask_out)) | full_mask_in;
 
 
assign next = |fullness;
assign next = |full_mask;
assign fifo_empty = ~next;
assign empty = fifo_empty & dout_empty;
assign full = SINGLE ? !dout_empty : &fullness;
assign full = SINGLE ? !dout_empty : &full_mask;
 
 
IFDEF STUB
reg [DEPTH_BITS:0] fullness;
always @(posedge clk or posedge reset)
if (reset)
fullness <= #FFD {DEPTH_BITS+1{1'b0}};
else if (push | pop)
fullness <= #FFD fullness + push - pop;
wire overflow = full & fifo_push & (~fifo_pop);
wire underflow = empty & fifo_pop & (~fifo_push);
always @(posedge overflow)
begin
#1;
if (overflow)
begin
$display("-E-%m - overflow.\tTime: %0d ns", $time);
#1000;
$finish;
end
end
always @(posedge underflow)
begin
#1;
if (underflow)
begin
$display("-E-%m - underflow.\tTime: %0d ns", $time);
#1000;
$finish;
end
end
ENDIF STUB
endmodule
 
 
/src/base/ic.v
33,9 → 33,11
ITER MX
ITER SX SLAVE_NUM ##external slave ports don't include decerr slave
 
##check all masters have IDs
VERIFY (GROUP_MMX_ID.NUM > 0) else Master MX does not have group for AXI IDs
VERIFY (GROUP_MMX_ID.NUM > 0) ##Master MX does not have group for AXI IDs
VERIFY(UNIQUE(GONCAT(GROUP_MMX_ID ,))) ##Master MX IDs are not unique
 
 
module PREFIX_ic (PORTS);
 
input clk;
/src/base/ic_registry_wr.v
139,7 → 139,7
LOOP SX
prgen_fifo #(MSTR_BITS, 32)
prgen_fifo #(MSTR_BITS, 32) //TBD SLV_DEPTH
master_fifo_SSX(
.clk(clk),
.reset(reset),
/src/base/def_ic.txt
27,7 → 27,7
//// ////
//////////////////////////////////////////////////////////////////##>
 
REQUIRE(1.3)
REQUIRE(1.4)
 
INCLUDE def_ic_static.txt
 
/src/base/def_ic_static.txt
26,8 → 26,7
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
 
##Static defines
SWAP.GLOBAL MODEL_NAME AXI interconnect fabric
 
SWAP MSTRS MASTER_NUM

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