OpenCores
URL https://opencores.org/ocsvn/robust_axi_fabric/robust_axi_fabric/trunk

Subversion Repositories robust_axi_fabric

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /robust_axi_fabric
    from Rev 15 to Rev 16
    ↔ Reverse comparison
  •

Rev 15 → Rev 16

/trunk/run/run.sh
1,3 → 1,11
#!/bin/bash
 
../../../robust ../src/base/ic.v -od out -I ../src/gen -list list.txt -listpath -header -gui ${@}
../../../robust -ver
if [ $? -eq 0 ];then
ROBUST=../../../robust
else
echo "RobustVerilog warning: GUI version not supported - using non-GUI version robust-lite"
ROBUST=../../../robust-lite
fi
 
$ROBUST ../src/base/ic.v -od out -I ../src/gen -list list.txt -listpath -header -gui ${@}
/trunk/src/base/ic.v
28,11 → 28,14
//////////////////////////////////////////////////////////////////##>
 
OUTFILE PREFIX_ic.v
INCLUDE def_ic.txt
INCLUDE def_ic.txt
 
ITER MX
 
ITER SX SLAVE_NUM ##external slave ports don't include decerr slave
 
##check all masters have IDs
VERIFY (GROUP_MMX_ID.NUM > 0) else Master MX does not have group for AXI IDs
module PREFIX_ic (PORTS);
 
input clk;
98,8 → 101,8
.MMX_AWGROUP_IC_AXI_CMD(MMX_AWGROUP_IC_AXI_CMD),
.MMX_WGROUP_IC_AXI_W(MMX_WGROUP_IC_AXI_W),
.SSX_WGROUP_IC_AXI_W(SSX_WGROUP_IC_AXI_W),
.SSX_AWVALID(SSX_AWVALID),
.SSX_AWREADY(SSX_AWREADY),
.SSX_AWVALID(SSX_AWVALID),
.SSX_AWREADY(SSX_AWREADY),
.SSX_AWMSTR(SSX_AWMSTR),
STOMP ,
);
/trunk/src/base/ic_registry_wr.v
32,10 → 32,6
ITER MX
ITER SX
 
LOOP MX
ITER MMX_IDX
ENDLOOP MX
module PREFIX_ic_registry_wr(PORTS);
 
45,82 → 41,78
 
port MMX_AWGROUP_IC_AXI_CMD;
input [ID_BITS-1:0] MMX_WID;
input [ID_BITS-1:0] MMX_WID;
input MMX_WVALID;
input MMX_WREADY;
input MMX_WLAST;
output [SLV_BITS-1:0] MMX_WSLV;
output [SLV_BITS-1:0] MMX_WSLV;
output MMX_WOK;
input SSX_AWVALID;
input SSX_AWREADY;
input [MSTR_BITS-1:0] SSX_AWMSTR;
input [MSTR_BITS-1:0] SSX_AWMSTR;
input SSX_WVALID;
input SSX_WREADY;
input SSX_WLAST;
wire AWmatch_MMX_IDMMX_IDX;
wire Wmatch_MMX_IDMMX_IDX;
wire AWmatch_MMX_IDGROUP_MMX_ID.IDX;
wire Wmatch_MMX_IDGROUP_MMX_ID.IDX;
 
wire cmd_push_MMX;
wire cmd_push_MMX_IDMMX_IDX;
wire cmd_push_MMX_IDGROUP_MMX_ID.IDX;
wire cmd_pop_MMX;
wire cmd_pop_MMX_IDMMX_IDX;
wire cmd_pop_MMX_IDGROUP_MMX_ID.IDX;
 
wire [SLV_BITS-1:0] slave_in_MMX_IDMMX_IDX;
wire [SLV_BITS-1:0] slave_out_MMX_IDMMX_IDX;
wire slave_empty_MMX_IDMMX_IDX;
wire slave_full_MMX_IDMMX_IDX;
wire [SLV_BITS-1:0] slave_in_MMX_IDGROUP_MMX_ID.IDX;
wire [SLV_BITS-1:0] slave_out_MMX_IDGROUP_MMX_ID.IDX;
wire slave_empty_MMX_IDGROUP_MMX_ID.IDX;
wire slave_full_MMX_IDGROUP_MMX_ID.IDX;
 
wire cmd_push_SSX;
wire cmd_pop_SSX;
wire [MSTR_BITS-1:0] master_in_SSX;
wire [MSTR_BITS-1:0] master_out_SSX;
wire [MSTR_BITS-1:0] master_in_SSX;
wire [MSTR_BITS-1:0] master_out_SSX;
wire master_empty_SSX;
wire master_full_SSX;
reg [SLV_BITS-1:0] MMX_WSLV;
reg [SLV_BITS-1:0] MMX_WSLV;
reg MMX_WOK;
 
assign AWmatch_MMX_IDMMX_IDX = MMX_AWID == ID_MMX_IDMMX_IDX;
assign AWmatch_MMX_IDGROUP_MMX_ID.IDX = MMX_AWID == ID_BITS'GROUP_MMX_ID;
assign Wmatch_MMX_IDMMX_IDX = MMX_WID == ID_MMX_IDMMX_IDX;
assign Wmatch_MMX_IDGROUP_MMX_ID.IDX = MMX_WID == ID_BITS'GROUP_MMX_ID;
assign cmd_push_MMX = MMX_AWVALID & MMX_AWREADY;
assign cmd_push_MMX_IDMMX_IDX = cmd_push_MMX & AWmatch_MMX_IDMMX_IDX;
assign cmd_push_MMX_IDGROUP_MMX_ID.IDX = cmd_push_MMX & AWmatch_MMX_IDGROUP_MMX_ID.IDX;
assign cmd_pop_MMX = MMX_WVALID & MMX_WREADY & MMX_WLAST;
assign cmd_pop_MMX_IDMMX_IDX = cmd_pop_MMX & Wmatch_MMX_IDMMX_IDX;
assign cmd_pop_MMX_IDGROUP_MMX_ID.IDX = cmd_pop_MMX & Wmatch_MMX_IDGROUP_MMX_ID.IDX;
 
assign cmd_push_SSX = SSX_AWVALID & SSX_AWREADY;
assign cmd_pop_SSX = SSX_WVALID & SSX_WREADY & SSX_WLAST;
assign master_in_SSX = SSX_AWMSTR;
assign slave_in_MMX_IDMMX_IDX = MMX_AWSLV;
assign slave_in_MMX_IDGROUP_MMX_ID.IDX = MMX_AWSLV;
 
LOOP MX
always @(MMX_WID
or slave_out_MMX_IDMMX_IDX
)
always @(*)
begin
case (MMX_WID)
ID_MMX_IDMMX_IDX : MMX_WSLV = slave_out_MMX_IDMMX_IDX;
ID_BITS'GROUP_MMX_ID : MMX_WSLV = slave_out_MMX_IDGROUP_MMX_ID.IDX;
default : MMX_WSLV = SERR;
endcase
end
 
always @(MMX_WSLV
or master_out_SSX
)
always @(*)
begin
case (MMX_WSLV)
'dSX : MMX_WOK = master_out_SSX == 'dMX;
SLV_BITS'dSX : MMX_WOK = master_out_SSX == MSTR_BITS'dMX;
default : MMX_WOK = 1'b0;
endcase
end
128,25 → 120,25
ENDLOOP MX
LOOP MX
LOOP MMX_IDX
LOOP IX GROUP_MMX_ID.NUM
prgen_fifo #(SLV_BITS, CMD_DEPTH)
slave_fifo_MMX_IDMMX_IDX(
.clk(clk),
.reset(reset),
.push(cmd_push_MMX_IDMMX_IDX),
.pop(cmd_pop_MMX_IDMMX_IDX),
.din(slave_in_MMX_IDMMX_IDX),
.dout(slave_out_MMX_IDMMX_IDX),
.empty(slave_empty_MMX_IDMMX_IDX),
.full(slave_full_MMX_IDMMX_IDX)
);
slave_fifo_MMX_IDIX(
.clk(clk),
.reset(reset),
.push(cmd_push_MMX_IDIX),
.pop(cmd_pop_MMX_IDIX),
.din(slave_in_MMX_IDIX),
.dout(slave_out_MMX_IDIX),
.empty(slave_empty_MMX_IDIX),
.full(slave_full_MMX_IDIX)
);
 
ENDLOOP MMX_IDX
ENDLOOP MX
ENDLOOP IX
ENDLOOP MX
 
LOOP SX
LOOP SX
prgen_fifo #(MSTR_BITS, 32)
master_fifo_SSX(
.clk(clk),
159,7 → 151,7
.full(master_full_SSX)
);
 
ENDLOOP SX
ENDLOOP SX
endmodule
 
/trunk/src/base/ic_wdata.v
27,6 → 27,7
//// ////
//////////////////////////////////////////////////////////////////##>
 
OUTFILE PREFIX_ic_wdata.v
 
ITER MX
/trunk/src/base/ic_registry_resp.v
31,11 → 31,6
 
ITER MX
ITER SX
 
LOOP MX
ITER MMX_IDX
ENDLOOP MX
 
module PREFIX_ic_registry_resp(PORTS);
51,66 → 46,56
output [MSTR_BITS-1:0] SSX_MSTR;
output SSX_OK;
 
 
wire Amatch_MMX_IDGROUP_MMX_ID.IDX;
wire Amatch_MMX_IDMMX_IDX;
wire match_SSX_MMX_IDMMX_IDX;
wire match_SSX_MMX_IDGROUP_MMX_ID.IDX;
wire no_Amatch_MMX;
wire cmd_push_MMX;
wire cmd_push_MMX_IDMMX_IDX;
wire cmd_push_MMX_IDGROUP_MMX_ID.IDX;
wire cmd_pop_SSX;
LOOP MX
wire cmd_pop_MMX_IDMMX_IDX;
ENDLOOP MX
wire cmd_pop_MMX_IDGROUP_MMX_ID.IDX;
 
wire [SLV_BITS-1:0] slave_in_MMX_IDMMX_IDX;
wire [SLV_BITS-1:0] slave_out_MMX_IDMMX_IDX;
wire slave_empty_MMX_IDMMX_IDX;
wire slave_full_MMX_IDMMX_IDX;
wire [SLV_BITS-1:0] slave_in_MMX_IDGROUP_MMX_ID.IDX;
wire [SLV_BITS-1:0] slave_out_MMX_IDGROUP_MMX_ID.IDX;
wire slave_empty_MMX_IDGROUP_MMX_ID.IDX;
wire slave_full_MMX_IDGROUP_MMX_ID.IDX;
 
reg [MSTR_BITS-1:0] ERR_MSTR_reg;
wire [MSTR_BITS-1:0] ERR_MSTR;
reg [MSTR_BITS-1:0] ERR_MSTR_reg;
wire [MSTR_BITS-1:0] ERR_MSTR;
reg [MSTR_BITS-1:0] SSX_MSTR;
reg SSX_OK;
reg [MSTR_BITS-1:0] SSX_MSTR;
reg SSX_OK;
 
assign Amatch_MMX_IDMMX_IDX = MMX_AID == ID_MMX_IDMMX_IDX;
assign Amatch_MMX_IDGROUP_MMX_ID.IDX = MMX_AID == ID_BITS'GROUP_MMX_ID;
assign match_SSX_MMX_IDMMX_IDX = SSX_ID == ID_MMX_IDMMX_IDX;
assign match_SSX_MMX_IDGROUP_MMX_ID.IDX = SSX_ID == ID_BITS'GROUP_MMX_ID;
 
assign cmd_push_MMX = MMX_AVALID & MMX_AREADY;
assign cmd_push_MMX_IDMMX_IDX = cmd_push_MMX & Amatch_MMX_IDMMX_IDX;
assign cmd_push_MMX_IDGROUP_MMX_ID.IDX = cmd_push_MMX & Amatch_MMX_IDGROUP_MMX_ID.IDX;
assign cmd_pop_SSX = SSX_VALID & SSX_READY & SSX_LAST;
LOOP MX
assign cmd_pop_MMX_IDMMX_IDX = CONCAT((cmd_pop_SSX & match_SSX_MMX_IDMMX_IDX) |);
ENDLOOP MX
assign slave_in_MMX_IDMMX_IDX = MMX_ASLV;
LOOP MX
assign cmd_pop_MMX_IDGROUP_MMX_ID.IDX = CONCAT((cmd_pop_SSX & match_SSX_MMX_IDGROUP_MMX_ID.IDX) |);
ENDLOOP MX
assign slave_in_MMX_IDGROUP_MMX_ID.IDX = MMX_ASLV;
 
 
 
 
IFDEF DEF_DECERR_SLV
LOOP MX
assign no_Amatch_MMX = CONCAT((~Amatch_MMX_IDMMX_IDX) &);
ENDLOOP MX
assign no_Amatch_MMX = GONCAT.REV((~Amatch_MMX_IDGROUP_MMX_ID.IDX) &);
 
always @(posedge clk or posedge reset)
if (reset)
ERR_MSTR_reg <= #FFD {MSTR_BITS{1'b0}};
LOOP MX
else if (cmd_push_MMX & no_Amatch_MMX)
ERR_MSTR_reg <= #FFD 'dMX;
ENDLOOP MX
else if (cmd_push_MMX & no_Amatch_MMX) ERR_MSTR_reg <= #FFD MSTR_BITS'dMX;
assign ERR_MSTR = ERR_MSTR_reg;
ELSE DEF_DECERR_SLV
119,12 → 104,10
LOOP SX
always @(SSX_ID or ERR_MSTR)
always @(*)
begin
case (SSX_ID)
LOOP MX
ID_MMX_IDMMX_IDX : SSX_MSTR = 'dMX;
ENDLOOP MX
ID_BITS'GROUP_MMX_ID : SSX_MSTR = MSTR_BITS'dMX;
default : SSX_MSTR = ERR_MSTR;
endcase
end
132,9 → 115,7
always @(*)
begin
case (SSX_ID)
LOOP MX
ID_MMX_IDMMX_IDX : SSX_OK = slave_out_MMX_IDMMX_IDX == 'dSX;
ENDLOOP MX
ID_BITS'GROUP_MMX_ID : SSX_OK = slave_out_MMX_IDGROUP_MMX_ID.IDX == SLV_BITS'dSX;
default : SSX_OK = 1'b1; //SLVERR
endcase
end
142,20 → 123,20
 
CREATE prgen_fifo.v DEFCMD(SWAP CONST(#FFD) #FFD)
LOOP MX
LOOP MMX_IDX
LOOP IX GROUP_MMX_ID.NUM
prgen_fifo #(SLV_BITS, CMD_DEPTH)
slave_fifo_MMX_IDMMX_IDX(
.clk(clk),
.reset(reset),
.push(cmd_push_MMX_IDMMX_IDX),
.pop(cmd_pop_MMX_IDMMX_IDX),
.din(slave_in_MMX_IDMMX_IDX),
.dout(slave_out_MMX_IDMMX_IDX),
.empty(slave_empty_MMX_IDMMX_IDX),
.full(slave_full_MMX_IDMMX_IDX)
);
slave_fifo_MMX_IDIX(
.clk(clk),
.reset(reset),
.push(cmd_push_MMX_IDIX),
.pop(cmd_pop_MMX_IDIX),
.din(slave_in_MMX_IDIX),
.dout(slave_out_MMX_IDIX),
.empty(slave_empty_MMX_IDIX),
.full(slave_full_MMX_IDIX)
);
ENDLOOP MMX_IDX
ENDLOOP IX
ENDLOOP MX
 
/trunk/src/base/def_ic.txt
27,9 → 27,11
//// ////
//////////////////////////////////////////////////////////////////##>
 
REQUIRE(1.3)
 
INCLUDE def_ic_static.txt
 
SWAP #FFD #1 ##flip-flop delay
SWAP #FFD #1 ##flip-flop delay
 
SWAP.USER PREFIX fabric_MASTER_NUM_SLAVE_NUM ##prefix for all module and file names
 
36,20 → 38,25
SWAP.USER MASTER_NUM 3 ##number of masters
SWAP.USER SLAVE_NUM 6 ##number of slaves
 
DEFINE.USER DEF_DECERR_SLV ##use interanl decode slave error
 
SWAP ID_BITS 3 ##AXI ID bits
LOOP M0_IDX 2 ##number of IDs for master 0
SWAP ID_M0_ID0 ID_BITS'b000 ##master 0 ID0
SWAP ID_M0_ID1 ID_BITS'b001 ##master 0 ID1
LOOP M1_IDX 1 ##number of IDs for master 1
SWAP ID_M1_ID0 ID_BITS'b011 ##master 1 ID0
LOOP M2_IDX 1 ##number of IDs for master 2
SWAP ID_M2_ID0 ID_BITS'b101 ##master 2 ID0
SWAP.USER CMD_DEPTH 8 ##AXI command depth for read and write
 
SWAP.USER DATA_BITS 64 ##AXI data bits
SWAP.USER ADDR_BITS 32 ##AXI address bits
 
DEFINE.USER DEF_DECERR_SLV ##use interanl decode slave error
SWAP.USER USER_BITS 4 ##AXI user bits
 
SWAP.USER ID_BITS 3 ##AXI ID bits
 
GROUP.USER M0_ID is { ##Supported AXI IDs for master 0
b000
b001
}
GROUP.USER M1_ID is { ##Supported AXI IDs for master
b011
}
GROUP.USER M2_ID is { ##Supported AXI IDs for master 2
b101
}
/trunk/src/base/ic_dec.v
32,10 → 32,6
ITER MX
ITER SX
 
LOOP MX
ITER MMX_IDX
ENDLOOP MX
module PREFIX_ic_dec (PORTS);
 
input [ADDR_BITS-1:0] MMX_AADDR;
49,17 → 45,17
reg [SLV_BITS-1:0] MMX_ASLV;
reg MMX_AIDOK;
LOOP MX
LOOP MX
always @(MMX_AADDR or MMX_AIDOK)
begin
IFDEF TRUE(SLAVE_NUM==1)
case (MMX_AIDOK)
1'b1 : MMX_ASLV = 'd0;
1'b1 : MMX_ASLV = SLV_BITS'd0;
ELSE TRUE(SLAVE_NUM==1)
case ({MMX_AIDOK, MMX_AADDR[DEC_MSB:DEC_LSB]})
{1'b1, BIN(SX SLV_BITS)} : MMX_ASLV = 'dSX;
{1'b1, BIN(SX SLV_BITS)} : MMX_ASLV = SLV_BITS'dSX;
ENDIF TRUE(SLAVE_NUM==1)
default : MMX_ASLV = 'dSERR;
default : MMX_ASLV = SLV_BITS'dSERR;
endcase
end
 
66,14 → 62,14
always @(MMX_AID)
begin
case (MMX_AID)
ID_MMX_IDMMX_IDX : MMX_AIDOK = 1'b1;
ID_BITS'GROUP_MMX_ID : MMX_AIDOK = 1'b1;
default : MMX_AIDOK = 1'b0;
endcase
end
ENDLOOP MX
ENDLOOP MX
endmodule
endmodule
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.