URL
https://opencores.org/ocsvn/robust_axi_fabric/robust_axi_fabric/trunk
Subversion Repositories robust_axi_fabric
Compare Revisions
- This comparison shows the changes necessary to convert path
/robust_axi_fabric
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/trunk/README.txt
2,6 → 2,10
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This code is a generic code written in RobustVerilog. In order to convert it to Verilog a RobustVerilog parser is required. |
It is possible to download a free RobustVerilog parser from www.provartec.com/edatools. |
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We will be very happy to receive any kind of feedback regarding our tools and cores. |
We will also be willing to support any company intending to integrate our cores into their project. |
For any questions / remarks / suggestions / bugs please contact info@provartec.com. |
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RobustVerilog generic AXI interconnect fabric |
14,7 → 18,6
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Changing the interconnect parameters should be made only in def_ic.txt in the src/base directory (changing master num, slave num etc.). |
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For any questions / remarks / suggestions / bugs please contact info@provartec.com. |
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