URL
https://opencores.org/ocsvn/rtf8088/rtf8088/trunk
Subversion Repositories rtf8088
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- This comparison shows the changes necessary to convert path
/rtf8088
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/trunk/rtl/verilog/ALU.v
73,6 → 73,19
wire ltu = a < b; |
wire lt = as < bs; |
|
wire [31:0] shlo = {16'h0000,b} << shftamt; |
wire [31:0] shruo = {b,16'h0000} >> shftamt; |
wire [15:0] shro = ~(~b >> shftamt); |
wire [32:0] shlco = {16'h0000,b,cf} << shftamt; |
wire [32:0] shrcuo = {cf,b,16'h0000} >> shftamt; |
|
wire [15:0] shlo8 = {8'h00,b[7:0]} << shftamt; |
wire [15:0] shruo8 = {b[7:0],8'h00} >> shftamt; |
wire [ 7:0] shro8 = ~(~b[7:0] >> shftamt); |
wire [16:0] shlco8 = {8'h00,b,cf} << shftamt; |
wire [16:0] shrcuo8 = {cf,b[7:0],8'h00} >> shftamt; |
|
|
always @(ir or ir2 or a or b or cf or af or al or ah or aldv10 or TTT) |
begin |
casex(ir) |
/trunk/rtl/verilog/rtf8088.v
27,7 → 27,7
// 650 ff's / 2 MULTs |
// |
// Webpack 14.3 xc6slx45 3-csg324 |
// 701 ff's 4115 LUTs / 90.261 MHz |
// 736 ff's 4433 LUTs / 90.360 MHz |
// ============================================================================ |
|
//`define BYTES_ONLY 1'b1 |
664,6 → 664,7
reg [2:0] cyc_type; // type of bus sycle |
reg w; // 0=8 bit, 1=16 bit |
reg d; |
reg v; // 1=count in cl, 0 = count is one |
reg [1:0] mod; |
reg [2:0] rrr; |
reg [2:0] rm; |
688,6 → 689,7
reg wrregs; |
reg wrsregs; |
wire take_br; |
reg [3:0] shftamt; |
|
reg nmi_armed; |
reg rst_nmi; // reset the nmi flag |
/trunk/rtl/verilog/EXECUTE.v
257,43 → 257,43
case(rrr) |
3'b000: // ROL |
begin |
res <= {b[14:0],b[15]}; |
res <= shlo[15:0]|shlo[31:16]; |
cf <= bmsb; |
vf <= bmsb^b[14]; |
end |
3'b001: // ROR |
begin |
res <= {b[0],b[15:1]}; |
res <= shruo[15:0]|shruo[31:16]; |
cf <= b[0]; |
vf <= cf^b[15]; |
end |
3'b010: // RCL |
begin |
res <= {b[14:0],cf}; |
res <= shlco[16:1]|shlco[32:17]; |
cf <= b[15]; |
vf <= b[15]^b[14]; |
end |
3'b011: // RCR |
begin |
res <= {cf,b[15:1]}; |
res <= shrcuo[15:0]|shrcuo[31:16]; |
cf <= b[0]; |
vf <= cf^b[15]; |
end |
3'b100: // SHL |
begin |
res <= {b[14:0],1'b0}; |
cf <= b[15]; |
res <= shlo[15:0]; |
cf <= shlo[16]; |
vf <= b[15]^b[14]; |
end |
3'b101: // SHR |
begin |
res <= {1'b0,b[15:1]}; |
cf <= b[0]; |
res <= shruo[31:16]; |
cf <= shruo[15]; |
vf <= b[15]; |
end |
3'b111: // SAR |
begin |
res <= {b[15],b[15:1]}; |
res <= shro; |
cf <= b[0]; |
vf <= 1'b0; |
end |
302,43 → 302,43
case(rrr) |
3'b000: // ROL |
begin |
res <= {b[6:0],b[7]}; |
res <= shlo8[7:0]|shlo8[15:8]; |
cf <= b[7]; |
vf <= b[7]^b[6]; |
end |
3'b001: // ROR |
begin |
res <= {b[0],b[7:1]}; |
res <= shruo8[15:8]|shruo8[7:0]; |
cf <= b[0]; |
vf <= cf^b[7]; |
end |
3'b010: // RCL |
begin |
res <= {b[6:0],cf}; |
res <= shlco8[8:1]|shlco8[16:9]; |
cf <= b[7]; |
vf <= b[7]^b[6]; |
end |
3'b011: // RCR |
begin |
res <= {cf,b[7:1]}; |
res <= shrcuo8[15:8]|shrcuo8[7:0]; |
cf <= b[0]; |
vf <= cf^b[7]; |
end |
3'b100: // SHL |
begin |
res <= {b[6:0],1'b0}; |
cf <= b[7]; |
res <= shlo8[7:0]; |
cf <= shlo8[8]; |
vf <= b[7]^b[6]; |
end |
3'b101: // SHR |
begin |
res <= {1'b0,b[7:1]}; |
cf <= b[0]; |
res <= shruo8[15:8]; |
cf <= shruo8[7]; |
vf <= b[7]; |
end |
3'b111: // SAR |
begin |
res <= {b[7],b[7:1]}; |
res <= shro8; |
cf <= b[0]; |
vf <= 1'b0; |
end |
/trunk/rtl/verilog/DECODE.v
273,6 → 273,8
|
default: |
begin |
if (v) shftamt <= cl[3:0]; |
else shftamt <= 4'd1; |
//----------------------------------------------------------------- |
// MOD/RM instructions |
//----------------------------------------------------------------- |
/trunk/rtl/verilog/IFETCH.v
94,6 → 94,7
// ir_ip <= dat_i; |
w <= dat_i[0]; |
d <= dat_i[1]; |
v <= dat_i[1]; |
sxi <= dat_i[1]; |
sreg2 <= dat_i[4:3]; |
sreg3 <= {1'b0,dat_i[4:3]}; |
/trunk/rtl/verilog/EACALC.v
134,6 → 134,11
res <= rmo; |
b <= rrro; |
end |
// shifts and rotates |
8'hD0,8'hD1,8'hD2,8'hD3: |
begin |
b <= rmo; |
end |
default: |
begin |
if (d) begin |