OpenCores
URL https://opencores.org/ocsvn/rtfsimpleuart/rtfsimpleuart/trunk

Subversion Repositories rtfsimpleuart

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 11 to Rev 12
    ↔ Reverse comparison
  •

Rev 11 → Rev 12

/rtfsimpleuart/trunk/rtl/verilog/rtfSimpleUartRx.v
91,6 → 91,7
//------------------------
input cs_i, // chip select
input baud16x_ce, // baud rate clock enable
input tri0 baud8x, // switches to mode baudX8
input clear, // clear reciever
input rxd, // external serial input
output reg data_present, // data present in fifo
98,8 → 99,11
output reg overrun // receiver overrun
);
 
//0 - simple sampling at middle of symbol period
//>0 - sampling of 3 middle ticks of sumbol perion and results as majority
parameter SamplerStyle = 0;
 
// variables
reg [3:0] rxdd; // synchronizer flops
reg [7:0] cnt; // sample bit rate counter
reg [9:0] rx_data; // working receive data register
reg state; // state machine
106,6 → 110,10
reg wf; // buffer write
reg [7:0] dat;
 
wire isX8;
buf(isX8, baud8x);
reg modeX8;
 
assign ack_o = cyc_i & stb_i & cs_i;
assign dat_o = ack_o ? dat : 8'b0;
 
117,20 → 125,42
// but set the status when the data register
// is updated by the receiver
always @(posedge clk_i)
if (wf) data_present <= 1;
if (rst_i)
data_present <= 0;
else if (wf)
data_present <= 1;
else if (ack_o & ~we_i) data_present <= 0;
 
 
// Three stage synchronizer to synchronize incoming data to
// the local clock (avoids metastability).
always @(posedge clk_i)
rxdd <= {rxdd[2:0],rxd};
reg [5:0] rxdd /* synthesis ramstyle = "logic" */; // synchronizer flops
reg rxdsmp; // majority samples
reg rdxstart; // for majority style sample solid 3tik-wide sample
reg [1:0] rxdsum;
always @(posedge clk_i) begin
rxdd <= {rxdd[4:0],rxd};
if (SamplerStyle == 0) begin
rxdsmp <= rxdd[3];
rdxstart <= rxdd[4]&~rxdd[3];
end
else begin
rxdsum[1] <= rxdsum[0];
rxdsum[0] <= {1'b0,rxdd[3]} + {1'b0,rxdd[4]} + {1'b0,rxdd[5]};
rxdsmp <= rxdsum[1];
rdxstart <= (rxdsum[1] == 2'b00) & ((rxdsum[1] == 2'b11));
end
end
 
`define CNT_FRAME (8'h97)
`define CNT_FINISH (8'h9D)
 
always @(posedge clk_i) begin
if (rst_i) begin
state <= `IDLE;
wf <= 1'b0;
overrun <= 1'b0;
frame_err <= 1'b0;
end
else begin
 
141,6 → 171,7
wf <= 1'b0;
state <= `IDLE;
overrun <= 1'b0;
frame_err <= 1'b0;
end
 
else if (baud16x_ce) begin
151,7 → 182,7
// detected.
`IDLE:
// look for start bit
if (~rxdd[3])
if (rdxstart)
state <= `CNT;
 
`CNT:
159,27 → 190,28
// End of the frame ?
// - check for framing error
// - write data to read buffer
if (cnt==8'h97)
if (cnt==`CNT_FRAME)
begin
frame_err <= ~rxdd[3];
frame_err <= ~rxdsmp;
overrun <= data_present;
if (!data_present)
wf <= 1'b1;
else
overrun <= 1'b1;
state <= `IDLE;
end
// Switch back to the idle state a little
// bit too soon.
if (cnt==8'h9D)
state <= `IDLE;
//if (cnt==`CNT_FINISH) begin
// state <= `IDLE;
//end
 
// On start bit check make sure the start
// bit is low, otherwise go back to the
// idle state because it's a false start.
if (cnt==8'h07 && rxdd[3])
if (cnt==8'h07 && rxdsmp)
state <= `IDLE;
 
if (cnt[3:0]==4'h7)
rx_data <= {rxdd[3],rx_data[9:1]};
rx_data <= {rxdsmp,rx_data[9:1]};
end
 
endcase
191,10 → 223,14
// bit rate counter
always @(posedge clk_i)
if (baud16x_ce) begin
if (state == `IDLE)
cnt <= 0;
else
cnt <= cnt + 1;
if (state == `IDLE) begin
cnt <= modeX8;
modeX8 <= isX8;
end
else begin
cnt[7:1] <= cnt[7:1] + cnt[0];
cnt[0] <= ~cnt[0] | (modeX8);
end
end
 
endmodule
/rtfsimpleuart/trunk/rtl/verilog/rtfSimpleUartTx.v
49,6 → 49,7
|Data transfer sequencing: Undefined
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|Clock frequency constraints: none
| Baud Generates by X16 or X8 CLK_I depends on baud8x pin
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|Supported signal list and Signal Name WISHBONE equiv.
|cross reference to equivalent ack_o ACK_O
81,9 → 82,11
//--------------------
input cs_i, // chip select
input baud16x_ce, // baud rate clock enable
input tri0 baud8x, // switches to mode baudX8
input cts, // clear to send
output txd, // external serial output
output reg empty // buffer is empty
output reg empty, // buffer is empty
output reg txc // tx complete flag
);
 
reg [9:0] tx_data; // transmit data working reg (raw)
91,6 → 94,10
reg [7:0] cnt; // baud clock counter
reg rd;
 
wire isX8;
buf(isX8, baud8x);
reg modeX8;
 
assign ack_o = cyc_i & stb_i & cs_i;
assign txd = tx_data[0];
 
105,12 → 112,14
else if (rd) empty <= 1;
end
 
 
`define CNT_FINISH (8'h9F)
always @(posedge clk_i)
if (rst_i) begin
cnt <= 8'h00;
cnt <= `CNT_FINISH;
rd <= 0;
tx_data <= 10'h3FF;
txc <= 1'b1;
modeX8 <= 1'b0;
end
else begin
 
118,19 → 127,26
 
if (baud16x_ce) begin
 
cnt <= cnt + 1;
// Load next data ?
if (cnt==8'h9F) begin
cnt <= 0;
if (cnt==`CNT_FINISH) begin
modeX8 <= isX8;
if (!empty && cts) begin
tx_data <= {1'b1,fdo,1'b0};
rd <= 1;
cnt <= modeX8;
txc <= 1'b0;
end
else
txc <= 1'b1;
end
// Shift the data out. LSB first.
else if (cnt[3:0]==4'hF)
tx_data <= {1'b1,tx_data[9:1]};
else begin
cnt[7:1] <= cnt[7:1] + cnt[0];
cnt[0] <= ~cnt[0] | (modeX8);
 
if (cnt[3:0]==4'hF)
tx_data <= {1'b1,tx_data[9:1]};
end
end
end
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.