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URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

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    from Rev 10 to Rev 11
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Rev 10 → Rev 11

/trunk/tools/opt/tracan/tracan.c
24,74 → 24,69
len = strlen(buf);
if(len==LEN_REQ && dir==CHAR_REQ) {
 
// Write details of request packet
printf("INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE ***\n");
if(bitsToInt(PCX_VLD,PCX_VLD)==1) printf("INFO: SPC2WBM: Request has valid bit\n");
else printf("INFO: SPC2WBM: Request has not valid bit\n");
switch(bitsToInt(PCX_RQ_HI,PCX_RQ_LO)) {
case LOAD_RQ: printf("INFO: SPC2WBM: Request of Type LOAD_RQ\n"); break;
case IMISS_RQ: printf("INFO: SPC2WBM: Request of Type IMISS_RQ\n"); break;
case STORE_RQ: printf("INFO: SPC2WBM: Request of Type STORE_RQ\n"); break;
case CAS1_RQ: printf("INFO: SPC2WBM: Request of Type CAS1_RQ\n"); break;
case CAS2_RQ: printf("INFO: SPC2WBM: Request of Type CAS2_RQ\n"); break;
case SWAP_RQ: printf("INFO: SPC2WBM: Request of Type SWAP_RQ\n"); break;
case STRLOAD_RQ: printf("INFO: SPC2WBM: Request of Type STRLOAD_RQ\n"); break;
case STRST_RQ: printf("INFO: SPC2WBM: Request of Type STRST_RQ\n"); break;
case STQ_RQ: printf("INFO: SPC2WBM: Request of Type STQ_RQ\n"); break;
case INT_RQ: printf("INFO: SPC2WBM: Request of Type INT_RQ\n"); break;
case FWD_RQ: printf("INFO: SPC2WBM: Request of Type FWD_RQ\n"); break;
case FWD_RPY: printf("INFO: SPC2WBM: Request of Type FWD_RPY\n"); break;
case RSVD_RQ: printf("INFO: SPC2WBM: Request of Type RSVD_RQ\n"); break;
default: printf("INFO: SPC2WBM: Request of Type Unknown\n");
if(bitsToInt(PCX_VLD,PCX_VLD)==0) printf("INFO: SPC2WBM: *** DIRTY REQUEST FROM SPARC CORE ***\n");
else {
 
// Write details of request packet
printf("INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE ***\n");
printf("INFO: SPC2WBM: Valid bit is %d\n",bitsToInt(PCX_VLD,PCX_VLD));
switch(bitsToInt(PCX_RQ_HI,PCX_RQ_LO)) {
case LOAD_RQ: printf("INFO: SPC2WBM: Request of Type LOAD_RQ\n"); break;
case IMISS_RQ: printf("INFO: SPC2WBM: Request of Type IMISS_RQ\n"); break;
case STORE_RQ: printf("INFO: SPC2WBM: Request of Type STORE_RQ\n"); break;
case CAS1_RQ: printf("INFO: SPC2WBM: Request of Type CAS1_RQ\n"); break;
case CAS2_RQ: printf("INFO: SPC2WBM: Request of Type CAS2_RQ\n"); break;
case SWAP_RQ: printf("INFO: SPC2WBM: Request of Type SWAP_RQ\n"); break;
case STRLOAD_RQ: printf("INFO: SPC2WBM: Request of Type STRLOAD_RQ\n"); break;
case STRST_RQ: printf("INFO: SPC2WBM: Request of Type STRST_RQ\n"); break;
case STQ_RQ: printf("INFO: SPC2WBM: Request of Type STQ_RQ\n"); break;
case INT_RQ: printf("INFO: SPC2WBM: Request of Type INT_RQ\n"); break;
case FWD_RQ: printf("INFO: SPC2WBM: Request of Type FWD_RQ\n"); break;
case FWD_RPY: printf("INFO: SPC2WBM: Request of Type FWD_RPY\n"); break;
case RSVD_RQ: printf("INFO: SPC2WBM: Request of Type RSVD_RQ\n"); break;
default: printf("INFO: SPC2WBM: Request of Type Unknown\n");
}
printf("INFO: SPC2WBM: Non-Cacheable bit is %d\n", bitsToInt(PCX_R,PCX_R));
printf("INFO: SPC2WBM: CPU ID is %0X\n", bitsToInt(PCX_CP_HI,PCX_CP_LO));
printf("INFO: SPC2WBM: Thread is %0X\n", bitsToInt(PCX_TH_HI,PCX_TH_LO));
printf("INFO: SPC2WBM: Invalidate All is %0X\n", bitsToInt(PCX_INVALL,PCX_INVALL));
printf("INFO: SPC2WBM: Replaced L1 Way is %0X\n", bitsToInt(PCX_WY_HI,PCX_WY_LO));
switch(bitsToInt(PCX_SZ_HI,PCX_SZ_LO)) {
case PCX_SZ_1B: printf("INFO: SPC2WBM: Request size is 1 Byte\n"); break;
case PCX_SZ_2B: printf("INFO: SPC2WBM: Request size is 2 Bytes\n"); break;
case PCX_SZ_4B: printf("INFO: SPC2WBM: Request size is 4 Bytes\n"); break;
case PCX_SZ_8B: printf("INFO: SPC2WBM: Request size is 8 Bytes\n"); break;
case PCX_SZ_16B: printf("INFO: SPC2WBM: Request size is 16 Bytes\n"); break;
default: printf("INFO: SPC2WBM: Request size is Unknown\n");
}
printf("INFO: SPC2WBM: Address is %05X%05X\n", bitsToInt(PCX_AD_HI,PCX_AD_HI-19), bitsToInt(PCX_AD_HI-20,PCX_AD_LO));
printf("INFO: SPC2WBM: Data is %08X%08X\n", bitsToInt(PCX_DA_HI,PCX_DA_HI-31), bitsToInt(PCX_DA_HI-32,PCX_DA_LO));
printf("INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master\n");
}
if(bitsToInt(PCX_RQ_HI,PCX_RQ_LO)==IMISS_RQ) {
if(bitsToInt(PCX_R,PCX_R)==1) printf("INFO: SPC2WBM: Request is Non-Cacheable\n");
else printf("INFO: SPC2WBM: Request is Cacheable\n");
} else {
if(bitsToInt(PCX_R,PCX_R)==1) printf("INFO: SPC2WBM: Request is a Read Access\n");
else printf("INFO: SPC2WBM: Request is a Write Access\n");
}
printf("INFO: SPC2WBM: CPU ID is %0X\n", bitsToInt(PCX_CP_HI,PCX_CP_LO));
printf("INFO: SPC2WBM: Thread is %0X\n", bitsToInt(PCX_TH_HI,PCX_TH_LO));
printf("INFO: SPC2WBM: Buffer is %0X\n", bitsToInt(PCX_BF_HI,PCX_BF_LO));
printf("INFO: SPC2WBM: Packet ID is %0X\n", bitsToInt(PCX_P_HI,PCX_P_LO));
switch(bitsToInt(PCX_SZ_HI,PCX_SZ_LO)) {
case PCX_SZ_1B: printf("INFO: SPC2WBM: Request size is 1 Byte\n"); break;
case PCX_SZ_2B: printf("INFO: SPC2WBM: Request size is 2 Bytes\n"); break;
case PCX_SZ_4B: printf("INFO: SPC2WBM: Request size is 4 Bytes\n"); break;
case PCX_SZ_8B: printf("INFO: SPC2WBM: Request size is 8 Bytes\n"); break;
case PCX_SZ_16B: printf("INFO: SPC2WBM: Request size is 16 Bytes\n"); break;
default: printf("INFO: SPC2WBM: Request size is Unknown\n");
}
printf("INFO: SPC2WBM: Error is %0X\n", bitsToInt(PCX_ERR_HI,PCX_ERR_LO));
printf("INFO: SPC2WBM: Address is %05X%05X\n", bitsToInt(PCX_AD_HI,PCX_AD_HI-19), bitsToInt(PCX_AD_HI-20,PCX_AD_LO));
printf("INFO: SPC2WBM: Data is %08X%08X\n", bitsToInt(PCX_DA_HI,PCX_DA_HI-31), bitsToInt(PCX_DA_HI-32,PCX_DA_LO));
printf("INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master\n");
 
} else if(len==LEN_RET && dir==CHAR_RET) {
 
// Write details of return packet
printf("INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE ***\n");
if(bitsToInt(CPX_VLD,CPX_VLD)==1) printf("INFO: WBM2SPC: Return packet has valid bit\n");
else printf("INFO: WBM2SPC: Return packet has not valid bit\n");
switch(bitsToInt(CPX_RQ_HI,CPX_RQ_LO)) {
case IFILL_RET: printf("INFO: WBM2SPC: Return Packet of Type IFILL_RET\n"); break;
case LOAD_RET: printf("INFO: WBM2SPC: Return Packet of Type LOAD_RET\n"); break;
case ST_ACK: printf("INFO: WBM2SPC: Return Packet of Type ST_ACK\n"); break;
default: printf("INFO: WBM2SPC: Return Packet of Type Unknown\n");
if(bitsToInt(CPX_VLD,CPX_VLD)==0) printf("INFO: WBM2SPC: *** DIRTY PACKET TO SPARC CORE ***\n");
else {
 
// Write details of return packet
printf("INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE ***\n");
printf("INFO: WBM2SPC: Valid bit is %d\n", bitsToInt(CPX_VLD,CPX_VLD));
switch(bitsToInt(CPX_RQ_HI,CPX_RQ_LO)) {
case IFILL_RET: printf("INFO: WBM2SPC: Return Packet of Type IFILL_RET\n"); break;
case LOAD_RET: printf("INFO: WBM2SPC: Return Packet of Type LOAD_RET\n"); break;
case ST_ACK: printf("INFO: WBM2SPC: Return Packet of Type ST_ACK\n"); break;
default: printf("INFO: WBM2SPC: Return Packet of Type Unknown\n");
}
printf("INFO: WBM2SPC: Error is %0X\n", bitsToInt(CPX_ERR_HI,CPX_ERR_LO));
printf("INFO: WBM2SPC: Non-Cacheable bit is %d\n", bitsToInt(CPX_R,CPX_R));
printf("INFO: WBM2SPC: Thread is %0X\n", bitsToInt(CPX_TH_HI,CPX_TH_LO));
printf("INFO: WBM2SPC: Way Valid is %0X\n", bitsToInt(CPX_WYVLD,CPX_WYVLD));
printf("INFO: WBM2SPC: Replaced L2 Way is %0X\n", bitsToInt(CPX_WY_HI,CPX_WY_LO));
printf("INFO: WBM2SPC: Data is %08X%08X%08X%08X\n", bitsToInt(CPX_DA_HI,CPX_DA_HI-31), bitsToInt(CPX_DA_HI-32,CPX_DA_HI-63), bitsToInt(CPX_DA_HI-64,CPX_DA_HI-95), bitsToInt(CPX_DA_HI-96,CPX_DA_LO));
printf("INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core\n");
}
if(bitsToInt(CPX_RQ_HI,CPX_RQ_LO)==IFILL_RET) {
if(bitsToInt(CPX_R,CPX_R)==1) printf("INFO: WBM2SPC: Return Packet is Non-Cacheable\n");
else printf("INFO: WBM2SPC: Return Packet is Cacheable\n");
} else {
if(bitsToInt(CPX_R,CPX_R)==1) printf("INFO: WBM2SPC: Return Packet is a Read Access\n");
else printf("INFO: WBM2SPC: Return Packet is a Write Access\n");
}
printf("INFO: WBM2SPC: Thread is %0X\n", bitsToInt(CPX_TH_HI,CPX_TH_LO));
printf("INFO: WBM2SPC: Packet ID is %0X\n", bitsToInt(CPX_P_HI,CPX_P_LO));
printf("INFO: WBM2SPC: Error is %0X\n", bitsToInt(CPX_ERR_HI,CPX_ERR_LO));
printf("INFO: WBM2SPC: Data is %08X%08X%08X%08X\n", bitsToInt(CPX_DA_HI,CPX_DA_HI-31), bitsToInt(CPX_DA_HI-32,CPX_DA_HI-63), bitsToInt(CPX_DA_HI-64,CPX_DA_HI-95), bitsToInt(CPX_DA_HI-96,CPX_DA_LO));
printf("INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core\n");
 
} else {
printf("PACKET DIRECTION UNKNOWN!!!\n");
}
/trunk/hdl/rtl/s1_top/spc2wbm.v
40,7 → 40,7
// System inputs
input sys_clock_i; // System Clock
input sys_reset_i; // System Reset
input[5:0] sys_interrupt_source_i; // Interrupt Requests
input[5:0] sys_interrupt_source_i; // Encoded Interrupt Source
 
// SPARC-side inputs connected to the PCX (Processor-to-Cache Xbar) outputs of the SPARC Core
input[4:0] spc_req_i; // Request
93,16 → 93,15
reg wbm2spc_valid; // Valid
reg[(`CPX_RQ_HI-`CPX_RQ_LO):0] wbm2spc_type; // Request type
reg[(`CPX_ERR_HI-`CPX_ERR_LO):0] wbm2spc_error; // Error
reg wbm2spc_rnwd_or_ncif; // Read-Not-Write Data or Non-Cacheable Instruction Fetch
reg wbm2spc_nc; // Non-Cacheable
reg[(`CPX_TH_HI-`CPX_TH_LO):0] wbm2spc_thread; // Thread
reg[(`CPX_P_HI-`CPX_P_LO):0] wbm2spc_packet_id; // Packet ID
reg wbm2spc_way_valid; // L2 Way Valid
reg[(`CPX_WY_HI-`CPX_WY_LO):0] wbm2spc_way; // Replaced L2 Way
reg[(`CPX_DA_HI-`CPX_DA_LO):0] wbm2spc_data; // Load Data
reg[(`CPX_IN_HI-`CPX_IN_LO):0] wbm2spc_interrupt_source; // Interrupt Source
reg wbm2spc_reset_not_int; // Reset and not interrupt packet
reg[4:0] wbm2spc_virtual_cpu_target; // ID of virtual CPU target
reg[(`CPX_IN_HI-`CPX_IN_LO):0] wbm2spc_intsrc_or_resettype; // Interrupt Source or Reset Type
reg[(`CPX_IN_HI-`CPX_IN_LO):0] wbm2spc_new_irq; // New Interrupt Request Pending
 
reg[6:0] wbm2spc_interrupt_source; // Encoded Interrupt Source
reg wbm2spc_interrupt_new; // New Interrupt Pending
/*
* Wires
*/
111,19 → 110,17
wire spc2wbm_req; // Request
wire spc2wbm_valid; // Valid
wire[(`PCX_RQ_HI-`PCX_RQ_LO):0] spc2wbm_type; // Request type
wire spc2wbm_rnwd_or_ncif; // Read-Not-Write Data or Non-Cacheable Instruction Fetch
wire spc2wbm_nc; // Non-Cacheable
wire[(`PCX_CP_HI-`PCX_CP_LO):0] spc2wbm_cpu_id; // CPU ID
wire[(`PCX_TH_HI-`PCX_TH_LO):0] spc2wbm_thread; // Thread
wire[(`PCX_BF_HI-`PCX_BF_LO):0] spc2wbm_buffer; // Buffer
wire[(`PCX_P_HI-`PCX_P_LO):0] spc2wbm_packet_id; // Packet ID
wire spc2wbm_invalidate; // Invalidate all
wire[(`PCX_WY_HI-`PCX_WY_LO):0] spc2wbm_way; // Replaced L1 Way
wire[(`PCX_SZ_HI-`PCX_SZ_LO):0] spc2wbm_size; // Load/Store size
wire[(`PCX_ERR_HI-`PCX_ERR_LO):0] spc2wbm_error; // Error
wire[(`PCX_AD_HI-`PCX_AD_LO):0] spc2wbm_addr; // Address
wire[(`PCX_DA_HI-`PCX_DA_LO):0] spc2wbm_data; // Store Data
 
// Return packets assembled with various fields
wire[`CPX_WIDTH-1:0] wbm2spc_packet_dat; // Incoming Packet - Data
wire[`CPX_WIDTH-1:0] wbm2spc_packet_int; // Incoming Packet - Interrupt
wire[`CPX_WIDTH-1:0] wbm2spc_packet; // Incoming Packet
 
/*
* Encode/decode incoming info
151,24 → 148,18
assign spc2wbm_req = ( spc_req_i[4] | spc_req_i[3] | spc_req_i[2] | spc_req_i[1] | spc_req_i[0] );
assign spc2wbm_valid = spc2wbm_packet[`PCX_VLD];
assign spc2wbm_type = spc2wbm_packet[`PCX_RQ_HI:`PCX_RQ_LO];
assign spc2wbm_rnwd_or_ncif = spc2wbm_packet[`PCX_R];
assign spc2wbm_nc = spc2wbm_packet[`PCX_NC];
assign spc2wbm_cpu_id = spc2wbm_packet[`PCX_CP_HI:`PCX_CP_LO];
assign spc2wbm_thread = spc2wbm_packet[`PCX_TH_HI:`PCX_TH_LO];
assign spc2wbm_buffer = spc2wbm_packet[`PCX_BF_HI:`PCX_BF_LO];
assign spc2wbm_packet_id = spc2wbm_packet[`PCX_P_HI:`PCX_P_LO];
assign spc2wbm_invalidate = spc2wbm_packet[`PCX_INVALL];
assign spc2wbm_way = spc2wbm_packet[`PCX_WY_HI:`PCX_WY_LO];
assign spc2wbm_size = spc2wbm_packet[`PCX_SZ_HI:`PCX_SZ_LO];
assign spc2wbm_error = spc2wbm_packet[`PCX_ERR_HI:`PCX_ERR_LO];
assign spc2wbm_addr = spc2wbm_packet[`PCX_AD_HI:`PCX_AD_LO];
assign spc2wbm_data = spc2wbm_packet[`PCX_DA_HI:`PCX_DA_LO];
 
// Encode info going to the SPC side assembling return packets
assign wbm2spc_packet_dat = { wbm2spc_valid, wbm2spc_type, wbm2spc_error,
wbm2spc_rnwd_or_ncif, wbm2spc_thread, 2'b00, wbm2spc_packet_id,
2'b00, wbm2spc_data };
assign wbm2spc_packet_int = { wbm2spc_valid, wbm2spc_type, wbm2spc_error,
wbm2spc_rnwd_or_ncif, wbm2spc_thread, wbm2spc_interrupt_source,
111'b0, wbm2spc_reset_not_int, 3'b0, wbm2spc_virtual_cpu_target,
2'b0, wbm2spc_intsrc_or_resettype };
assign wbm2spc_packet = { wbm2spc_valid, wbm2spc_type, wbm2spc_error, wbm2spc_nc,
wbm2spc_thread, wbm2spc_way_valid, wbm2spc_way, 3'b100, wbm2spc_data };
 
/*
* State Machine
198,14 → 189,11
wbm2spc_valid = 1;
wbm2spc_type = `INT_RET;
wbm2spc_error = 0;
wbm2spc_rnwd_or_ncif = 0;
wbm2spc_nc = 0;
wbm2spc_thread = 0;
wbm2spc_packet_id = 0;
wbm2spc_interrupt_source = 0;
wbm2spc_reset_not_int = 1;
wbm2spc_virtual_cpu_target = 0;
wbm2spc_intsrc_or_resettype = 6'b000001;
wbm2spc_new_irq = 0; // Ignored for wakeup packet
wbm2spc_way_valid = 0;
wbm2spc_way = 0;
wbm2spc_data = 64'h10001;
 
// Clear state machine
state = `STATE_WAKEUP;
218,7 → 206,7
 
// Send wakeup packet
spc_ready_o = 1;
spc_packetin_o = wbm2spc_packet_int;
spc_packetin_o = wbm2spc_packet;
 
// synopsys translate_off
// Display comment
255,32 → 243,29
end else if(sys_interrupt_source_i!=wbm2spc_interrupt_source) begin
 
// Set the flag for next cycle
wbm2spc_new_irq = 1;
wbm2spc_interrupt_new = 1;
 
// Prepare the interrupt packet for the SPARC Core
wbm2spc_valid = 1;
wbm2spc_type = `INT_RET;
wbm2spc_error = 0;
wbm2spc_rnwd_or_ncif = 0;
wbm2spc_nc = 0;
wbm2spc_thread = 0;
wbm2spc_packet_id = 0;
wbm2spc_interrupt_source = sys_interrupt_source_i;
wbm2spc_reset_not_int = 0;
wbm2spc_virtual_cpu_target = 0;
wbm2spc_intsrc_or_resettype = sys_interrupt_source_i;
wbm2spc_way_valid = 0;
wbm2spc_way = 0;
 
// Stall other requests from the SPARC Core
spc_stallreq_o = 1;
 
// Next cycle see if there's an int to be forwarded to the Core
end else if(wbm2spc_interrupt_source!=6'b000000 && wbm2spc_new_irq) begin
end else if(wbm2spc_interrupt_source!=6'b000000 && wbm2spc_interrupt_new) begin
 
// Clean the flag
wbm2spc_new_irq = 0;
wbm2spc_interrupt_new = 0;
 
// Send the interrupt packet to the Core
spc_ready_o = 1;
spc_packetin_o = wbm2spc_packet_int;
spc_packetin_o = wbm2spc_packet;
 
// Stall other requests from the SPARC Core
spc_stallreq_o = 1;
356,10 → 341,23
// For accesses to RAM 256 bits are expected (2 ret packets)
wbm_sel_o = 8'b11111111;
 
end else begin
end else if(spc2wbm_type==`LOAD_RQ) begin
// For data load use the provided data
wbm_we_o = 0;
case(spc2wbm_size)
`PCX_SZ_1B: wbm_sel_o = (1'b1<<spc2wbm_addr[2:0]);
`PCX_SZ_2B: wbm_sel_o = (2'b11<<(spc2wbm_addr[2:1]<<1));
`PCX_SZ_4B: wbm_sel_o = (4'b1111<<(spc2wbm_addr[2]<<2));
`PCX_SZ_8B: wbm_sel_o = 8'b11111111;
`PCX_SZ_16B: wbm_sel_o = 8'b11111111; // Requires a 2nd access
default: wbm_sel_o = 8'b00000000;
endcase
 
// For data load/store use the provided data
wbm_we_o = !spc2wbm_rnwd_or_ncif;
end else if(spc2wbm_type==`STORE_RQ) begin
 
// For data store use the provided data
wbm_we_o = 1;
case(spc2wbm_size)
`PCX_SZ_1B: wbm_sel_o = (1'b1<<spc2wbm_addr[2:0]);
`PCX_SZ_2B: wbm_sel_o = (2'b11<<(spc2wbm_addr[2:1]<<1));
369,12 → 367,16
default: wbm_sel_o = 8'b00000000;
endcase
 
end else begin
 
wbm_we_o = 1;
wbm_sel_o = 8'b00000000;
 
end
 
// synopsys translate_off
// Print details of request packet
if(spc2wbm_valid==1) $display("INFO: SPC2WBM: Request has valid bit");
else $display("INFO: SPC2WBM: Request has not valid bit");
$display("INFO: SPC2WBM: Valid bit is %X", spc2wbm_valid);
case(spc2wbm_type)
`LOAD_RQ: $display("INFO: SPC2WBM: Request of Type LOAD_RQ");
`IMISS_RQ: $display("INFO: SPC2WBM: Request of Type IMISS_RQ");
390,18 → 392,12
`FWD_RPY: $display("INFO: SPC2WBM: Request of Type FWD_RPY");
`RSVD_RQ: $display("INFO: SPC2WBM: Request of Type RSVD_RQ");
default: $display("INFO: SPC2WBM: Request of Type Unknown");
endcase
if(spc2wbm_type==`IMISS_RQ) begin
if(spc2wbm_rnwd_or_ncif==1) $display("INFO: SPC2WBM: Request is Non-Cacheable");
else $display("INFO: SPC2WBM: Request is Cacheable");
end else begin
if(spc2wbm_rnwd_or_ncif==1) $display("INFO: SPC2WBM: Request is a Read Access");
else $display("INFO: SPC2WBM: Request is a Write Access");
end
$display("INFO: SPC2WBM: CPU ID is %X", spc2wbm_cpu_id);
endcase
$display("INFO: SPC2WBM: Non-Cacheable is %X", spc2wbm_nc);
$display("INFO: SPC2WBM: CPU-ID is %X", spc2wbm_cpu_id);
$display("INFO: SPC2WBM: Thread is %X", spc2wbm_thread);
$display("INFO: SPC2WBM: Buffer is %X", spc2wbm_buffer);
$display("INFO: SPC2WBM: Packet ID is %X", spc2wbm_packet_id);
$display("INFO: SPC2WBM: Invalidate All is %X", spc2wbm_invalidate);
$display("INFO: SPC2WBM: Replaced L1 Way is %X", spc2wbm_way);
case(spc2wbm_size)
`PCX_SZ_1B: $display("INFO: SPC2WBM: Request size is 1 Byte");
`PCX_SZ_2B: $display("INFO: SPC2WBM: Request size is 2 Bytes");
410,7 → 406,6
`PCX_SZ_16B: $display("INFO: SPC2WBM: Request size is 16 Bytes");
default: $display("INFO: SPC2WBM: Request size is Unknown");
endcase
$display("INFO: SPC2WBM: Error is %X", spc2wbm_error);
$display("INFO: SPC2WBM: Address is %X", spc2wbm_addr);
$display("INFO: SPC2WBM: Data is %X", spc2wbm_data);
$display("INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master");
436,17 → 431,12
 
// Latch the data and set up the return packet for the SPARC Core
wbm2spc_valid = 1;
wbm2spc_rnwd_or_ncif = spc2wbm_rnwd_or_ncif;
if(spc2wbm_addr[3]==0)
wbm2spc_data = { wbm_data_i, 64'b0 };
else
wbm2spc_data = { 64'b0, wbm_data_i };
case(spc2wbm_type)
`IMISS_RQ: begin
wbm2spc_type = `IFILL_RET; // I-Cache Miss
end
`LOAD_RQ: begin
wbm2spc_type = `LOAD_RET; // Load
wbm2spc_type = `LOAD_RET; // Load
end
`STORE_RQ: begin
wbm2spc_type = `ST_ACK; // Store
453,11 → 443,12
end
endcase
wbm2spc_error = 0;
wbm2spc_nc = spc2wbm_nc;
wbm2spc_thread = spc2wbm_thread;
// CHECK THIS!!!!!!!
// wbm2spc_packet_id = spc2wbm_packet_id;
if(spc2wbm_region==5'b10000) wbm2spc_packet_id = 2'b01;
else wbm2spc_packet_id = 2'b00;
wbm2spc_way_valid = 0;
wbm2spc_way = 0;
if(spc2wbm_addr[3]==0) wbm2spc_data = { wbm_data_i, 64'b0 };
else wbm2spc_data = { 64'b0, wbm_data_i };
 
// See if other 64-bit Wishbone accesses are required
if(
520,7 → 511,7
 
// Return the packet to the SPARC Core
spc_ready_o = 1;
spc_packetin_o = wbm2spc_packet_dat;
spc_packetin_o = wbm2spc_packet;
 
// Issue a third request on the Wishbone bus
wbm_cycle_o = 1;
532,8 → 523,7
 
// synopsys translate_off
// Print details of return packet
if(wbm2spc_valid==1) $display("INFO: WBM2SPC: Return packet has valid bit");
else $display("INFO: WBM2SPC: Return packet has not valid bit");
$display("INFO: WBM2SPC: Return packet has valid bit %X", wbm2spc_valid);
case(wbm2spc_type)
`IFILL_RET: $display("INFO: WBM2SPC: Return Packet of Type IFILL_RET");
`LOAD_RET: $display("INFO: WBM2SPC: Return Packet of Type LOAD_RET");
540,16 → 530,11
`ST_ACK: $display("INFO: WBM2SPC: Return Packet of Type ST_ACK");
default: $display("INFO: WBM2SPC: Return Packet of Type Unknown");
endcase
if(wbm2spc_type==`IFILL_RET) begin
if(wbm2spc_rnwd_or_ncif==1) $display("INFO: WBM2SPC: Return Packet is Non-Cacheable");
else $display("INFO: WBM2SPC: Return Packet is Cacheable");
end else begin
if(spc2wbm_rnwd_or_ncif==1) $display("INFO: WBM2SPC: Return Packet is a Read Access");
else $display("INFO: WBM2SPC: Return Packet is a Write Access");
end
$display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
$display("INFO: WBM2SPC: Non-Cacheable is %X", wbm2spc_nc);
$display("INFO: WBM2SPC: Thread is %X", wbm2spc_thread);
$display("INFO: WBM2SPC: Packet ID is %X", wbm2spc_packet_id);
$display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
$display("INFO: WBM2SPC: Way Valid is %X", wbm2spc_way_valid);
$display("INFO: WBM2SPC: Replaced L2 Way is %X", wbm2spc_way);
$display("INFO: WBM2SPC: Data is %X", wbm2spc_data);
$display("INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core");
// synopsys translate_on
627,7 → 612,7
 
// Return the packet to the SPARC Core
spc_ready_o = 1;
spc_packetin_o = wbm2spc_packet_dat;
spc_packetin_o = wbm2spc_packet;
 
// Unconditional state change
state = `STATE_IDLE;
634,8 → 619,7
 
// synopsys translate_off
// Print details of return packet
if(wbm2spc_valid==1) $display("INFO: WBM2SPC: Return packet has valid bit");
else $display("INFO: WBM2SPC: Return packet has not valid bit");
$display("INFO: WBM2SPC: Valid bit is %X", wbm2spc_valid);
case(wbm2spc_type)
`IFILL_RET: $display("INFO: WBM2SPC: Return Packet of Type IFILL_RET");
`LOAD_RET: $display("INFO: WBM2SPC: Return Packet of Type LOAD_RET");
642,16 → 626,11
`ST_ACK: $display("INFO: WBM2SPC: Return Packet of Type ST_ACK");
default: $display("INFO: WBM2SPC: Return Packet of Type Unknown");
endcase
if(wbm2spc_type==`IFILL_RET) begin
if(wbm2spc_rnwd_or_ncif==1) $display("INFO: WBM2SPC: Return Packet is Non-Cacheable");
else $display("INFO: WBM2SPC: Return Packet is Cacheable");
end else begin
if(spc2wbm_rnwd_or_ncif==1) $display("INFO: WBM2SPC: Return Packet is a Read Access");
else $display("INFO: WBM2SPC: Return Packet is a Write Access");
end
$display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
$display("INFO: WBM2SPC: Non-Cacheable bit is %X", wbm2spc_nc);
$display("INFO: WBM2SPC: Thread is %X", wbm2spc_thread);
$display("INFO: WBM2SPC: Packet ID is %X", wbm2spc_packet_id);
$display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
$display("INFO: WBM2SPC: Way Valid is %X", wbm2spc_way_valid);
$display("INFO: WBM2SPC: Replaced L2 Way is %X", wbm2spc_way);
$display("INFO: WBM2SPC: Data is %X", wbm2spc_data);
$display("INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core");
// synopsys translate_on

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