URL
https://opencores.org/ocsvn/s1_core/s1_core/trunk
Subversion Repositories s1_core
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- This comparison shows the changes necessary to convert path
/
- from Rev 56 to Rev 57
- ↔ Reverse comparison
Rev 56 → Rev 57
/trunk/hdl/behav/testbench/mem_harness.v
70,6 → 70,7
integer i; // Index |
|
// Initialization |
`ifdef DEBUG |
initial begin |
$display("INFO: MEMH %m: Memory Harness with Wishbone Slave interface starting..."); |
$display("INFO: MEMH %m: %0d Address Bits / %0d Doublewords / %0d Bytes Total Memory", addr_bits, addr_max+1, (addr_max+1)*8); |
77,6 → 78,7
$readmemh(memfilename, mem); |
$display("INFO: MEMH %m: Memory initialization completed"); |
end |
`endif |
|
// Assignments |
assign tmp_rd = mem[wbs_addr_i[addr_bits+2:3]]; |
102,7 → 104,9
wbs_data_o = tmp_rd; |
|
// Write a comment |
`ifdef DEBUG |
if(wbs_sel_i) $display("INFO: MEMH %m: R @ %t ns, AD=%X SEL=%X DAT=%X", $time, wbs_addr_i, wbs_sel_i, wbs_data_o); |
`endif |
|
// Write cycle |
end else if(wbs_cycle_i & wbs_strobe_i & wbs_we_i) begin |
117,7 → 121,9
mem[wbs_addr_i[addr_bits+2:3]] = tmp_wd; |
|
// Write a comment |
`ifdef DEBUG |
if(wbs_sel_i) $display("INFO: MEMH %m: W @ %t ns, AD=%X SEL=%X DAT=%X", $time, wbs_addr_i, wbs_sel_i, tmp_wd); |
`endif |
|
// No read/write cycle |
end else begin |