OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

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Rev 4 → Rev 3

/s6soc/trunk/rtl/wbqspiflashp.v File deleted
/s6soc/trunk/rtl/wbubus.v File deleted
/s6soc/trunk/rtl/wbpwmaudio.v
81,12 → 81,11
// Wishbone interface
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
o_wb_ack, o_wb_stall, o_wb_data,
o_pwm, o_aux, o_int);
parameter DEFAULT_RELOAD = 12'd1814, // about 44.1 kHz @ 80MHz
o_pwm, o_int);
parameter DEFAULT_RELOAD = 32'd1814, // about 44.1 kHz @ 80MHz
//DEFAULT_RELOAD = 32'd2268,//about 44.1 kHz @ 100MHz
NAUX=2, // Dev control values
VARIABLE_RATE=0,
TIMING_BITS=12;
VARIABLE_RATE=0;
input i_clk;
input i_wb_cyc, i_wb_stb, i_wb_we;
input i_wb_addr;
102,27 → 101,29
// How often shall we create an interrupt? Every reload_value clocks!
// If VARIABLE_RATE==0, this value will never change and will be kept
// at the default reload rate (44.1 kHz, for a 100 MHz clock)
wire [(TIMING_BITS-1):0] w_reload_value;
generate
if (VARIABLE_RATE != 0)
begin
reg [(TIMING_BITS-1):0] r_reload_value;
reg [31:0] r_reload_value;
initial r_reload_value = DEFAULT_RELOAD;
always @(posedge i_clk) // Data write
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
r_reload_value <= i_wb_data[(TIMING_BITS-1):0];
reload_value <= i_wb_data;
wire [31:0] w_reload_value;
assign w_reload_value = r_reload_value;
end else begin
wire [31:0] w_reload_value;
assign w_reload_value = DEFAULT_RELOAD;
end endgenerate
 
reg [(TIMING_BITS-1):0] timer;
reg [31:0] reload_value, timer;
initial reload_value = DEFAULT_RELOAD;
initial timer = DEFAULT_RELOAD;
always @(posedge i_clk)
if (timer == 0)
timer <= {{(32-TIMING_BITS){1'b0}}, w_reload_value };
timer <= reload_value;
else
timer <= timer - {{(TIMING_BITS-1){1'b0}},1'b1};
timer <= timer - 1;
 
reg [15:0] sample_out;
always @(posedge i_clk)
175,7 → 176,7
reg [31:0] r_wb_data;
always @(posedge i_clk)
if (i_wb_addr)
r_wb_data <= w_reload_value;
r_wb_data <= reload_value;
else
r_wb_data <= { {(12-NAUX){1'b0}}, o_aux,
3'h0, o_int, sample_out };
/s6soc/trunk/rtl/rtclight.v
52,8 → 52,7
o_interrupt,
// A once-per-day strobe on the last clock of the day
o_ppd);
parameter DEFAULT_SPEED = 32'd2814750,
CKBITS = 24; // 100 Mhz
parameter DEFAULT_SPEED = 32'd2814750; // 100 Mhz
input i_clk;
input i_wb_cyc, i_wb_stb, i_wb_we;
input [2:0] i_wb_addr;
63,8 → 62,7
output wire o_interrupt, o_ppd;
 
reg [21:0] clock;
reg [31:0] stopwatch;
reg [(CKBITS-1):0] ckspeed;
reg [31:0] stopwatch, ckspeed;
reg [25:0] timer;
wire ck_sel, tm_sel, sw_sel, sp_sel, al_sel;
79,8 → 77,7
initial ck_carry = 1'b0;
initial ck_counter = 40'h00;
always @(posedge i_clk)
{ ck_carry, ck_counter } <= ck_counter
+ { {(8+32-CKBITS){1'b0}}, ckspeed };
{ ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed };
 
wire ck_pps;
reg ck_prepps, ck_ppm, ck_pph, ck_ppd;
/s6soc/trunk/rtl/cpu/ziptimer.v
121,7 → 121,7
initial o_int = 1'b0;
always @(posedge i_clk)
if (i_ce)
o_int<=(r_running)&&(r_value == {{(VW-1){1'b0}},1'b1 });
o_int <= (r_running)&&(r_value == { {(VW-1){1'b0}}, 1'b1 });
else
o_int <= 1'b0;
 
130,11 → 130,6
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
assign o_wb_stall = 1'b0;
 
generate
if (VW < BW-1)
assign o_wb_data = { r_auto_reload, r_value };
else
assign o_wb_data = { r_auto_reload, {(BW-1-VW){1'b0}}, r_value };
endgenerate
assign o_wb_data = { r_auto_reload, r_value };
 
endmodule
/s6soc/trunk/rtl/rxuart.v
1,8 → 1,9
////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
//
//
// Filename: rxuart.v
//
// Project: CMod S6 System on a Chip, ZipCPU demonstration project
// Project: FPGA library development (Spartan 3E development board)
//
// Purpose: Receive and decode inputs from a single UART line.
//
59,32 → 60,20
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// Copyright: 2015
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
/////////////////////////////////////////////////////////////////////////
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
// This software is the ownership of Gisselquist Technology, LLC, and as
// such it is proprietary. It is provided without any warrantees, either
// express or implied, so that it may be tested. Upon completion, I ask
// that working code be returned and not further distributed beyond those
// that it is originally offered to.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
// Thank you.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
 
// States: (@ baud counter == 0)
// 0 First bit arrives
// ..7 Bits arrive
/s6soc/trunk/rtl/txuart.v
1,8 → 1,9
////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
//
//
// Filename: txuart.v
//
// Project: CMod S6 System on a Chip, ZipCPU demonstration project
// Project: FPGA library development (Spartan 3E development board)
//
// Purpose: Transmit outputs over a single UART line.
//
59,33 → 60,19
// Creator: Dan Gisselquist
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// Copyright: 2015
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
/////////////////////////////////////////////////////////////////////////
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
// This software is the ownership of Gisselquist Technology, LLC, and as
// such it is proprietary. It is provided without any warrantees, either
// express or implied, so that it may be tested. Upon completion, I ask
// that working code be returned and not further distributed beyond those
// that it is originally offered to.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
// Thank you.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
//
`define TXU_BIT_ZERO 4'h0
`define TXU_BIT_ONE 4'h1
`define TXU_BIT_TWO 4'h2
102,17 → 89,14
// `define TXU_START 4'hd // An unused state
`define TXU_BREAK 4'he
`define TXU_IDLE 4'hf
//
//
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data, o_uart, i_cts, o_busy);
 
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data, o_uart, o_busy);
input i_clk, i_reset;
input [29:0] i_setup;
input i_break;
input i_wr;
input [7:0] i_data;
output reg o_uart;
input i_cts;
output wire o_busy;
output reg o_uart, o_busy;
 
wire [27:0] clocks_per_baud, break_condition;
wire [1:0] data_bits;
130,10 → 114,9
reg [3:0] state;
reg [7:0] lcl_data;
reg calc_parity;
reg r_busy;
 
initial o_uart = 1'b1;
initial r_busy = 1'b1;
initial o_busy = 1'b1;
initial state = `TXU_IDLE;
// initial baud_counter = clocks_per_baud;
always @(posedge i_clk)
142,7 → 125,7
begin
baud_counter <= clocks_per_baud;
o_uart <= 1'b1;
r_busy <= 1'b1;
o_busy <= 1'b1;
state <= `TXU_IDLE;
lcl_data <= 8'h0;
calc_parity <= 1'b0;
152,15 → 135,15
o_uart <= 1'b0;
state <= `TXU_BREAK;
calc_parity <= 1'b0;
r_busy <= 1'b1;
o_busy <= 1'b1;
end else if (baud_counter != 0)
begin // r_busy needs to be set coming into here
begin // o_busy needs to be set coming into here
baud_counter <= baud_counter - 28'h01;
r_busy <= 1'b1;
o_busy <= 1'b1;
end else if (state == `TXU_BREAK)
begin
state <= `TXU_IDLE;
r_busy <= 1'b1;
o_busy <= 1'b1;
o_uart <= 1'b1;
calc_parity <= 1'b0;
// Give us two stop bits before becoming available
170,10 → 153,10
// baud_counter <= 0;
r_setup <= i_setup;
calc_parity <= 1'b0;
if ((i_wr)&&(~r_busy))
if ((i_wr)&&(~o_busy))
begin // Immediately start us off with a start bit
o_uart <= 1'b0;
r_busy <= 1'b1;
o_busy <= 1'b1;
case(data_bits)
2'b00: state <= `TXU_BIT_ZERO;
2'b01: state <= `TXU_BIT_ONE;
184,7 → 167,7
baud_counter <= clocks_per_baud-28'h01;
end else begin // Stay in idle
o_uart <= 1'b1;
r_busy <= 0;
o_busy <= 0;
// lcl_data is irrelevant
// state <= state;
end
191,7 → 174,7
end else begin
// One clock tick in each of these states ...
baud_counter <= clocks_per_baud - 28'h01;
r_busy <= 1'b1;
o_busy <= 1'b1;
if (state[3] == 0) // First 8 bits
begin
o_uart <= lcl_data[0];
220,7 → 203,7
begin
state <= `TXU_IDLE; // Go back to idle
o_uart <= 1'b1;
// Still r_busy, since we need to wait
// Still o_busy, since we need to wait
// for the baud clock to finish counting
// out this last bit.
end
227,7 → 210,8
end
end
 
// assign o_busy = (r_busy)||(~i_cts);
assign o_busy = (r_busy);
endmodule
 
 
 
 
/s6soc/trunk/rtl/toplevel.v
1,59 → 1,8
`timescale 10ns / 100ps
////////////////////////////////////////////////////////////////////////////////
//
// Filename: toplevel.v
//
// Project: CMod S6 System on a Chip, ZipCPU demonstration project
//
// Purpose: This is (supposed to be) the one Xilinx specific file in the
// project. The idea is that all of the board specific logic,
// the logic used in simulation, is kept in the busmaster.v file. It's
// not quite true, since rxuart and txuart modules are instantiated here,
// but it's mostly true.
//
// One thing that makes this module unique is that all of its inputs and
// outputs must match those on the chip, as specified within the cmod.ucf
// file (up one directory).
//
// Within this file you will find specific I/O for output pins, such as
// the necessary adjustments to make an I2C port from GPIO pins, as well
// as the clock management approach.
//
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
module toplevel(i_clk_8mhz,
o_qspi_cs_n, o_qspi_sck, io_qspi_dat,
i_btn, o_led, o_pwm, o_pwm_shutdown_n, o_pwm_gain,
i_uart, o_uart, i_uart_cts, o_uart_rts,
i_uart, o_uart,
i_kp_row, o_kp_col,
i_gpio, o_gpio,
io_scl, io_sda);
72,9 → 21,6
// and our serial port
input i_uart;
output wire o_uart;
// and it's associated control wires
input i_uart_cts;
output wire o_uart_rts;
// Our keypad
input [3:0] i_kp_row;
output wire [3:0] o_kp_col;
84,20 → 30,15
// and our I2C port
inout io_scl, io_sda;
 
/////
wire ck_zero_0, clk_s; // intermediate_clk, intermediate_clk_n;
 
//
// Clock management
//
// Generate a usable clock for the rest of the board to run at.
//
wire ck_zero_0, clk_s;
 
// Clock frequency = (20 / 2) * 8Mhz = 80 MHz
// Clock period = 12.5 ns
// Clock frequency = (25 / 2) * 8Mhz
// Clock period = 10 ns
DCM_SP #(
.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(2), // Here's the divide by two
.CLKFX_MULTIPLY(20), // and here's the multiply by 20
.CLKFX_DIVIDE(2),
.CLKFX_MULTIPLY(20),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(125.0),
.CLKOUT_PHASE_SHIFT("NONE"),
111,16 → 52,11
.CLK0(ck_zero_0),
.CLKFB(ck_zero_0),
.CLKFX(clk_s),
// .CLKFX180(intermediate_clk_n),
.PSEN(1'b0),
.RST(1'b0));
 
//
// Generate active-high reset.
//
// Actually, we don't. Instead, let this board reset through
// the reconfiguration/power on process and we never use this
// wire.
//
/*
reg r_reset;
initial r_reset = 1'b1;
129,15 → 65,6
*/
assign reset_s = 1'b0;
 
 
//
// The UART serial interface
//
// Perhaps this should be part of our simulation model as well.
// For historical reasons, internal to Gisselquist Technology,
// this has remained separate from the simulation, allowing the
// simulation to bypass whether or not these two functions work.
//
wire rx_stb, tx_stb;
wire [7:0] rx_data, tx_data;
wire tx_busy;
145,22 → 72,13
 
wire rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, tx_break;
assign tx_break = 1'b0;
rxuart rcvuart(clk_s, reset_s, uart_setup,
i_uart, rx_stb, rx_data,
rxuart rcvuart(clk_s, reset_s, uart_setup, i_uart, rx_stb, rx_data,
rx_break, rx_parity_err, rx_frame_err, rx_ck_uart);
txuart tcvuart(clk_s, reset_s, uart_setup, tx_break, tx_stb, tx_data,
o_uart, i_uart_cts, tx_busy);
o_uart, tx_busy);
 
 
//
// BUSMASTER
//
// Busmaster is so named because it contains the wishbone
// interconnect that all of the internal devices are hung off of.
// To reconfigure this device for another purpose, usually
// the busmaster module (i.e. the interconnect) is all that needs
// to be changed: either to add more devices, or to remove them.
//
 
wire [3:0] qspi_dat;
wire [1:0] qspi_bmod;
wire [15:0] w_gpio;
167,7 → 85,7
 
busmaster masterbus(clk_s, reset_s,
// External ... bus control (if enabled)
rx_stb, rx_data, tx_stb, tx_data, tx_busy, o_uart_rts,
rx_stb, rx_data, tx_stb, tx_data, tx_busy,
// SPI/SD-card flash
o_qspi_cs_n, o_qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod,
// Board lights and switches
180,28 → 98,9
{ i_gpio, io_scl, io_sda }, w_gpio
);
 
//
// Quad SPI support
//
// Supporting a Quad SPI port requires knowing which direction the
// wires are going at each instant, whether the device is in full
// Quad mode in, full quad mode out, or simply the normal SPI
// port with one wire in and one wire out. This utilizes our
// control wires (qspi_bmod) to set the output lines appropriately.
//
assign io_qspi_dat = (~qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
:((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
 
//
// I2C support
//
// Supporting I2C requires a couple quick adjustments to our
// GPIO lines. Specifically, we'll allow that when the output
// (i.e. w_gpio) pins are high, then the I2C lines float. They
// will be (need to be) pulled up by a resistor in order to
// match the I2C protocol, but this change makes them look/act
// more like GPIO pins.
//
assign io_sda = (w_gpio[0]) ? 1'bz : 1'b0;
assign io_scl = (w_gpio[1]) ? 1'bz : 1'b0;
assign o_gpio[15:2] = w_gpio[15:2];
/s6soc/trunk/rtl/busmaster.v
1,54 → 1,30
////////////////////////////////////////////////////////////////////////////////
//
// Filename: busmaster.v
//
// Project: CMod S6 System on a Chip, ZipCPU demonstration project
// Filename: busmaster.v
//
// Purpose:
// Project: FPGA library development (S6 development board)
//
// Creator: Dan Gisselquist, Ph.D.
// Purpose:
//
// Creator: Dan Gisselquist
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// Copyright: 2015
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
//
`include "builddate.v"
//
`define NO_ZIP_WBU_DELAY
`define INCLUDE_ZIPPY
`define IMPLEMENT_ONCHIP_RAM // 2804 w/o after synthesis
`define IMPLEMENT_ONCHIP_RAM
`ifndef VERILATOR
`define FANCY_ICAP_ACCESS
`endif
`define FLASH_ACCESS
// `define CFG_SCOPE // About 204 LUTs, at 2^6 addresses
`define INCLUDE_RTC // About 90 LUTs
`define CFG_SCOPE
`define INCLUDE_RTC // 2017 slice LUTs w/o, 2108 with (!!!)
module busmaster(i_clk, i_rst,
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
o_uart_rts,
// The SPI Flash lines
o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
// The board I/O
69,7 → 45,6
output reg o_tx_stb;
output reg [7:0] o_tx_data;
input i_tx_busy;
output wire o_uart_rts;
// SPI flash control
output wire o_qspi_cs_n, o_qspi_sck;
output wire [3:0] o_qspi_dat;
169,7 → 144,7
assign rtc_stall = 1'b0;
`endif
wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
reg io_ack;
reg io_ack, uart_ack;
 
wire [31:0] flash_data, scop_data, cfg_data, mem_data, pwm_data,
spio_data, gpio_data, uart_data;
177,6 → 152,7
reg [(BAW-1):0] bus_err_addr;
 
assign wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
||(uart_ack)
`ifdef INCLUDE_RTC
||(rtc_ack)
`endif
200,8 → 176,9
: 32'h00))));
*/
assign wb_idata = (io_ack|scop_ack)?((io_ack )? io_data : scop_data)
: ((cfg_ack|uart_ack) ? ((cfg_ack)?cfg_data: uart_data)
: ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
: ((cfg_ack) ? cfg_data : flash_data));//if (flash_ack)
: flash_data)); // if (flash_ack)
assign wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
 
// Addresses ...
256,7 → 233,8
wb_err, button_int };
 
wire [31:0] pic_data;
icontrol #(11) pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
icontrol #(11) pic(i_clk, 1'b0,
(wb_cyc)&&(wb_stb)&&(io_sel)
&&(wb_addr[3:0]==4'h0)&&(wb_we),
wb_data, pic_data, int_vector, w_interrupt);
 
267,13 → 245,11
 
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
wire [31:0] timer_a, timer_b;
ziptimer #(32,20)
zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
ziptimer zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
wb_we, wb_data, zta_ack, zta_stall, timer_a,
tmra_int);
ziptimer #(32,20)
zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
ziptimer zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
tmrb_int);
290,7 → 266,7
assign rtc_ack = r_rtc_ack;
 
rtclight
#(32'h35afe5,23) // 80 MHz clock
#(32'h35afe5) // 80 MHz clock
thetime(i_clk, wb_cyc,
((wb_stb)&&(rtc_sel)), wb_we,
{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
357,7 → 333,7
initial o_tx_stb = 1'b0;
initial o_tx_data = 8'h00;
always @(posedge i_clk)
if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
if ((wb_cyc)&&(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
begin
o_tx_data <= wb_data[7:0];
o_tx_stb <= 1'b1;
370,19 → 346,14
r_rx_data <= i_rx_data;
always @(posedge i_clk)
begin
if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
if((wb_cyc)&&(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
rx_rdy <= i_rx_stb;
else if (i_rx_stb)
rx_rdy <= (rx_rdy | i_rx_stb);
end
assign o_uart_rts = (~rx_rdy);
assign uart_data = { 23'h0, ~rx_rdy, r_rx_data };
//
// uart_ack gets returned as part of io_ack, since that happens when
// io_sel and wb_stb are defined
//
// always @(posedge i_clk)
// uart_ack<= ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
always @(posedge i_clk)
uart_ack<= ((wb_cyc)&&(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
 
 
 
392,7 → 363,7
wire flash_cs_n, flash_sck, flash_mosi;
wbqspiflash #(24) flashmem(i_clk,
wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
wb_addr[(24-3):0], wb_data,
wb_addr[21:0], wb_data,
flash_ack, flash_stall, flash_data,
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
flash_interrupt);
420,17 → 391,8
//
// ON-CHIP RAM MEMORY ACCESS
//
`ifdef IMPLEMENT_ONCHIP_RAM
memdev #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
`else
assign mem_data = 32'h00;
assign mem_stall = 1'b0;
reg r_mem_ack;
always @(posedge i_clk)
r_mem_ack <= (wb_cyc)&&(wb_stb)&&(mem_sel);
assign mem_ack = r_mem_ack;
`endif
 
//
//
444,19 → 406,12
`ifdef CFG_SCOPE
wire scop_cfg_trigger;
assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
wbscope #(5'h6) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
// Wishbone interface
i_clk, wb_cyc, (wb_stb)&&(scop_sel),
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
wb_we, wb_addr[0], wb_data,
scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
scop_cfg_interrupt);
`else
reg r_scop_cfg_ack;
always @(posedge i_clk)
r_scop_cfg_ack <= (wb_cyc)&&(wb_stb)&&(scop_sel);
assign scop_cfg_ack = r_scop_cfg_ack;
assign scop_cfg_data = 32'h000;
assign scop_cfg_stall= 1'b0;
`endif
 
assign scop_interrupt = scop_cfg_interrupt;
466,3 → 421,4
 
endmodule
 
// 0x8684 interrupts ...???

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