OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /s6soc
    from Rev 16 to Rev 17
    Reverse comparison

Rev 16 → Rev 17

/trunk/bench/cpp/qspiflashsim.cpp
106,6 → 106,8
 
void QSPIFLASHSIM::write(const unsigned addr, const unsigned len, const uint32_t *buf) {
char *ptr;
if ((addr+len < SPIFLASH)||(addr >= SPIFLASH+MEMBYTES/4))
return;
printf("FLASH: Copying into memory at S6Add4 %08x, my addr %08x, %d values\n",
addr, (addr-SPIFLASH)<<2, len<<2);
ptr = &m_mem[(addr-SPIFLASH)<<2];
/trunk/bench/cpp/zip_sim.cpp
80,9 → 80,11
KEYPADSIM m_keypad;
unsigned m_last_led;
time_t m_start_time;
FILE *m_dbg;
 
ZIPSIM_TB(void) : m_uart(0x2b6) {
m_start_time = time(NULL);
m_dbg = fopen("dbg.txt","w");
}
 
void reset(void) {
127,8 → 129,8
m_last_led = m_core->o_led;
}
 
/*
printf("PC: %08x:%08x [%08x:%08x:%08x:%08x:%08x],%08x,%08x,%d,%08x,%08x (%x,%x)\n",
if (m_dbg) fprintf(m_dbg, "PC: %08x:%08x [%08x:%08x:%08x:%08x:%08x],%08x,%08x,%d,%08x,%08x (%x,%x/0x%08x)\n",
m_core->v__DOT__thecpu__DOT__thecpu__DOT__ipc,
m_core->v__DOT__thecpu__DOT__thecpu__DOT__upc,
m_core->v__DOT__thecpu__DOT__thecpu__DOT__regset[0],
142,11 → 144,11
m_core->v__DOT__thecpu__DOT__thecpu__DOT__r_opA,
m_core->v__DOT__thecpu__DOT__thecpu__DOT__wr_reg_vl,
m_core->v__DOT__thecpu__DOT__thecpu__DOT__w_iflags,
m_core->v__DOT__thecpu__DOT__thecpu__DOT__w_iflags,
m_core->v__DOT__thecpu__DOT__thecpu__DOT__w_uflags,
m_core->v__DOT__thecpu__DOT__thecpu__DOT__pf_pc
);
if (m_core->v__DOT__wb_cyc) {
printf("WB: %s/%s/%s[@0x%08x] %08x ->%s/%s %08x\n",
if ((m_core->v__DOT__wb_cyc)&&(m_dbg))
fprintf(m_dbg, "WB: %s/%s/%s[@0x%08x] %08x ->%s/%s %08x\n",
(m_core->v__DOT__wb_cyc)?"CYC":" ",
(m_core->v__DOT__wb_stb)?"STB":" ",
(m_core->v__DOT__wb_we )?"WE ":" ",
156,10 → 158,16
(m_core->v__DOT__wb_stall)?"STL":" ",
(m_core->v__DOT__wb_idata)
);
}
if (m_dbg)
fprintf(m_dbg, "PIC: %3s(%4x) %3s(%4x)%s\n",
(m_core->v__DOT__pic__DOT__r_gie)?"GIE":"",
(m_core->v__DOT__pic__DOT__r_int_enable),
(m_core->v__DOT__pic__DOT__r_any)?"ANY":"",
(m_core->v__DOT__pic__DOT__r_int_state),
(m_core->v__DOT__pic__DOT__r_interrupt)?" ---> INT!":"");
 
if (m_core->v__DOT__thecpu__DOT__thecpu__DOT__pf_valid)
printf("PC: %08x - %08x, uart=%d,%d, pic = %d,%04x,%0d,%04x\n",
if ((m_core->v__DOT__thecpu__DOT__thecpu__DOT__pf_valid)&&(m_dbg))
fprintf(m_dbg, "PC: %08x - %08x, uart=%d,%d, pic = %d,%04x,%0d,%04x\n",
m_core->v__DOT__thecpu__DOT__thecpu__DOT__instruction_pc,
m_core->v__DOT__thecpu__DOT__thecpu__DOT__instruction,
m_core->i_rx_stb, m_core->i_tx_busy,
167,9 → 175,6
m_core->v__DOT__pic__DOT__r_int_enable,
m_core->v__DOT__pic__DOT__r_any,
m_core->v__DOT__pic__DOT__r_int_state);
*/
 
printf("%08x\n", m_core->v__DOT__zipt_a__DOT__r_value);
}
};
 

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.