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URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

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  • This comparison shows the changes necessary to convert path 
    /s6soc
    from Rev 25 to Rev 24
    ↔ Reverse comparison
  •

Rev 25 → Rev 24

/trunk/rtl/busmaster.v
47,10 → 47,8
`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
// `define COMPRESSED_SCOPE
`define INCLUDE_SECOND_TIMER
`define SECOND_TIMER_IS_WATCHDOG
`define INCLUDE_CPU_RESET_LOGIC
// `define INCLUDE_RTC // About 90 LUTs
// `define FULL_BUSERR_CALCULATION
`define INCLUDE_CPU_RESET_LOGIC
module busmaster(i_clk, i_rst,
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
o_uart_cts,
149,7 → 147,7
// in the flash without needing to change our FPGA load and vice versa.
//
// 23'h404000
wire cpu_reset, tmrb_int;
wire cpu_reset;
`ifdef INCLUDE_CPU_RESET_LOGIC
reg btn_reset, x_button, r_button;
initial btn_reset = 1'b0;
159,11 → 157,7
begin
x_button <= i_btn[1];
r_button <= x_button;
`ifdef SECOND_TIMER_IS_WATCHDOG
btn_reset <= ((r_button)&&(zip_cpu_int))||(tmrb_int);
`else
btn_reset <= ((r_button)&&(zip_cpu_int));
`endif
end
assign cpu_reset = btn_reset;
`else
189,7 → 183,7
 
wire io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
rtc_sel, none_sel, many_sel;
wire flash_ack, scop_ack, cfg_ack, mem_ack, many_ack;
wire flash_ack, scop_ack, cfg_ack, mem_ack;
wire rtc_ack, rtc_stall;
`ifdef INCLUDE_RTC
assign rtc_stall = 1'b0;
234,8 → 228,8
// 0000 xxxx configuration/control registers
// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
assign io_sel =((wb_cyc)&&(io_addr[5:0]==6'h1));
assign flctl_sel= 1'b0; // ((wb_cyc)&&(io_addr[5:1]==5'h1));
assign scop_sel =((wb_cyc)&&(io_addr[5:1]==5'h1));
assign flctl_sel= 1'b0; // ((wb_cyc)&&(io_addr[5:1]==5'h1));
assign cfg_sel =((wb_cyc)&&(io_addr[5:2]==4'h1));
// zip_sel is not on the bus at this point
`ifdef INCLUDE_RTC
244,12 → 238,14
assign mem_sel =((wb_cyc)&&(io_addr[5:4]==2'h1));
assign flash_sel=((wb_cyc)&&(io_addr[5]));
 
`ifdef FULL_BUSERR_CALCULATION
assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
/*
assign none_sel =((wb_cyc)&&(wb_stb)&&
((io_addr==6'h0)
||((~io_addr[5])&&(|wb_addr[22:14]))
||((io_addr[5:4]==2'b00)&&(|wb_addr[12])))
||((~io_addr[5])&&(|wb_addr[22:14])))
);
*/
/*
assign many_sel =((wb_cyc)&&(wb_stb)&&(
{3'h0, io_sel}
+{3'h0, flctl_sel}
258,7 → 254,10
+{3'h0, rtc_sel}
+{3'h0, mem_sel}
+{3'h0, flash_sel} > 1));
*/
assign many_sel = 1'b0;
 
wire many_ack;
assign many_ack =((wb_cyc)&&(
{3'h0, io_ack}
+{3'h0, scop_ack}
268,12 → 267,8
`endif
+{3'h0, mem_ack}
+{3'h0, flash_ack} > 1));
`else
assign many_ack = 1'b0;
assign many_sel = 1'b0;
assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
`endif
wire flash_interrupt, scop_interrupt, tmra_int,
 
wire flash_interrupt, scop_interrupt, tmra_int, tmrb_int,
rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int;
 
 
282,15 → 277,9
//
reg rx_rdy;
wire [10:0] int_vector;
assign int_vector = {
gpio_int, pwm_int, keypad_int,
assign int_vector = { gpio_int, pwm_int, keypad_int,
(~o_tx_stb), rx_rdy,
`ifdef SECOND_TIMER_IS_WATCHDOG
1'b0,
`else
tmrb_int,
`endif
tmra_int,
tmrb_int, tmra_int,
rtc_interrupt, scop_interrupt,
wb_err, button_int };
 
306,7 → 295,7
 
wire [31:0] timer_a, timer_b;
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
ziptimer #(32,31,1)
ziptimer #(32,31)
zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
`ifdef INCLUDE_SECOND_TIMER
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
316,20 → 305,12
wb_we, wb_data, zta_ack, zta_stall, timer_a,
tmra_int);
`ifdef INCLUDE_SECOND_TIMER
`ifdef SECOND_TIMER_IS_WATCHDOG
ziptimer #(32,31,0)
ziptimer #(32,31)
zipt_b(i_clk, cpu_reset, 1'b1, wb_cyc,
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
tmrb_int);
`else
ziptimer #(32,31,1)
zipt_b(i_clk, cpu_reset, 1'b1, wb_cyc,
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
tmrb_int);
`endif
`else
// assign timer_b = 32'h000;
assign timer_b = timer_a;
assign tmrb_int = 1'b0;
/trunk/rtl/altbusmaster.v
44,11 → 44,7
`endif
`define FLASH_ACCESS
`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
// `define COMPRESSED_SCOPE
`define INCLUDE_SECOND_TIMER
`define SECOND_TIMER_IS_WATCHDOG
`define INCLUDE_RTC // About 90 LUTs
`define FULL_BUSERR_CALCULATION
`define WBUBUS
module altbusmaster(i_clk, i_rst,
// DEPP I/O Control
171,7 → 167,7
 
wire io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
rtc_sel, none_sel, many_sel;
wire flash_ack, scop_ack, cfg_ack, mem_ack, many_ack;
wire flash_ack, scop_ack, cfg_ack, mem_ack;
wire rtc_ack, rtc_stall;
`ifdef INCLUDE_RTC
assign rtc_stall = 1'b0;
226,12 → 222,7
assign mem_sel =((wb_cyc)&&(io_addr[5:4]==2'h1));
assign flash_sel=((wb_cyc)&&(io_addr[5]));
 
`ifdef FULL_BUSERR_CALCULATION
assign none_sel =((wb_cyc)&&(wb_stb)&&
((io_addr==6'h0)
||((~io_addr[5])&&(|wb_addr[22:14]))
||((io_addr[5:4]==2'b00)&&(|wb_addr[12])))
);
assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
assign many_sel =((wb_cyc)&&(wb_stb)&&(
{3'h0, io_sel}
+{3'h0, flctl_sel}
240,7 → 231,9
+{3'h0, rtc_sel}
+{3'h0, mem_sel}
+{3'h0, flash_sel} > 1));
// assign many_sel = 1'b0;
 
wire many_ack;
assign many_ack =((wb_cyc)&&(
{3'h0, io_ack}
+{3'h0, scop_ack}
250,11 → 243,7
`endif
+{3'h0, mem_ack}
+{3'h0, flash_ack} > 1));
`else
assign many_ack = 1'b0;
assign many_sel = 1'b0;
assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
`endif
 
wire flash_interrupt, scop_interrupt, tmra_int, tmrb_int,
rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int;
 
264,8 → 253,7
//
reg rx_rdy;
wire [11:0] int_vector;
assign int_vector = {
flash_interrupt, gpio_int, pwm_int, keypad_int,
assign int_vector = { flash_interrupt, gpio_int, pwm_int, keypad_int,
(~o_tx_stb), rx_rdy,
tmrb_int, tmra_int,
rtc_interrupt, scop_interrupt,
283,34 → 271,16
 
wire [31:0] timer_a, timer_b;
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
ziptimer #(32,31,1)
ziptimer #(32,31)
zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
`ifdef INCLUDE_SECOND_TIMER
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
`else
(wb_stb)&&(io_sel)&&(wb_addr[3:1]==3'h1),
`endif
wb_we, wb_data, zta_ack, zta_stall, timer_a,
tmra_int);
`ifdef INCLUDE_SECOND_TIMER
`ifdef SECOND_TIMER_IS_WATCHDOG
ziptimer #(32,31,0)
ziptimer #(32,31)
zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
tmrb_int);
`else
ziptimer #(32,31,1)
zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
tmrb_int);
`endif
`else
// assign timer_b = 32'h000;
assign timer_b = timer_a;
assign tmrb_int = 1'b0;
`endif
 
wire [31:0] rtc_data;
`ifdef INCLUDE_RTC
364,11 → 334,9
//
// Special Purpose I/O: Keypad, button, LED status and control
//
wire [3:0] w_led;
spio thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),wb_we,
wb_data, spio_data, o_kp_col, i_kp_row, i_btn, w_led,
wb_data, spio_data, o_kp_col, i_kp_row, i_btn, o_led,
keypad_int, button_int);
assign o_led = { w_led[3]|w_interrupt,w_led[2]|zip_cpu_int,w_led[1:0] };
 
//
// General purpose (sort of) I/O: (Bottom two bits robbed in each
482,14 → 450,7
`ifdef DBG_SCOPE
wire scop_cfg_trigger;
assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
wire scop_trigger = scop_cfg_trigger;
`ifdef COMPRESSED_SCOPE
wbscopc #(5'ha)
`else
wbscope #(5'ha)
`endif
wbcfgscope(i_clk, 1'b1, scop_trigger,
cfg_scope,
wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
// Wishbone interface
i_clk, wb_cyc, (wb_stb)&&(scop_sel),
wb_we, wb_addr[0], wb_data,

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