OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 41 to Rev 42
    Reverse comparison

Rev 41 → Rev 42

/s6soc/trunk/rtl/cpu/ziptimer.v
84,7 → 84,7
wire wb_write;
assign wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
 
wire auto_reload;
wire auto_reload, need_reload;
wire [(VW-1):0] reload_value;
 
initial r_running = 1'b0;
99,11 → 99,10
generate
if (RELOADABLE != 0)
begin
reg r_auto_reload;
reg r_auto_reload, r_need_reload;
reg [(VW-1):0] r_reload_value;
 
initial r_auto_reload = 1'b0;
 
always @(posedge i_clk)
if (wb_write)
r_auto_reload <= (i_wb_data[(BW-1)]);
116,9 → 115,20
if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0]))
r_reload_value <= i_wb_data[(VW-1):0];
assign reload_value = r_reload_value;
 
initial r_need_reload = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_need_reload <= 1'b0;
else if ((i_ce)&&(auto_reload))
r_need_reload <= (i_ce)
&&(r_value == { {(VW-1){1'b0}}, 1'b1 });
 
assign need_reload = r_need_reload;
end else begin
assign auto_reload = 1'b0;
assign reload_value = 0;
assign need_reload = 1'b0;
end endgenerate
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.