URL
https://opencores.org/ocsvn/s6soc/s6soc/trunk
Subversion Repositories s6soc
Compare Revisions
- This comparison shows the changes necessary to convert path
/s6soc/trunk/rtl/cpu
- from Rev 11 to Rev 16
- ↔ Reverse comparison
Rev 11 → Rev 16
/ziptimer.v
120,7 → 120,9
// Set the interrupt on our last tick. |
initial o_int = 1'b0; |
always @(posedge i_clk) |
if (i_ce) |
if (i_rst) |
o_int <= 1'b0; |
else if (i_ce) |
o_int <= (r_running)&&(r_value == { {(VW-1){1'b0}}, 1'b1 }); |
else |
o_int <= 1'b0; |
/cpudefs.v
266,6 → 266,6
// `define INCLUDE_ACCOUNTING_COUNTERS |
// |
// |
// `define DEBUG_SCOPE |
`define DEBUG_SCOPE |
// |
`endif // CPUDEFS_H |
/cpuops.v
240,8 → 240,8
// +(al*bl) |
// - 2^31 (2^16 bh+bl + 2^16 ah+al + 2^31) |
// |
reg [31:0] pp_f, pp_l; // pp_o, pp_i, pp_l; |
reg [32:0] pp_oi; |
reg [31:0] pp_f, pp_l; // F and L from FOIL |
reg [32:0] pp_oi; // The O and I from FOIL |
reg [32:0] pp_s; |
always @(posedge i_clk) |
begin |
/zipcpu.v
304,7 → 304,8
// |
// |
reg [(AW-1):0] alu_pc; |
reg alu_pc_valid, mem_pc_valid; |
reg r_alu_pc_valid, mem_pc_valid; |
wire alu_pc_valid; |
wire alu_phase; |
wire alu_ce, alu_stall; |
wire [31:0] alu_result; |
375,11 → 376,8
// |
// PIPELINE STAGE #2 :: Instruction Decode |
// Calculate stall conditions |
`ifdef OPT_PIPELINED |
assign dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline); |
`else |
assign dcd_ce = 1'b1; |
`endif |
|
`ifdef OPT_PIPELINED |
assign dcd_stalled = (dcdvalid)&&(op_stall); |
`else |
428,7 → 426,7
assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline); |
`else |
assign op_stall = (opvalid)&&(~master_ce); |
assign op_ce = ((dcdvalid)||(dcd_illegal)); |
assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~clear_pipeline); |
`endif |
|
// |
458,7 → 456,7
`else |
assign alu_stall = ((~master_ce)&&(opvalid_alu)) |
||((opvalid_alu)&&(op_break)); |
assign alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall); |
assign alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall)&&(~clear_pipeline); |
`endif |
// |
|
473,7 → 471,7
// If we aren't pipelined, then no one will be changing what's in the |
// pipeline (i.e. clear_pipeline), while our only instruction goes |
// through the ... pipeline. |
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled); |
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline); |
`endif |
`ifdef OPT_PIPELINED_BUS_ACCESS |
assign mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&( |
512,7 → 510,7
|
assign pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_valid); |
prefetch #(ADDRESS_WIDTH) |
pf(i_clk, i_rst, (pf_ce), (~dcd_stalled), pf_pc, gie, |
pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc, gie, |
instruction, instruction_pc, instruction_gie, |
pf_valid, pf_illegal, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
520,7 → 518,7
|
initial r_dcdvalid = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
if ((i_rst)||(clear_pipeline)) |
r_dcdvalid <= 1'b0; |
else if (dcd_ce) |
r_dcdvalid <= (pf_valid); |
565,7 → 563,7
if ((i_rst)||(clear_pipeline)) |
r_dcdvalid <= 1'b0; |
else if (dcd_ce) |
r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&(~dcd_ljmp)&&((~r_dcdvalid)||(~dcd_early_branch)); |
r_dcdvalid <= (pf_valid)&&(~dcd_ljmp)&&((~r_dcdvalid)||(~dcd_early_branch)); |
else if (op_ce) |
r_dcdvalid <= 1'b0; |
assign dcdvalid = r_dcdvalid; |
1160,13 → 1158,16
assign alu_illegal = (alu_illegal_op)||(r_alu_illegal); |
`endif |
|
initial alu_pc_valid = 1'b0; |
initial r_alu_pc_valid = 1'b0; |
initial mem_pc_valid = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
alu_pc_valid <= 1'b0; |
else |
alu_pc_valid <= (alu_ce); |
r_alu_pc_valid <= 1'b0; |
else if (alu_ce) // Includes && (~alu_clear_pipeline) |
r_alu_pc_valid <= 1'b1; |
else if ((~alu_busy)||(clear_pipeline)) |
r_alu_pc_valid <= 1'b0; |
assign alu_pc_valid = (r_alu_pc_valid)&&(~alu_busy); |
always @(posedge i_clk) |
if (i_rst) |
mem_pc_valid <= 1'b0; |
1638,7 → 1639,9
else if ((new_pc)||((~dcd_stalled)&&(pf_valid))) |
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1}; |
`else |
else if (((alu_pc_valid)&&(~clear_pipeline))||(mem_pc_valid)) |
else if ((alu_gie==gie)&&( |
((alu_pc_valid)&&(~clear_pipeline)) |
||(mem_pc_valid))) |
pf_pc <= alu_pc; |
`endif |
|
1707,20 → 1710,45
`ifdef DEBUG_SCOPE |
always @(posedge i_clk) |
o_debug <= { |
/* |
o_break, i_wb_err, pf_pc[1:0], |
// |
flags, |
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid, |
// |
pf_valid, dcdvalid, opvalid, alu_valid, |
// |
mem_valid, |
op_ce, alu_ce, mem_ce, |
// |
master_ce, opvalid_alu, opvalid_mem, |
master_ce, |
opvalid_alu, opvalid_mem, alu_stall, |
// |
alu_stall, mem_busy, op_pipe, mem_pipe_stalled, |
mem_busy, op_pipe, |
`ifdef OPT_PIPELINED_BUS_ACCESS |
mem_pipe_stalled, |
`else |
1'b0, |
`endif |
mem_we, |
// |
// ((opvalid_alu)&&(alu_stall)) |
// ||((opvalid_mem)&&(~op_pipe)&&(mem_busy)) |
// ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled))); |
// opA[23:20], opA[3:0], |
gie, sleep, wr_reg_ce, wr_reg_vl[4:0] |
*/ |
|
o_break, i_wb_err, o_wb_gbl_cyc, o_wb_gbl_stb, |
pf_valid, dcdvalid, opvalid, alu_valid, |
mem_valid, dcd_ce, op_ce, alu_ce, |
mem_ce, |
dcd_illegal, gie, sleep, |
{ ((o_wb_gbl_cyc)&&(o_wb_gbl_stb)&&(o_wb_we)) |
? o_wb_data[15:0] |
: ((o_wb_gbl_cyc)&&(o_wb_gbl_stb)&&(~o_wb_we)&&(i_wb_ack)) |
? i_wb_data[15:0] |
: o_wb_addr[15:0] |
} |
/* |
i_rst, master_ce, (new_pc), |
((dcd_early_branch)&&(dcdvalid)), |