OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /s6soc/trunk/rtl
    from Rev 4 to Rev 5
    ↔ Reverse comparison
  •

Rev 4 → Rev 5

/alttop.v
0,0 → 1,204
`timescale 10ns / 100ps
////////////////////////////////////////////////////////////////////////////////
//
// Filename: alttop.v
//
// Project: CMod S6 System on a Chip, ZipCPU demonstration project
//
// Purpose: This is an alternate toplevel configuration for the CMod S6
// project. Basically, the CMod S6 has so little logic within
// it, that there's no logic available for in situ reprogramming. This
// toplevel file serves that purpose: It provides full configuration
// access, via the UART port, for the flash (read and write), and full
// test level access for all of the devices on the board. What it
// doesn't have, however, is the ZipCPU. (I had to give up something to
// get the logic back for this purpose!)
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
module alttop(i_clk_8mhz,
o_qspi_cs_n, o_qspi_sck, io_qspi_dat,
i_btn, o_led, o_pwm, o_pwm_shutdown_n, o_pwm_gain,
i_uart, o_uart, i_uart_cts, o_uart_rts,
i_kp_row, o_kp_col,
i_gpio, o_gpio,
io_scl, io_sda);
input i_clk_8mhz;
//
// Quad SPI Flash
output wire o_qspi_cs_n;
output wire o_qspi_sck;
inout wire [3:0] io_qspi_dat;
//
// General purpose I/O
input [1:0] i_btn;
output wire [3:0] o_led;
output wire o_pwm, o_pwm_shutdown_n, o_pwm_gain;
//
// and our serial port
input i_uart;
output wire o_uart;
// and it's associated control wires
input i_uart_cts;
output wire o_uart_rts;
// Our keypad
input [3:0] i_kp_row;
output wire [3:0] o_kp_col;
// and our GPIO
input [15:2] i_gpio;
output wire [15:2] o_gpio;
// and our I2C port
inout io_scl, io_sda;
 
//
// Clock management
//
// Generate a usable clock for the rest of the board to run at.
//
wire ck_zero_0, clk_s;
 
// Clock frequency = (20 / 2) * 8Mhz = 80 MHz
// Clock period = 12.5 ns
DCM_SP #(
.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(2), // Here's the divide by two
.CLKFX_MULTIPLY(20), // and here's the multiply by 20
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(125.0),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DLL_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("TRUE")
) u0( .CLKIN(i_clk_8mhz),
.CLK0(ck_zero_0),
.CLKFB(ck_zero_0),
.CLKFX(clk_s),
.PSEN(1'b0),
.RST(1'b0));
 
//
// Generate active-high reset.
//
// Actually, we don't. Instead, let this board reset through
// the reconfiguration/power on process and we never use this
// wire.
//
/*
reg r_reset;
initial r_reset = 1'b1;
always @(posedge i_clk_12mhz)
r_reset <= 1'b0;
*/
assign reset_s = 1'b0;
 
 
//
// The UART serial interface
//
// Perhaps this should be part of our simulation model as well.
// For historical reasons, internal to Gisselquist Technology,
// this has remained separate from the simulation, allowing the
// simulation to bypass whether or not these two functions work.
//
wire rx_stb, tx_stb;
wire [7:0] rx_data, tx_data;
wire tx_busy;
wire [29:0] uart_setup;
 
wire rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, tx_break;
assign tx_break = 1'b0;
rxuart rcvuart(clk_s, reset_s, uart_setup,
i_uart, rx_stb, rx_data,
rx_break, rx_parity_err, rx_frame_err, rx_ck_uart);
txuart tcvuart(clk_s, reset_s, uart_setup, tx_break, tx_stb, tx_data,
o_uart, i_uart_cts, tx_busy);
 
 
//
// ALT-BUSMASTER
//
// Busmaster is so named because it contains the wishbone
// interconnect that all of the internal devices are hung off of.
// To reconfigure this device for another purpose, usually
// the busmaster module (i.e. the interconnect) is all that needs
// to be changed: either to add more devices, or to remove them.
//
// This is an alternate version of the busmaster interface,
// offering no ZipCPU and access to reprogramming via the flash.
//
wire [3:0] qspi_dat;
wire [1:0] qspi_bmod;
wire [15:0] w_gpio;
 
altbusmaster slavedbus(clk_s, reset_s,
// External ... bus control (if enabled)
rx_stb, rx_data, tx_stb, tx_data, tx_busy, o_uart_rts,
// SPI/SD-card flash
o_qspi_cs_n, o_qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod,
// Board lights and switches
i_btn, o_led, o_pwm, { o_pwm_shutdown_n, o_pwm_gain },
// Keypad connections
i_kp_row, o_kp_col,
// UART control
uart_setup,
// GPIO lines
{ i_gpio, io_scl, io_sda }, w_gpio
);
 
//
// Quad SPI support
//
// Supporting a Quad SPI port requires knowing which direction the
// wires are going at each instant, whether the device is in full
// Quad mode in, full quad mode out, or simply the normal SPI
// port with one wire in and one wire out. This utilizes our
// control wires (qspi_bmod) to set the output lines appropriately.
//
assign io_qspi_dat = (~qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
:((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
 
//
// I2C support
//
// Supporting I2C requires a couple quick adjustments to our
// GPIO lines. Specifically, we'll allow that when the output
// (i.e. w_gpio) pins are high, then the I2C lines float. They
// will be (need to be) pulled up by a resistor in order to
// match the I2C protocol, but this change makes them look/act
// more like GPIO pins.
//
assign io_sda = (w_gpio[0]) ? 1'bz : 1'b0;
assign io_scl = (w_gpio[1]) ? 1'bz : 1'b0;
assign o_gpio[15:2] = w_gpio[15:2];
 
endmodule
/altbusmaster.v
0,0 → 1,410
////////////////////////////////////////////////////////////////////////////////
//
// Filename: altbusmaster.v
//
// Project: CMod S6 System on a Chip, ZipCPU demonstration project
//
// Purpose:
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
//
`include "builddate.v"
//
`define IMPLEMENT_ONCHIP_RAM
`ifndef VERILATOR
`define FANCY_ICAP_ACCESS
`endif
`define FLASH_ACCESS
`define CFG_SCOPE
`define INCLUDE_RTC // 2017 slice LUTs w/o, 2108 with (!!!)
module altbusmaster(i_clk, i_rst,
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
o_uart_rts,
// The SPI Flash lines
o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
// The board I/O
i_btn, o_led, o_pwm, o_pwm_aux,
// Keypad connections
i_kp_row, o_kp_col,
// UART control
o_uart_setup,
// GPIO lines
i_gpio, o_gpio);
parameter ZIP_ADDRESS_WIDTH=23, ZA=ZIP_ADDRESS_WIDTH,
CMOD_ZIPCPU_RESET_ADDRESS=23'h400100,
BUS_ADDRESS_WIDTH=23, BAW=23; // 24bits->2,258,23b->2181
input i_clk, i_rst;
// The bus commander, via an external JTAG port
input i_rx_stb;
input [7:0] i_rx_data;
output wire o_tx_stb;
output wire [7:0] o_tx_data;
input i_tx_busy;
output wire o_uart_rts;
// SPI flash control
output wire o_qspi_cs_n, o_qspi_sck;
output wire [3:0] o_qspi_dat;
input [3:0] i_qspi_dat;
output wire [1:0] o_qspi_mod;
// Board I/O
input [1:0] i_btn;
output wire [3:0] o_led;
output wire o_pwm;
output wire [1:0] o_pwm_aux;
// Keypad
input [3:0] i_kp_row;
output wire [3:0] o_kp_col;
// UART control
output wire [29:0] o_uart_setup;
// GPIO liines
input [15:0] i_gpio;
output wire [15:0] o_gpio;
 
 
//
//
// Master wishbone wires
//
//
wire wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
wire [31:0] wb_data, wb_idata;
wire [(BAW-1):0] wb_addr;
wire [5:0] io_addr;
assign io_addr = {
wb_addr[22], // Flash
wb_addr[13], // RAM
wb_addr[11], // RTC
wb_addr[10], // CFG
wb_addr[ 9], // SCOPE
wb_addr[ 8] }; // I/O
 
// Wires going to devices
// And then headed back home
wire w_interrupt;
// Oh, and the debug control for the ZIP CPU
wire zip_dbg_ack, zip_dbg_stall;
wire [31:0] zip_dbg_data;
 
 
//
//
// The BUS master (source): The WB to UART conversion bus
//
//
wire zip_cyc, zip_stb, zip_we, zip_cpu_int;
wire [(ZA-1):0] w_zip_addr;
wire [(BAW-1):0] zip_addr;
wire [31:0] zip_data;
// and then coming from devices
wire zip_ack, zip_stall, zip_err;
wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
wire [(BAW-1):0] dwb_addr;
wire [31:0] dwb_odata;
 
// wire [31:0] zip_debug;
wbubus busbdriver(i_clk, i_rx_stb, i_rx_data,
// The wishbone interface
wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
wb_ack, wb_stall, wb_err, wb_idata,
w_interrupt,
// Provide feedback to the UART
o_tx_stb, o_tx_data, i_tx_busy);
assign o_uart_rts = (~rx_rdy);
 
generate
if (ZA < BAW)
assign wb_addr = { {(BAW-ZA){1'b0}}, w_wbu_addr };
else
assign wb_addr = w_zip_addr;
endgenerate
 
wire io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
rtc_sel, none_sel, many_sel;
wire flash_ack, scop_ack, cfg_ack, mem_ack;
wire rtc_ack, rtc_stall;
`ifdef INCLUDE_RTC
assign rtc_stall = 1'b0;
`endif
wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
reg io_ack, uart_ack;
 
wire [31:0] flash_data, scop_data, cfg_data, mem_data, pwm_data,
spio_data, gpio_data, uart_data;
reg [31:0] io_data;
reg [(BAW-1):0] bus_err_addr;
 
assign wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
||(uart_ack)
`ifdef INCLUDE_RTC
||(rtc_ack)
`endif
||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
assign wb_stall = ((io_sel)&&(io_stall))
||((scop_sel)&&(scop_stall))
||((cfg_sel)&&(cfg_stall))
||((mem_sel)&&(mem_stall))
`ifdef INCLUDE_RTC
||((rtc_sel)&&(rtc_stall))
`endif
||((flash_sel||flctl_sel)&&(flash_stall));
// (none_sel)&&(1'b0)
 
/*
assign wb_idata = (io_ack)?io_data
: ((scop_ack)?scop_data
: ((cfg_ack)?cfg_data
: ((mem_ack)?mem_data
: ((flash_ack)?flash_data
: 32'h00))));
*/
assign wb_idata = (io_ack|scop_ack)?((io_ack )? io_data : scop_data)
: ((cfg_ack|uart_ack) ? ((cfg_ack)?cfg_data: uart_data)
: ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
: flash_data)); // if (flash_ack)
assign wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
 
// Addresses ...
// 0000 xxxx configuration/control registers
// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
assign io_sel =((wb_cyc)&&(io_addr[5:0]==6'h1));
assign flctl_sel= 1'b0; // ((wb_cyc)&&(io_addr[5:1]==5'h1));
assign scop_sel =((wb_cyc)&&(io_addr[5:1]==5'h1));
assign cfg_sel =((wb_cyc)&&(io_addr[5:2]==4'h1));
// zip_sel is not on the bus at this point
`ifdef INCLUDE_RTC
assign rtc_sel =((wb_cyc)&&(io_addr[5:3]==3'h1));
`endif
assign mem_sel =((wb_cyc)&&(io_addr[5:4]==2'h1));
assign flash_sel=((wb_cyc)&&(io_addr[5]));
 
assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
/*
assign many_sel =((wb_cyc)&&(wb_stb)&&(
{3'h0, io_sel}
+{3'h0, flctl_sel}
// +{3'h0, scop_sel}
+{3'h0, cfg_sel}
+{3'h0, mem_sel}
+{3'h0, flash_sel} > 1));
*/
assign many_sel = 1'b0;
 
wire many_ack;
assign many_ack =((wb_cyc)&&(
{3'h0, io_ack}
+{3'h0, scop_ack}
+{3'h0, cfg_ack}
`ifdef INCLUDE_RTC
+{3'h0, rtc_ack}
`endif
+{3'h0, mem_ack}
+{3'h0, flash_ack} > 1));
 
wire flash_interrupt, scop_interrupt, tmra_int, tmrb_int,
rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int;
 
 
//
//
//
reg rx_rdy;
wire [10:0] int_vector;
assign int_vector = { gpio_int, pwm_int, keypad_int,
1'b0, rx_rdy, tmrb_int, tmra_int,
rtc_interrupt, scop_interrupt,
wb_err, button_int };
 
wire [31:0] pic_data;
icontrol #(11) pic(i_clk, 1'b0,
(wb_cyc)&&(wb_stb)&&(io_sel)
&&(wb_addr[3:0]==4'h0)&&(wb_we),
wb_data, pic_data, int_vector, w_interrupt);
 
initial bus_err_addr = `DATESTAMP;
always @(posedge i_clk)
if (wb_err)
bus_err_addr <= wb_addr;
 
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
wire [31:0] timer_a, timer_b;
ziptimer zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
wb_we, wb_data, zta_ack, zta_stall, timer_a,
tmra_int);
ziptimer zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
tmrb_int);
 
wire [31:0] rtc_data;
`ifdef INCLUDE_RTC
wire rtcd_ack, rtcd_stall, ppd;
// rtcdate thedate(i_clk, ppd, wb_cyc, (wb_stb)&&(io_sel), wb_we,
// wb_data, rtcd_ack, rtcd_stall, date_data);
reg r_rtc_ack;
initial r_rtc_ack = 1'b0;
always @(posedge i_clk)
r_rtc_ack <= ((wb_stb)&&(rtc_sel));
assign rtc_ack = r_rtc_ack;
 
rtclight
#(32'h35afe5) // 80 MHz clock
thetime(i_clk, wb_cyc,
((wb_stb)&&(rtc_sel)), wb_we,
{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
rtc_interrupt, ppd);
`else
assign rtc_interrupt = 1'b0;
assign rtc_data = 32'h00;
assign rtc_ack = 1'b0;
`endif
 
always @(posedge i_clk)
case(wb_addr[3:0])
4'h0: io_data <= pic_data;
4'h1: io_data <= { {(32-BAW){1'b0}}, bus_err_addr };
4'h2: io_data <= timer_a;
4'h3: io_data <= timer_b;
4'h4: io_data <= pwm_data;
4'h5: io_data <= spio_data;
4'h6: io_data <= gpio_data;
4'h7: io_data <= uart_data;
default: io_data <= `DATESTAMP;
// 4'h8: io_data <= `DATESTAMP;
endcase
always @(posedge i_clk)
io_ack <= (wb_cyc)&&(wb_stb)&&(io_sel);
assign io_stall = 1'b0;
 
wire pwm_ack, pwm_stall;
wbpwmaudio theaudio(i_clk, wb_cyc,
((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h4)), wb_we,
1'b0, wb_data,
pwm_ack, pwm_stall, pwm_data, o_pwm, o_pwm_aux,
pwm_int);
 
//
// Special Purpose I/O: Keypad, button, LED status and control
//
spio thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),wb_we,
wb_data, spio_data, o_kp_col, i_kp_row, i_btn, o_led,
keypad_int, button_int);
 
//
// General purpose (sort of) I/O: (Bottom two bits robbed in each
// direction for an I2C link at the toplevel.v design)
//
wbgpio #(16,16,16'hffff) thegpio(i_clk, wb_cyc,
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h6), wb_we,
wb_data, gpio_data, i_gpio, o_gpio, gpio_int);
 
//
//
// Rudimentary serial port control
//
reg [7:0] r_rx_data;
// Baud rate is set by clock rate / baud rate.
// Thus, 80MHz / 115200MBau
// = 694.4, or about 0x2b6.
// although the CPU might struggle to keep up at this speed without a
// hardware buffer.
//
// We'll add the flag for two stop bits.
assign o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
 
 
 
 
//
// FLASH MEMORY CONFIGURATION ACCESS
//
wire flash_cs_n, flash_sck, flash_mosi;
wbqspiflashp #(24) flashmem(i_clk,
wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
wb_addr[21:0], wb_data,
flash_ack, flash_stall, flash_data,
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
flash_interrupt);
 
//
// MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
//
wire [31:0] cfg_scope;
`ifdef FANCY_ICAP_ACCESS
wbicape6 fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
wb_addr[5:0], wb_data,
cfg_ack, cfg_stall, cfg_data,
cfg_scope);
`else
reg r_cfg_ack;
always @(posedge i_clk)
r_cfg_ack <= (wb_cyc)&&(cfg_sel)&&(wb_stb);
assign cfg_ack = r_cfg_ack;
assign cfg_stall = 1'b0;
assign cfg_data = 32'h00;
assign cfg_scope = 32'h00;
`endif
 
 
//
// ON-CHIP RAM MEMORY ACCESS
//
memdev #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
 
//
//
// WISHBONE SCOPE
//
//
//
//
wire [31:0] scop_cfg_data;
wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
`ifdef CFG_SCOPE
wire scop_cfg_trigger;
assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
// Wishbone interface
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
wb_we, wb_addr[0], wb_data,
scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
scop_cfg_interrupt);
`endif
 
assign scop_interrupt = scop_cfg_interrupt;
assign scop_ack = scop_cfg_ack;
assign scop_stall = scop_cfg_stall;
assign scop_data = scop_cfg_data;
 
endmodule
 
// 0x8684 interrupts ...???

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.