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URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /s6soc/trunk
    from Rev 25 to Rev 26
    ↔ Reverse comparison
  •

Rev 25 → Rev 26

/sw/host/zipload.cpp
305,7 → 305,7
 
current_section++;
 
r[i]->m_start = phdr.p_vaddr;
r[i]->m_start = phdr.p_paddr;
r[i]->m_len = phdr.p_filesz/ sizeof(FPGA::BUSW);
 
current_offset += phdr.p_memsz + sizeof(SECTION);
349,7 → 349,7
 
int main(int argc, char **argv) {
int skp=0;
bool permit_raw_files = false;
bool permit_raw_files = false, debug_only = false;
unsigned entry = RAMBASE;
FLASHDRVR *flash = NULL;
const char *bitfile = NULL, *altbitfile = NULL;
363,12 → 363,22
for(int argn=0; argn<argc-skp; argn++) {
if (argv[argn+skp][0] == '-') {
switch(argv[argn+skp][1]) {
case 'd':
debug_only = true;
break;
case 'h':
usage();
exit(EXIT_SUCCESS);
break;
case 'r':
permit_raw_files = true;
break;
default:
fprintf(stderr, "Unknown option, -%c\n\n",
argv[argn+skp][0]);
usage();
exit(EXIT_FAILURE);
break;
} skp++; argn--;
} else { // Check for bit files
int sl = strlen(argv[argn+skp]);
409,13 → 419,15
// Set the flash buffer to all ones
memset(fbuf, -1, FLASHWORDS*sizeof(fbuf[0]));
 
{
if (debug_only) {
m_fpga = NULL;
} else {
char szSel[64];
strcpy(szSel, "SN:210282768825");
m_fpga = new FPGA(new DEPPI(szSel));
}
 
flash = new FLASHDRVR(m_fpga);
flash = (debug_only)?NULL : new FLASHDRVR(m_fpga);
 
// First, see if we need to load a bit file
if (bitfile) {
436,7 → 448,7
assert(fbuf[4] == 0x0665599aa);
 
printf("Loading: %s\n", bitfile);
if (!flash->write(CONFIG_ADDRESS, len, &fbuf[CONFIG_ADDRESS-SPIFLASH], true)) {
if ((flash)&&(!flash->write(CONFIG_ADDRESS, len, &fbuf[CONFIG_ADDRESS-SPIFLASH], true))) {
fprintf(stderr, "Could not write primary bitfile\n");
exit(EXIT_FAILURE);
}
452,7 → 464,7
fclose(fp);
printf("Loading: %s\n", altbitfile);
 
if (!flash->write(ALTCONFIG_ADDRESS, len, &fbuf[ALTCONFIG_ADDRESS-SPIFLASH], true)) {
if ((flash)&&(!flash->write(ALTCONFIG_ADDRESS, len, &fbuf[ALTCONFIG_ADDRESS-SPIFLASH], true))) {
fprintf(stderr, "Could not write alternate bitfile\n");
exit(EXIT_FAILURE);
}
519,11 → 531,13
secp->m_len*sizeof(FPGA::BUSW));
}
}
if (!flash->write(startaddr, codelen, &fbuf[startaddr-SPIFLASH], true)) {
if ((flash)&&(!flash->write(startaddr, codelen, &fbuf[startaddr-SPIFLASH], true))) {
fprintf(stderr, "ERR: Could not write program to flash\n");
exit(EXIT_FAILURE);
}
m_fpga->readio(R_VERSION); // Check for bus errors
} else if (!flash)
printf("flash->write(%08x, %d, ... );\n", startaddr,
codelen);
if (m_fpga) m_fpga->readio(R_VERSION); // Check for bus errors
 
// Now ... how shall we start this CPU?
printf("The CPU should be fully loaded, you may now start\n");
536,7 → 550,7
exit(-2);
}
 
delete m_fpga;
if (m_fpga) delete m_fpga;
 
return EXIT_SUCCESS;
}

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