URL
https://opencores.org/ocsvn/s6soc/s6soc/trunk
Subversion Repositories s6soc
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/s6soc/trunk
- from Rev 45 to Rev 46
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Rev 45 → Rev 46
/rtl/wbicape6.v
File deleted
/rtl/rtclight.v
File deleted
/rtl/wbicapesimple.v
File deleted
/rtl/rtcdate.v
File deleted
/rtl/Makefile
1,72 → 1,72
################################################################################ |
# |
# Filename: rtl/Makefile |
# |
# Project: CMod S6 System on a Chip, ZipCPU demonstration project |
# |
# Purpose: This makefile builds a verilator simulation of the zipsystem. |
# It does not make the system within Vivado or Quartus. |
# |
# Creator: Dan Gisselquist, Ph.D. |
# Gisselquist Technology, LLC |
# |
## |
## Filename: rtl/Makefile |
## |
## Project: CMod S6 System on a Chip, ZipCPU demonstration project |
## |
## Purpose: This makefile builds a verilator simulation of the zipsystem. |
## It does not make the system within Vivado or Quartus. |
## |
## Creator: Dan Gisselquist, Ph.D. |
## Gisselquist Technology, LLC |
## |
################################################################################ |
## |
## Copyright (C) 2015-2016, Gisselquist Technology, LLC |
## |
## This program is free software (firmware): you can redistribute it and/or |
## modify it under the terms of the GNU General Public License as published |
## by the Free Software Foundation, either version 3 of the License, or (at |
## your option) any later version. |
## |
## This program is distributed in the hope that it will be useful, but WITHOUT |
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
## for more details. |
## |
## You should have received a copy of the GNU General Public License along |
## with this program. (It's in the $(ROOT)/doc directory, run make with no |
## target there if the PDF file isn't present.) If not, see |
## <http://www.gnu.org/licenses/> for a copy. |
## |
## License: GPL, v3, as defined and found on www.gnu.org, |
## http://www.gnu.org/licenses/gpl.html |
## |
# |
# Copyright (C) 2015-2016, Gisselquist Technology, LLC |
# |
# This program is free software (firmware): you can redistribute it and/or |
# modify it under the terms of the GNU General Public License as published |
# by the Free Software Foundation, either version 3 of the License, or (at |
# your option) any later version. |
# |
# This program is distributed in the hope that it will be useful, but WITHOUT |
# ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
# for more details. |
# |
# You should have received a copy of the GNU General Public License along |
# with this program. (It's in the $(ROOT)/doc directory, run make with no |
# target there if the PDF file isn't present.) If not, see |
# <http://www.gnu.org/licenses/> for a copy. |
# |
# License: GPL, v3, as defined and found on www.gnu.org, |
# http://www.gnu.org/licenses/gpl.html |
# |
# |
################################################################################ |
# |
# |
## |
## |
.PHONY: all |
all: busmaster altbusmaster |
|
YYMMDD=`date +%Y%m%d` |
CPUD := cpu |
RAWZIP := zipbones.v zipcpu.v cpudefs.v \ |
prefetch.v idecode.v cpuops.v memops.v \ |
wbdblpriarb.v |
ZIPSRC := $(addprefix $(CPUD)/,$(RAWZIP)) |
BUSSRC := builddate.v llqspi.v wbicape6.v wbicapesimple.v wbscope.v \ |
memdev.v rtclight.v spio.v wbgpio.v wbpwmaudio.v |
BUSSRC := builddate.v llqspi.v wbscope.v memdev.v spio.v wbgpio.v wbpwmaudio.v |
MAINSRC := busmaster.v builddate.v flash_config.v wbqspiflash.v \ |
$(BUSSRC) $(ZIPSRC) |
# toplevel.v rxuart.v txuart.v |
ALTSRC := altbusmaster.v builddate.v flash_config.v wbqspiflash.v \ |
$(BUSSRC) wbdeppsimple.v |
$(BUSSRC) wbubus.v |
# alttop.v rxuart.v txuart.v |
# rtcdate.v wbubus.v |
|
VOBJ := obj_dir |
|
$(VOBJ)/Vbusmaster.cpp: $(MAINSRC) |
verilator -cc -y $(CPUD) busmaster.v |
verilator -trace -cc -y $(CPUD) busmaster.v |
$(VOBJ)/Vbusmaster.h: $(VOBJ)/Vbusmaster.cpp |
|
$(VOBJ)/Valtbusmaster.cpp: $(ALTSRC) |
verilator -cc -y $(CPUD) altbusmaster.v |
verilator -trace -cc -y $(CPUD) altbusmaster.v |
$(VOBJ)/Valtbusmaster.h: $(VOBJ)/Valtbusmaster.cpp |
|
$(VOBJ)/Vbusmaster__ALL.a: $(VOBJ)/Vbusmaster.cpp $(VOBJ)/Vbusmaster.h |
cd $(VOBJ); make --no-print-directory -f Vbusmaster.mk |
|
$(VOBJ)/V%__ALL.a: $(VOBJ)/V%.mk |
cd $(VDIRFB); make -f V$*.mk |
|
$(VOBJ)/Valtbusmaster__ALL.a: $(VOBJ)/Valtbusmaster.cpp $(VOBJ)/Valtbusmaster.h |
cd $(VOBJ); make --no-print-directory -f Valtbusmaster.mk |
|
/rtl/altbusmaster.v
4,7 → 4,11
// |
// Project: CMod S6 System on a Chip, ZipCPU demonstration project |
// |
// Purpose: |
// Purpose: Because the S6 is *so* small logic-wise, the logic of setting up |
// a project/design was separated from the logic of the design |
// itself. Hence, this is the "setup" design. It allows us to test various |
// components from the command line interface, as well as erasing and |
// programming the flash in order to set up the actual device interface. |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
11,7 → 15,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
35,20 → 39,12
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// |
`include "builddate.v" |
// |
// `define IMPLEMENT_ONCHIP_RAM |
`ifndef VERILATOR |
`define FANCY_ICAP_ACCESS |
`endif |
`define FLASH_ACCESS |
`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses |
// `define DBG_SCOPE // About 204 LUTs, at 2^6 addresses |
// `define COMPRESSED_SCOPE |
`define INCLUDE_SECOND_TIMER |
`define SECOND_TIMER_IS_WATCHDOG |
`define INCLUDE_RTC // About 90 LUTs |
`define FULL_BUSERR_CALCULATION |
`define WBUBUS |
module altbusmaster(i_clk, i_rst, |
// DEPP I/O Control |
56,7 → 52,7
i_depp_data, o_depp_data, o_depp_wait, |
// External UART interface |
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy, |
o_uart_cts, |
o_uart_rts_n, |
// The SPI Flash lines |
o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod, |
// The board I/O |
69,6 → 65,13
i_gpio, o_gpio); |
parameter BUS_ADDRESS_WIDTH=23, |
BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181 |
// 2^14 bytes requires a LGMEMSZ of 14, and 12 address bits ranging from |
// 0 to 11. As with many other devices, the wb_cyc line is more for |
// form than anything else--it is ignored by the memory itself. |
localparam LGMEMSZ=14; // Takes 8 BLKRAM16 elements for LGMEMSZ=14 |
// As with the memory size, the flash size is also measured in log_2 of |
// the number of bytes. |
localparam LGFLASHSZ = 24; |
input i_clk, i_rst; |
// The bus commander, via an external DEPP port |
input i_depp_astb_n, i_depp_dstb_n, i_depp_write_n; |
81,7 → 84,7
output reg o_tx_stb; |
output reg [7:0] o_tx_data; |
input i_tx_busy; |
output wire o_uart_cts; |
output wire o_uart_rts_n; |
// SPI flash control |
output wire o_qspi_cs_n, o_qspi_sck; |
output wire [3:0] o_qspi_dat; |
96,7 → 99,7
input [3:0] i_kp_row; |
output wire [3:0] o_kp_col; |
// UART control |
output wire [29:0] o_uart_setup; |
output wire [30:0] o_uart_setup; |
// GPIO liines |
input [15:0] i_gpio; |
output wire [15:0] o_gpio; |
110,14 → 113,6
wire wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err; |
wire [31:0] wb_data, wb_idata, w_wbu_addr; |
wire [(BAW-1):0] wb_addr; |
wire [5:0] io_addr; |
assign io_addr = { |
wb_addr[22], // Flash |
wb_addr[13], // RAM |
wb_addr[11], // RTC |
wb_addr[10], // CFG |
wb_addr[ 9], // SCOPE |
wb_addr[ 8] }; // I/O |
|
// Wires going to devices |
// And then headed back home |
136,7 → 131,8
dep_rx_stb, dep_rx_data, |
dep_tx_stb, dep_tx_data, dep_tx_busy); |
|
wbubus busbdriver(i_clk, |
wire bus_dbg; |
wbubus #(22) busbdriver(i_clk, |
// i_rx_stb, i_rx_data, // UART control |
dep_rx_stb, dep_rx_data, // DEPP control |
// The wishbone interface |
144,10 → 140,18
wb_ack, wb_stall, wb_err, wb_idata, |
w_interrupt, |
// Provide feedback to the DEPP interface |
dep_tx_stb, dep_tx_data, dep_tx_busy); |
dep_tx_stb, dep_tx_data, dep_tx_busy, |
bus_dbg); |
// // Provide feedback to the UART |
// o_tx_stb, o_tx_data, i_tx_busy |
// assign o_uart_rts = (~rx_rdy); |
|
wire [30:0] bus_debug; |
assign bus_debug = { |
wb_cyc, wb_stb, wb_ack, wb_stall, |
wb_addr[7:0], |
dep_rx_stb, (~dep_tx_busy)&&(dep_tx_stb), dep_tx_stb, |
dep_rx_data, dep_tx_data }; |
`else |
// |
// |
162,20 → 166,14
w_interrupt); |
`endif |
|
generate |
if (BAW < 32) |
assign wb_addr = w_wbu_addr[(BAW-1):0]; |
else |
assign wb_addr = w_wbu_addr; |
endgenerate |
assign wb_addr = w_wbu_addr[(BAW-1):0]; |
|
wire io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel, |
rtc_sel, none_sel, many_sel; |
|
// Signals to build/detect bus errors |
wire none_sel, many_sel; |
|
wire io_sel, flash_sel, flctl_sel, scop_sel, mem_sel; |
wire flash_ack, scop_ack, cfg_ack, mem_ack, many_ack; |
wire rtc_ack, rtc_stall; |
`ifdef INCLUDE_RTC |
assign rtc_stall = 1'b0; |
`endif |
wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall; |
reg io_ack; |
|
183,92 → 181,215
spio_data, gpio_data, uart_data; |
reg [31:0] io_data; |
reg [(BAW-1):0] bus_err_addr; |
// |
// wb_ack |
// |
// The returning wishbone ack is equal to the OR of every component that |
// might possibly produce an acknowledgement, gated by the CYC line. To |
// add new components, OR their acknowledgements in here. |
// |
// Note the reference to none_sel. If nothing is selected, the result |
// is an error. Here, we do nothing more than insure that the erroneous |
// request produces an ACK ... if it was ever made, rather than stalling |
// the bus. |
// |
|
assign wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack) |
`ifdef INCLUDE_RTC |
||(rtc_ack) |
`endif |
|
assign wb_ack = (wb_cyc)&&((io_ack)||(scop_ack) |
||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1))); |
|
// |
// wb_stall |
// |
// The returning wishbone stall line really depends upon what device |
// is requested. Thus, if a particular device is selected, we return |
// the stall line for that device. |
// |
// To add a new device, simply and that devices select and stall lines |
// together, and OR the result with the massive OR logic below. |
// |
assign wb_stall = ((io_sel)&&(io_stall)) |
||((scop_sel)&&(scop_stall)) |
||((cfg_sel)&&(cfg_stall)) |
||((mem_sel)&&(mem_stall)) |
`ifdef INCLUDE_RTC |
||((rtc_sel)&&(rtc_stall)) |
`endif |
||((flash_sel||flctl_sel)&&(flash_stall)); |
// (none_sel)&&(1'b0) |
|
/* |
assign wb_idata = (io_ack)?io_data |
: ((scop_ack)?scop_data |
: ((cfg_ack)?cfg_data |
: ((mem_ack)?mem_data |
: ((flash_ack)?flash_data |
: 32'h00)))); |
*/ |
// |
// wb_idata |
// |
// This is the data returned on the bus. Here, we select between a |
// series of bus sources to select what data to return. The basic |
// logic is simply this: the data we return is the data for which the |
// ACK line is high. |
// |
// The last item on the list is chosen by default if no other ACK's are |
// true. Although we might choose to return zeros in that case, by |
// returning something we can skimp a touch on the logic. |
// |
// To add another device, add another ack check, and another closing |
// parenthesis. |
// |
assign wb_idata = (io_ack|scop_ack)?((io_ack )? io_data : scop_data) |
: ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data) |
: ((cfg_ack) ? cfg_data : flash_data));//if (flash_ack) |
assign wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack; |
: ((mem_ack)?(mem_data) |
: flash_data); |
|
// |
// wb_err |
// |
// This is the bus error signal. It should never be true, but practice |
// teaches us otherwise. Here, we allow for three basic errors: |
// |
// 1. STB is true, but no devices are selected |
// |
// This is the null pointer reference bug. If you try to access |
// something on the bus, at an address with no mapping, the bus |
// should produce an error--such as if you try to access something |
// at zero. |
// |
// 2. STB is true, and more than one device is selected |
// |
// (This can be turned off, if you design this file well. For |
// this line to be true means you have a design flaw.) |
// |
// 3. If more than one ACK is every true at any given time. |
// |
// This is a bug of bus usage, combined with a subtle flaw in the |
// WB pipeline definition. You can issue bus requests, one per |
// clock, and if you cross device boundaries with your requests, |
// you may have things come back out of order (not detected here) |
// or colliding on return (detected here). The solution to this |
// problem is to make certain that any burst request does not cross |
// device boundaries. This is a requirement of whoever (or |
// whatever) drives the bus. |
// |
assign wb_err = ((wb_stb)&&(none_sel || many_sel)) || many_ack; |
|
// Addresses ... |
// 0000 xxxx configuration/control registers |
// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps |
assign io_sel =((wb_cyc)&&(io_addr[5:0]==6'h1)); |
assign scop_sel =((wb_cyc)&&(io_addr[5:0]==6'h2)); |
assign flctl_sel=((wb_cyc)&&(io_addr[5:0]==6'h3)); |
assign cfg_sel =((wb_cyc)&&(io_addr[5:1]==5'h2)); |
// zip_sel is not on the bus at this point |
`ifdef INCLUDE_RTC |
assign rtc_sel =((wb_cyc)&&(io_addr[5:3]==3'h1)); |
`endif |
assign mem_sel =((wb_cyc)&&(io_addr[5:4]==2'h1)); |
assign flash_sel=((wb_cyc)&&(io_addr[5])); |
// |
// dev_sel |
// |
// The device select lines |
// |
// |
|
`ifdef FULL_BUSERR_CALCULATION |
assign none_sel =((wb_cyc)&&(wb_stb)&& |
((io_addr==6'h0) |
||((~io_addr[5])&&(|wb_addr[22:14])) |
||((io_addr[5:4]==2'b00)&&(|wb_addr[12]))) |
); |
assign many_sel =((wb_cyc)&&(wb_stb)&&( |
{3'h0, io_sel} |
+{3'h0, flctl_sel} |
+{3'h0, scop_sel} |
+{3'h0, cfg_sel} |
+{3'h0, rtc_sel} |
+{3'h0, mem_sel} |
+{3'h0, flash_sel} > 1)); |
|
assign many_ack =((wb_cyc)&&( |
{3'h0, io_ack} |
+{3'h0, scop_ack} |
+{3'h0, cfg_ack} |
`ifdef INCLUDE_RTC |
+{3'h0, rtc_ack} |
// |
// The skipaddr bitfield below is our cheaters way of handling |
// device selection. We grab particular wires from the bus to do |
// this, and ignore all others. While this may lead to some |
// surprising results for the CPU when it tries to access an |
// inappropriate address, it also minimizes our logic while also |
// placing every address at the right address. The only problem is |
// ... devices will also be at some unexpected addresses, but ... this |
// is still within our spec. |
// |
wire [3:0] skipaddr; |
assign skipaddr = { |
wb_addr[(LGFLASHSZ-2)], // Flash |
wb_addr[(LGMEMSZ-2)], // RAM |
wb_addr[ 9], // SCOPE |
wb_addr[ 8] }; // I/O |
// |
// This might not be the most efficient way in hardware, but it will |
// work for our purposes here. There are two phantom bits for each |
// of these ... bits that tell the CPU which byte within the word, and |
// another phantom bit because we allocated a minimum of two words to |
// every device. |
// |
wire idle_n; |
`ifdef ZERO_ON_IDLE |
assign idle_n = wb_stb; |
`else |
assign idle_n = 1'b1; |
`endif |
+{3'h0, mem_ack} |
+{3'h0, flash_ack} > 1)); |
|
// `define ZERO_ON_IDLE |
`ifdef ZERO_ON_IDLE |
assign idle_n = (wb_cyc)&&(wb_stb); |
`else |
assign idle_n = 1'b1; |
`endif |
assign io_sel =((idle_n)&&(skipaddr[3:0]==4'h1)); |
assign scop_sel =((idle_n)&&(skipaddr[3:1]==3'h1)); // = 4'h2 |
assign flctl_sel= 1'b0; // ((wb_cyc)&&(skipaddr[3:0]==4'h3)); |
assign mem_sel =((idle_n)&&(skipaddr[3:2]==2'h1)); |
assign flash_sel=((idle_n)&&(skipaddr[3])); |
|
// |
// none_sel |
// |
// This wire is true if wb_stb is true and no device is selected. This |
// is an error condition, but here we present the logic to test for it. |
// |
// |
// If you add another device, add another OR into the select lines |
// associated with this term. |
// |
assign none_sel =((wb_stb)&&(skipaddr==4'h0)); |
|
// |
// many_sel |
// |
// This should *never* be true .... unless you mess up your address |
// decoding logic. Since I've done that before, I test/check for it |
// here. |
// |
// To add a new device here, simply add it to the list. Make certain |
// that the width of the add, however, is greater than the number |
// of devices below. Hence, for 3 devices, you will need an add |
// at least 3 bits in width, for 7 devices you will need at least 4 |
// bits, etc. |
// |
// Because this add uses the {} operator, the individual components to |
// it are by default unsigned ... just as we would like. |
// |
// There's probably another easier/better/faster/cheaper way to do this, |
// but I haven't found any such that are also easier to adjust with |
// new devices. I'm open to options. |
// |
assign many_sel = 1'b0; |
|
// |
// many_ack |
// |
// Normally this would capture the error when multiple things creates acks |
// at the same time. The S6 is small, though, and doesn't have the logic |
// we need to do this right. Hence we just declare (and hope) that this |
// will never be true and work with that. |
// |
assign many_ack = 1'b0; |
assign many_sel = 1'b0; |
assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0)); |
`endif |
|
wire flash_interrupt, scop_interrupt, tmra_int, tmrb_int, |
rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int; |
gpio_int, pwm_int, keypad_int,button_int; |
|
|
// |
// bus_err_addr |
// |
// We'd like to know, after the fact, what (if any) address caused a |
// bus error. So ... if we get a bus error, let's record the address |
// on the bus for later analysis. |
// |
initial bus_err_addr = 0; |
always @(posedge i_clk) |
if (wb_err) |
bus_err_addr <= wb_addr; |
// |
// Interrupt processing |
// |
// The interrupt controller will be used to tell us if any interrupts |
// take place. |
// |
// To add more interrupts, you can just add more wires to this int_vector |
// for the new interrupts. |
// |
reg rx_rdy; |
wire [11:0] int_vector; |
assign int_vector = { |
flash_interrupt, gpio_int, pwm_int, keypad_int, |
(~o_tx_stb), rx_rdy, |
(!o_tx_stb), rx_rdy, |
tmrb_int, tmra_int, |
rtc_interrupt, scop_interrupt, |
1'b0, scop_interrupt, |
wb_err, button_int }; |
|
wire [31:0] pic_data; |
276,70 → 397,24
&&(wb_addr[3:0]==4'h0)&&(wb_we), |
wb_data, pic_data, int_vector, w_interrupt); |
|
initial bus_err_addr = 0; // `DATESTAMP; |
always @(posedge i_clk) |
if (wb_err) |
bus_err_addr <= wb_addr; |
|
wire [31:0] timer_a, timer_b; |
wire [31:0] timer_data, timer_b; |
wire zta_ack, zta_stall, ztb_ack, ztb_stall; |
ziptimer #(32,31,1) |
zipt_a(i_clk, 1'b0, 1'b1, wb_cyc, |
`ifdef INCLUDE_SECOND_TIMER |
thetimer(i_clk, 1'b0, 1'b1, wb_cyc, |
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2), |
`else |
(wb_stb)&&(io_sel)&&(wb_addr[3:1]==3'h1), |
`endif |
wb_we, wb_data, zta_ack, zta_stall, timer_a, |
wb_we, wb_data, zta_ack, zta_stall, timer_data, |
tmra_int); |
`ifdef INCLUDE_SECOND_TIMER |
`ifdef SECOND_TIMER_IS_WATCHDOG |
ziptimer #(32,31,0) |
zipt_b(i_clk, 1'b0, 1'b1, wb_cyc, |
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3), |
wb_we, wb_data, ztb_ack, ztb_stall, timer_b, |
tmrb_int); |
`else |
ziptimer #(32,31,1) |
zipt_b(i_clk, 1'b0, 1'b1, wb_cyc, |
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3), |
wb_we, wb_data, ztb_ack, ztb_stall, timer_b, |
tmrb_int); |
`endif |
`else |
// assign timer_b = 32'h000; |
assign timer_b = timer_a; |
assign tmrb_int = 1'b0; |
`endif |
|
wire [31:0] rtc_data; |
`ifdef INCLUDE_RTC |
wire rtcd_ack, rtcd_stall, ppd; |
// rtcdate thedate(i_clk, ppd, wb_cyc, (wb_stb)&&(io_sel), wb_we, |
// wb_data, rtcd_ack, rtcd_stall, date_data); |
reg r_rtc_ack; |
initial r_rtc_ack = 1'b0; |
always @(posedge i_clk) |
r_rtc_ack <= ((wb_stb)&&(rtc_sel)); |
assign rtc_ack = r_rtc_ack; |
|
rtclight |
#(23'h35afe5,23,0,0) // 80 MHz clock |
thetime(i_clk, wb_cyc, |
((wb_stb)&&(rtc_sel)), wb_we, |
{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data, |
rtc_interrupt, ppd); |
`else |
assign rtc_interrupt = 1'b0; |
assign rtc_data = 32'h00; |
assign rtc_ack = 1'b0; |
`endif |
|
always @(posedge i_clk) |
case(wb_addr[3:0]) |
4'h0: io_data <= pic_data; |
4'h1: io_data <= { {(32-BAW){1'b0}}, bus_err_addr }; |
4'h2: io_data <= timer_a; |
4'h1: io_data <= { {(30-BAW){1'b0}}, bus_err_addr, 2'b00 }; |
4'h2: io_data <= timer_data; |
4'h3: io_data <= timer_b; |
4'h4: io_data <= pwm_data; |
4'h5: io_data <= spio_data; |
349,7 → 424,7
// 4'h8: io_data <= `DATESTAMP; |
endcase |
always @(posedge i_clk) |
io_ack <= (wb_cyc)&&(wb_stb)&&(io_sel); |
io_ack <= (wb_stb)&&(io_sel); |
assign io_stall = 1'b0; |
|
wire pwm_ack, pwm_stall; |
365,8 → 440,9
// Special Purpose I/O: Keypad, button, LED status and control |
// |
wire [3:0] w_led; |
spio thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),wb_we, |
wb_data, spio_data, o_kp_col, i_kp_row, i_btn, w_led, |
spio thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5), |
wb_we, wb_data, spio_data, |
o_kp_col, i_kp_row, i_btn, w_led, |
keypad_int, button_int); |
assign o_led = { w_led[3]|w_interrupt,w_led[2],w_led[1:0] }; |
|
391,7 → 467,7
// |
// We'll add the flag for two stop bits. |
// assign o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock |
assign o_uart_setup = 30'h0000208d; // 9600 MBaud, 8N1 |
assign o_uart_setup = 31'h4000208d; // 9600 MBaud, 8N1 |
|
initial o_tx_stb = 1'b0; |
initial o_tx_data = 8'h00; |
414,7 → 490,7
else if (i_rx_stb) |
rx_rdy <= (rx_rdy | i_rx_stb); |
end |
assign o_uart_cts = (~rx_rdy); |
assign o_uart_rts_n = (rx_rdy); |
assign uart_data = { 23'h0, ~rx_rdy, r_rx_data }; |
// |
// uart_ack gets returned as part of io_ack, since that happens when |
428,45 → 504,44
// |
// FLASH MEMORY CONFIGURATION ACCESS |
// |
wbqspiflashp #(24) flashmem(i_clk, |
`ifdef FLASH_ACCESS |
wbqspiflash #(LGFLASHSZ) flashmem(i_clk, |
wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we, |
wb_addr[(24-3):0], wb_data, |
wb_addr[(LGFLASHSZ-3):0], wb_data, |
flash_ack, flash_stall, flash_data, |
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat, |
flash_interrupt); |
|
// |
// MULTIBOOT/ICAPE2 CONFIGURATION ACCESS |
// |
wire [31:0] cfg_scope; |
`ifdef FANCY_ICAP_ACCESS |
wbicape6 fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we, |
wb_addr[5:0], wb_data, |
cfg_ack, cfg_stall, cfg_data, |
cfg_scope); |
`else |
reg r_cfg_ack; |
reg r_flash_ack; |
initial r_flash_ack = 1'b0; |
always @(posedge i_clk) |
r_cfg_ack <= (wb_cyc)&&(cfg_sel)&&(wb_stb); |
assign cfg_ack = r_cfg_ack; |
assign cfg_stall = 1'b0; |
assign cfg_data = 32'h00; |
assign cfg_scope = 32'h00; |
r_flash_ack <= (wb_stb)&&((flash_sel)||(flctl_sel)); |
|
assign flash_ack = r_flash_ack; |
assign flash_stall = 1'b0; |
assign flash_data = 32'h0000; |
assign flash_interrupt = 1'b0; |
|
assign o_qspi_sck = 1'b1; |
assign o_qspi_cs_n = 1'b1; |
assign o_qspi_mod = 2'b01; |
assign o_qspi_dat = 4'b1111; |
`endif |
|
|
// |
// ON-CHIP RAM MEMORY ACCESS |
// |
`ifdef IMPLEMENT_ONCHIP_RAM |
memdev #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we, |
wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data); |
memdev #(.LGMEMSZ(LGMEMSZ)) |
ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we, |
wb_addr[(LGMEMSZ-3):0], wb_data, wb_sel, |
mem_ack, mem_stall, mem_data); |
`else |
assign mem_data = 32'h00; |
assign mem_stall = 1'b0; |
reg r_mem_ack; |
always @(posedge i_clk) |
r_mem_ack <= (wb_cyc)&&(wb_stb)&&(mem_sel); |
r_mem_ack <= (wb_stb)&&(mem_sel); |
assign mem_ack = r_mem_ack; |
`endif |
|
481,15 → 556,14
wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt; |
`ifdef DBG_SCOPE |
wire scop_cfg_trigger; |
assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel); |
wire scop_trigger = scop_cfg_trigger; |
assign scop_cfg_trigger = (wb_stb)&&(cfg_sel); |
wire scop_trigger = bus_dbg; |
`ifdef COMPRESSED_SCOPE |
wbscopc #(5'ha) |
`else |
wbscope #(5'ha) |
`endif |
wbcfgscope(i_clk, 1'b1, scop_trigger, |
cfg_scope, |
wbcfgscope(i_clk, 1'b1, scop_trigger, bus_debug, |
// Wishbone interface |
i_clk, wb_cyc, (wb_stb)&&(scop_sel), |
wb_we, wb_addr[0], wb_data, |
498,7 → 572,7
`else |
reg r_scop_cfg_ack; |
always @(posedge i_clk) |
r_scop_cfg_ack <= (wb_cyc)&&(wb_stb)&&(scop_sel); |
r_scop_cfg_ack <= (wb_stb)&&(scop_sel); |
assign scop_cfg_ack = r_scop_cfg_ack; |
assign scop_cfg_data = 32'h000; |
assign scop_cfg_stall= 1'b0; |
/rtl/alttop.v
46,7 → 46,7
module alttop(i_clk_8mhz, |
o_qspi_cs_n, o_qspi_sck, io_qspi_dat, |
i_btn, o_led, o_pwm, o_pwm_shutdown_n, o_pwm_gain, |
i_uart, o_uart, o_uart_cts, i_uart_rts, |
i_uart, o_uart, o_uart_rts_n, i_uart_cts_n, |
i_kp_row, o_kp_col, |
i_gpio, o_gpio, |
io_scl, io_sda, |
69,8 → 69,8
input i_uart; |
output wire o_uart; |
// and it's associated control wires |
output wire o_uart_cts; |
input i_uart_rts; |
output wire o_uart_rts_n; |
input i_uart_cts_n; |
// Our keypad |
input [3:0] i_kp_row; |
output wire [3:0] o_kp_col; |
126,13 → 126,25
wire tx_busy; |
wire [29:0] uart_setup; |
|
// Baud rate is set by clock rate / baud rate desired. Thus, |
// 80 MHz / 9600 Baud = 8333, or about 0x208d. We choose a slow |
// speed such as 9600 Baud to help the CPU keep up with the serial |
// port rate. |
localparam [30:0] UART_SETUP = 31'h4000208d; |
assign uart_setup = UART_SETUP; |
|
wire reset_s; |
assign reset_s = 1'b0; |
|
wire rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, tx_break; |
assign tx_break = 1'b0; |
rxuart rcvuart(clk_s, 1'b0, uart_setup, |
rxuart #(UART_SETUP) |
rcvuart(clk_s, 1'b0, uart_setup, |
i_uart, rx_stb, rx_data, |
rx_break, rx_parity_err, rx_frame_err, rx_ck_uart); |
txuart tcvuart(clk_s, reset_s, uart_setup, tx_break, tx_stb, tx_data, |
o_uart, tx_busy); |
txuart #(UART_SETUP) |
tcvuart(clk_s, reset_s, uart_setup, tx_break, tx_stb, tx_data, |
i_uart_cts_n, o_uart, tx_busy); |
|
|
// |
152,6 → 164,7
wire [15:0] w_gpio; |
wire [7:0] w_depp_data; |
|
wire w_uart_rts_n; |
`ifndef BYPASS_LOGIC |
altbusmaster slavedbus(clk_s, 1'b0, |
// External ... bus control (if enabled) |
159,7 → 172,7
i_depp_astb_n, i_depp_dstb_n, i_depp_write_n, |
io_depp_data, w_depp_data, o_depp_wait, |
// External UART interface |
rx_stb, rx_data, tx_stb, tx_data, tx_busy, w_uart_cts, |
rx_stb, rx_data, tx_stb, tx_data, tx_busy, w_uart_rts_n, |
// SPI/SD-card flash |
o_qspi_cs_n, o_qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod, |
// Board lights and switches |
171,7 → 184,7
// GPIO lines |
{ i_gpio, io_scl, io_sda }, w_gpio |
); |
assign o_uart_cts = (w_uart_cts)&&(i_uart_rts); |
assign o_uart_rts_n = (w_uart_rts_n); |
|
// |
// Quad SPI support |
211,7 → 224,7
|
assign uart_setup = 30'h080002b6; |
|
assign o_uart_cts = 1'b1; |
assign o_uart_rts_n = 1'b0; |
`endif |
// |
// I2C support |
/rtl/builddate.v
1,7 → 224,7
`define DATESTAMP 32'h20160520 |
`define DATESTAMP 32'h20170309 |
/rtl/busmaster.v
4,7 → 4,12
// |
// Project: CMod S6 System on a Chip, ZipCPU demonstration project |
// |
// Purpose: |
// Purpose: This is the highest level, simulatable, file in the S6SoC |
// project--of that portion of the project that includes the |
// ZipCPU. This portion therefore contains references to all of the |
// masters (ZipCPU) and slaves (flash, block RAM, I/O, Scope) on the |
// wishbone bus, and connects them all together. Hence, this contains |
// the wishbone interconnect logic as well. |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
11,7 → 16,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
35,25 → 40,15
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// |
`include "builddate.v" |
// |
`define INCLUDE_ZIPPY |
`define IMPLEMENT_ONCHIP_RAM |
`ifndef VERILATOR |
`define FANCY_ICAP_ACCESS |
`endif |
`define FLASH_ACCESS |
`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses |
// `define COMPRESSED_SCOPE |
`define INCLUDE_SECOND_TIMER |
`define SECOND_TIMER_IS_WATCHDOG |
// `define INCLUDE_RTC // About 90 LUTs |
// `define FULL_BUSERR_CALCULATION |
`define INCLUDE_CPU_RESET_LOGIC |
module busmaster(i_clk, i_rst, |
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy, |
o_uart_cts, |
i_uart, o_uart_rts_n, o_uart, i_uart_cts_n, |
// The SPI Flash lines |
o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod, |
// The board I/O |
60,20 → 55,25
i_btn, o_led, o_pwm, o_pwm_aux, |
// Keypad connections |
i_kp_row, o_kp_col, |
// UART control |
o_uart_setup, |
// GPIO lines |
i_gpio, o_gpio); |
parameter BUS_ADDRESS_WIDTH=23, ZIP_ADDRESS_WIDTH=BUS_ADDRESS_WIDTH, |
CMOD_ZIPCPU_RESET_ADDRESS=23'h480000, |
ZA=ZIP_ADDRESS_WIDTH, BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181 |
parameter BUS_ADDRESS_WIDTH=23, |
ZIP_ADDRESS_WIDTH=BUS_ADDRESS_WIDTH, |
CMOD_ZIPCPU_RESET_ADDRESS=32'h1200000, |
UART_SETUP = 31'd25; |
localparam ZA=ZIP_ADDRESS_WIDTH, |
BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181 |
// 2^14 bytes requires a LGMEMSZ of 14, and 12 address bits ranging from |
// 0 to 11. As with many other devices, the wb_cyc line is more for |
// form than anything else--it is ignored by the memory itself. |
localparam LGMEMSZ=14; // Takes 8 BLKRAM16 elements for LGMEMSZ=14 |
// As with the memory size, the flash size is also measured in log_2 of |
// the number of bytes. |
localparam LGFLASHSZ = 24; |
input i_clk, i_rst; |
input i_rx_stb; |
input [7:0] i_rx_data; |
output reg o_tx_stb; |
output reg [7:0] o_tx_data; |
input i_tx_busy; |
output wire o_uart_cts; |
// UART parameters |
input i_uart, i_uart_cts_n; |
output wire o_uart, o_uart_rts_n; |
// SPI flash control |
output wire o_qspi_cs_n, o_qspi_sck; |
output wire [3:0] o_qspi_dat; |
87,8 → 87,6
// Keypad |
input [3:0] i_kp_row; |
output wire [3:0] o_kp_col; |
// UART control |
output wire [29:0] o_uart_setup; |
// GPIO liines |
input [15:0] i_gpio; |
output wire [15:0] o_gpio; |
101,15 → 99,8
// |
wire wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err; |
wire [31:0] wb_data, wb_idata; |
wire [3:0] wb_sel; |
wire [(BAW-1):0] wb_addr; |
wire [5:0] io_addr; |
assign io_addr = { |
wb_addr[22], // Flash |
wb_addr[13], // RAM |
wb_addr[11], // RTC |
wb_addr[10], // CFG |
wb_addr[ 9], // SCOPE |
wb_addr[ 8] }; // I/O |
|
// Wires going to devices |
// And then headed back home |
134,22 → 125,8
wire [(BAW-1):0] dwb_addr; |
wire [31:0] dwb_odata; |
|
// wire [31:0] zip_debug; |
wire cpu_reset, watchdog_int; |
// |
// We'll define our RESET_ADDRESS to be halfway through our flash memory. |
// `define CMOD_ZIPCPU_RESET_ADDRESS 23'h600000 |
// |
// Ahm, No. We can actually do much better than that. Our toplevel *.bit file |
// only takes up only 335kB. Let's give it some room to grow to 1024 kB. Then |
// 23 can start our ROM at 23'h400100 |
// |
// Not so fast. In hindsight, we really want to be able to adjust the load and |
// the program separately. So, instead, let's place our RESET address at the |
// second flash erase block. That way, we can change our program code found |
// in the flash without needing to change our FPGA load and vice versa. |
// |
// 23'h404000 |
wire cpu_reset, tmrb_int; |
`ifdef INCLUDE_CPU_RESET_LOGIC |
reg btn_reset, x_button, r_button; |
initial btn_reset = 1'b0; |
159,11 → 136,7
begin |
x_button <= i_btn[1]; |
r_button <= x_button; |
`ifdef SECOND_TIMER_IS_WATCHDOG |
btn_reset <= ((r_button)&&(zip_cpu_int))||(tmrb_int); |
`else |
btn_reset <= ((r_button)&&(zip_cpu_int)); |
`endif |
btn_reset <= ((r_button)&&(zip_cpu_int))||(watchdog_int); |
end |
assign cpu_reset = btn_reset; |
`else |
171,9 → 144,9
`endif |
|
zipbones #(CMOD_ZIPCPU_RESET_ADDRESS,ZA,6) |
thecpu(i_clk, btn_reset, // 1'b0, |
swic(i_clk, btn_reset, // 1'b0, |
// Zippys wishbone interface |
wb_cyc, wb_stb, wb_we, w_zip_addr, wb_data, |
wb_cyc, wb_stb, wb_we, w_zip_addr, wb_data, wb_sel, |
wb_ack, wb_stall, wb_idata, wb_err, |
w_interrupt, zip_cpu_int, |
// Debug wishbone interface -- not really used |
187,13 → 160,12
assign wb_addr = w_zip_addr; |
endgenerate |
|
wire io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel, |
rtc_sel, none_sel, many_sel; |
|
// Signals to build/detect bus errors |
wire none_sel, many_sel; |
|
wire io_sel, flash_sel, flctl_sel, scop_sel, mem_sel; |
wire flash_ack, scop_ack, cfg_ack, mem_ack, many_ack; |
wire rtc_ack, rtc_stall; |
`ifdef INCLUDE_RTC |
assign rtc_stall = 1'b0; |
`endif |
wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall; |
reg io_ack; |
|
201,109 → 173,216
spio_data, gpio_data, uart_data; |
reg [31:0] io_data; |
reg [(BAW-1):0] bus_err_addr; |
// |
// wb_ack |
// |
// The returning wishbone ack is equal to the OR of every component that |
// might possibly produce an acknowledgement, gated by the CYC line. To |
// add new components, OR their acknowledgements in here. |
// |
// Note the reference to none_sel. If nothing is selected, the result |
// is an error. Here, we do nothing more than insure that the erroneous |
// request produces an ACK ... if it was ever made, rather than stalling |
// the bus. |
// |
|
assign wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack) |
`ifdef INCLUDE_RTC |
||(rtc_ack) |
`endif |
|
assign wb_ack = (wb_cyc)&&((io_ack)||(scop_ack) |
||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1))); |
|
// |
// wb_stall |
// |
// The returning wishbone stall line really depends upon what device |
// is requested. Thus, if a particular device is selected, we return |
// the stall line for that device. |
// |
// To add a new device, simply and that devices select and stall lines |
// together, and OR the result with the massive OR logic below. |
// |
assign wb_stall = ((io_sel)&&(io_stall)) |
||((scop_sel)&&(scop_stall)) |
||((cfg_sel)&&(cfg_stall)) |
||((mem_sel)&&(mem_stall)) |
`ifdef INCLUDE_RTC |
||((rtc_sel)&&(rtc_stall)) |
`endif |
||((flash_sel||flctl_sel)&&(flash_stall)); |
// (none_sel)&&(1'b0) |
|
/* |
assign wb_idata = (io_ack)?io_data |
: ((scop_ack)?scop_data |
: ((cfg_ack)?cfg_data |
: ((mem_ack)?mem_data |
: ((flash_ack)?flash_data |
: 32'h00)))); |
*/ |
// |
// wb_idata |
// |
// This is the data returned on the bus. Here, we select between a |
// series of bus sources to select what data to return. The basic |
// logic is simply this: the data we return is the data for which the |
// ACK line is high. |
// |
// The last item on the list is chosen by default if no other ACK's are |
// true. Although we might choose to return zeros in that case, by |
// returning something we can skimp a touch on the logic. |
// |
// To add another device, add another ack check, and another closing |
// parenthesis. |
// |
assign wb_idata = (io_ack|scop_ack)?((io_ack )? io_data : scop_data) |
: ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data) |
: ((cfg_ack) ? cfg_data : flash_data));//if (flash_ack) |
assign wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack; |
: ((mem_ack)?(mem_data) |
: flash_data); |
|
// |
// wb_err |
// |
// This is the bus error signal. It should never be true, but practice |
// teaches us otherwise. Here, we allow for three basic errors: |
// |
// 1. STB is true, but no devices are selected |
// |
// This is the null pointer reference bug. If you try to access |
// something on the bus, at an address with no mapping, the bus |
// should produce an error--such as if you try to access something |
// at zero. |
// |
// 2. STB is true, and more than one device is selected |
// |
// (This can be turned off, if you design this file well. For |
// this line to be true means you have a design flaw.) |
// |
// 3. If more than one ACK is every true at any given time. |
// |
// This is a bug of bus usage, combined with a subtle flaw in the |
// WB pipeline definition. You can issue bus requests, one per |
// clock, and if you cross device boundaries with your requests, |
// you may have things come back out of order (not detected here) |
// or colliding on return (detected here). The solution to this |
// problem is to make certain that any burst request does not cross |
// device boundaries. This is a requirement of whoever (or |
// whatever) drives the bus. |
// |
assign wb_err = ((wb_stb)&&(none_sel || many_sel)) || many_ack; |
|
// Addresses ... |
// 0000 xxxx configuration/control registers |
// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps |
assign io_sel =((wb_cyc)&&(io_addr[5:0]==6'h1)); |
assign scop_sel =((wb_cyc)&&(io_addr[5:1]==5'h1)); |
assign flctl_sel= 1'b0; // ((wb_cyc)&&(io_addr[5:1]==5'h1)); |
assign cfg_sel =((wb_cyc)&&(io_addr[5:2]==4'h1)); |
// zip_sel is not on the bus at this point |
`ifdef INCLUDE_RTC |
assign rtc_sel =((wb_cyc)&&(io_addr[5:3]==3'h1)); |
`endif |
assign mem_sel =((wb_cyc)&&(io_addr[5:4]==2'h1)); |
assign flash_sel=((wb_cyc)&&(io_addr[5])); |
// |
// dev_sel |
// |
// The device select lines |
// |
// |
|
`ifdef FULL_BUSERR_CALCULATION |
assign none_sel =((wb_cyc)&&(wb_stb)&& |
((io_addr==6'h0) |
||((~io_addr[5])&&(|wb_addr[22:14])) |
||((io_addr[5:4]==2'b00)&&(|wb_addr[12]))) |
); |
assign many_sel =((wb_cyc)&&(wb_stb)&&( |
{3'h0, io_sel} |
+{3'h0, flctl_sel} |
+{3'h0, scop_sel} |
+{3'h0, cfg_sel} |
+{3'h0, rtc_sel} |
+{3'h0, mem_sel} |
+{3'h0, flash_sel} > 1)); |
|
assign many_ack =((wb_cyc)&&( |
{3'h0, io_ack} |
+{3'h0, scop_ack} |
+{3'h0, cfg_ack} |
`ifdef INCLUDE_RTC |
+{3'h0, rtc_ack} |
// |
// The skipaddr bitfield below is our cheaters way of handling |
// device selection. We grab particular wires from the bus to do |
// this, and ignore all others. While this may lead to some |
// surprising results for the CPU when it tries to access an |
// inappropriate address, it also minimizes our logic while also |
// placing every address at the right address. The only problem is |
// ... devices will also be at some unexpected addresses, but ... this |
// is still within our spec. |
// |
wire [3:0] skipaddr; |
assign skipaddr = { |
wb_addr[(LGFLASHSZ-2)], // Flash |
wb_addr[(LGMEMSZ-2)], // RAM |
wb_addr[ 9], // SCOPE |
wb_addr[ 8] }; // I/O |
// |
// This might not be the most efficient way in hardware, but it will |
// work for our purposes here. There are two phantom bits for each |
// of these ... bits that tell the CPU which byte within the word, and |
// another phantom bit because we allocated a minimum of two words to |
// every device. |
// |
wire idle_n; |
`ifdef ZERO_ON_IDLE |
assign idle_n = wb_stb; |
`else |
assign idle_n = 1'b1; |
`endif |
+{3'h0, mem_ack} |
+{3'h0, flash_ack} > 1)); |
|
// `define ZERO_ON_IDLE |
`ifdef ZERO_ON_IDLE |
assign idle_n = (wb_cyc)&&(wb_stb); |
`else |
assign many_ack = 1'b0; |
assign many_sel = 1'b0; |
assign none_sel =((wb_cyc)&&(wb_stb)&&( |
(io_addr[5:4]==2'h0) |
&&(~io_addr[0]) |
`ifdef INCLUDE_RTC |
&&(~io_addr[3]) |
assign idle_n = 1'b1; |
`endif |
`ifdef FANCY_ICAP_ACCESS |
&&(~io_addr[2]) |
`endif |
`ifdef DBG_SCOPE |
&&(~io_addr[1]) |
`endif |
)); |
`endif |
wire flash_interrupt, scop_interrupt, tmra_int, |
rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int; |
assign io_sel =((idle_n)&&(skipaddr[3:0]==4'h1)); |
assign scop_sel =((idle_n)&&(skipaddr[3:1]==3'h1)); // = 4'h2 |
assign flctl_sel= 1'b0; // ((wb_cyc)&&(skipaddr[3:0]==4'h3)); |
assign mem_sel =((idle_n)&&(skipaddr[3:2]==2'h1)); |
assign flash_sel=((idle_n)&&(skipaddr[3])); |
|
// |
// none_sel |
// |
// This wire is true if wb_stb is true and no device is selected. This |
// is an error condition, but here we present the logic to test for it. |
// |
// |
// If you add another device, add another OR into the select lines |
// associated with this term. |
// |
assign none_sel =((wb_stb)&&(skipaddr==4'h0)); |
|
// |
// many_sel |
// |
// This should *never* be true .... unless you mess up your address |
// decoding logic. Since I've done that before, I test/check for it |
// here. |
// |
// To add a new device here, simply add it to the list. Make certain |
// that the width of the add, however, is greater than the number |
// of devices below. Hence, for 3 devices, you will need an add |
// at least 3 bits in width, for 7 devices you will need at least 4 |
// bits, etc. |
// |
// Because this add uses the {} operator, the individual components to |
// it are by default unsigned ... just as we would like. |
// |
// There's probably another easier/better/faster/cheaper way to do this, |
// but I haven't found any such that are also easier to adjust with |
// new devices. I'm open to options. |
// |
assign many_sel = 1'b0; |
|
// |
// many_ack |
// |
// Normally this would capture the error when multiple things creates acks |
// at the same time. The S6 is small, though, and doesn't have the logic |
// we need to do this right. Hence we just declare (and hope) that this |
// will never be true and work with that. |
// |
assign many_ack = 1'b0; |
|
|
wire flash_interrupt, scop_interrupt, timer_int, |
gpio_int, pwm_int, keypad_int,button_int; |
|
|
// |
// bus_err_addr |
// |
// We'd like to know, after the fact, what (if any) address caused a |
// bus error. So ... if we get a bus error, let's record the address |
// on the bus for later analysis. |
// |
initial bus_err_addr = 0; |
always @(posedge i_clk) |
if (wb_err) |
bus_err_addr <= wb_addr; |
// |
// Interrupt processing |
// |
// The interrupt controller will be used to tell us if any interrupts |
// take place. |
// |
// To add more interrupts, you can just add more wires to this |
// int_vector. |
// |
reg rx_rdy; |
wire [10:0] int_vector; |
assign int_vector = { |
assign int_vector = { |
gpio_int, pwm_int, keypad_int, |
(~o_tx_stb), rx_rdy, |
`ifdef SECOND_TIMER_IS_WATCHDOG |
1'b0, |
`else |
tmrb_int, |
`endif |
tmra_int, |
rtc_interrupt, scop_interrupt, |
(!tx_stb), rx_rdy, |
1'b0, timer_int, |
1'b0, scop_interrupt, |
wb_err, button_int }; |
|
wire [31:0] pic_data; |
311,71 → 390,25
&&(wb_addr[3:0]==4'h0)&&(wb_we), |
wb_data, pic_data, int_vector, w_interrupt); |
|
initial bus_err_addr = 0; // `DATESTAMP; |
always @(posedge i_clk) |
if (wb_err) |
bus_err_addr <= wb_addr; |
|
wire [31:0] timer_a, timer_b; |
wire [31:0] timer_data, watchdog_data; |
wire zta_ack, zta_stall, ztb_ack, ztb_stall; |
ziptimer #(32,31,1) |
zipt_a(i_clk, 1'b0, 1'b1, wb_cyc, |
`ifdef INCLUDE_SECOND_TIMER |
thetimer(i_clk, 1'b0, 1'b1, wb_cyc, |
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2), |
`else |
(wb_stb)&&(io_sel)&&(wb_addr[3:1]==3'h1), |
`endif |
wb_we, wb_data, zta_ack, zta_stall, timer_a, |
tmra_int); |
`ifdef INCLUDE_SECOND_TIMER |
`ifdef SECOND_TIMER_IS_WATCHDOG |
wb_we, wb_data, zta_ack, zta_stall, timer_data, |
timer_int); |
ziptimer #(32,31,0) |
zipt_b(i_clk, cpu_reset, 1'b1, wb_cyc, |
watchdog(i_clk, cpu_reset, 1'b1, wb_cyc, |
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3), |
wb_we, wb_data, ztb_ack, ztb_stall, timer_b, |
tmrb_int); |
`else |
ziptimer #(32,31,1) |
zipt_b(i_clk, cpu_reset, 1'b1, wb_cyc, |
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3), |
wb_we, wb_data, ztb_ack, ztb_stall, timer_b, |
tmrb_int); |
`endif |
`else |
// assign timer_b = 32'h000; |
assign timer_b = timer_a; |
assign tmrb_int = 1'b0; |
`endif |
wb_we, wb_data, ztb_ack, ztb_stall, watchdog_data, |
watchdog_int); |
|
wire [31:0] rtc_data; |
`ifdef INCLUDE_RTC |
wire rtcd_ack, rtcd_stall, ppd; |
// rtcdate thedate(i_clk, ppd, wb_cyc, (wb_stb)&&(io_sel), wb_we, |
// wb_data, rtcd_ack, rtcd_stall, date_data); |
reg r_rtc_ack; |
initial r_rtc_ack = 1'b0; |
always @(posedge i_clk) |
r_rtc_ack <= ((wb_stb)&&(rtc_sel)); |
assign rtc_ack = r_rtc_ack; |
|
rtclight |
#(23'h35afe5,23,0,0) // 80 MHz clock |
thetime(i_clk, wb_cyc, |
((wb_stb)&&(rtc_sel)), wb_we, |
{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data, |
rtc_interrupt, ppd); |
`else |
assign rtc_interrupt = 1'b0; |
assign rtc_data = 32'h00; |
assign rtc_ack = 1'b0; |
`endif |
|
always @(posedge i_clk) |
case(wb_addr[3:0]) |
4'h0: io_data <= pic_data; |
4'h1: io_data <= { {(32-BAW){1'b0}}, bus_err_addr }; |
4'h2: io_data <= timer_a; |
4'h3: io_data <= timer_b; |
4'h1: io_data <= { {(30-BAW){1'b0}}, bus_err_addr, 2'b00 }; |
4'h2: io_data <= timer_data; |
4'h3: io_data <= watchdog_data; |
4'h4: io_data <= pwm_data; |
4'h5: io_data <= spio_data; |
4'h6: io_data <= gpio_data; |
384,7 → 417,7
// 4'h8: io_data <= `DATESTAMP; |
endcase |
always @(posedge i_clk) |
io_ack <= (wb_cyc)&&(wb_stb)&&(io_sel); |
io_ack <= (wb_stb)&&(io_sel); |
assign io_stall = 1'b0; |
|
wire pwm_ack, pwm_stall; |
400,8 → 433,9
// Special Purpose I/O: Keypad, button, LED status and control |
// |
wire [3:0] w_led; |
spio thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),wb_we, |
wb_data, spio_data, o_kp_col, i_kp_row, i_btn, w_led, |
spio thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5), |
wb_we, wb_data, spio_data, |
o_kp_col, i_kp_row, i_btn, w_led, |
keypad_int, button_int); |
assign o_led = { w_led[3]|w_interrupt,w_led[2]|zip_cpu_int,w_led[1:0] }; |
|
415,42 → 449,57
|
// |
// |
// UART device: our console |
// |
// |
wire [30:0] uart_setup; |
// |
wire rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, rx_stb; |
wire [7:0] rx_data; |
// |
assign uart_setup = UART_SETUP; |
// |
rxuart #(UART_SETUP) |
rcvuart(i_clk, 1'b0, uart_setup, i_uart, rx_stb, rx_data, |
rx_break, rx_parity_err, rx_frame_err, rx_ck_uart); |
// |
wire tx_break, tx_busy; |
reg tx_stb; |
reg [7:0] tx_data; |
assign tx_break = 1'b0; |
txuart #(UART_SETUP) |
tcvuart(i_clk, 1'b0, uart_setup, tx_break, tx_stb, tx_data, |
i_uart_cts_n, o_uart, tx_busy); |
|
// |
// Rudimentary serial port control |
// |
reg [7:0] r_rx_data; |
// Baud rate is set by clock rate / baud rate. |
// Thus, 80MHz / 115200MBau |
// = 694.4, or about 0x2b6. |
// although the CPU might struggle to keep up at this speed without a |
// hardware buffer. |
// |
// We'll add the flag for two stop bits. |
// assign o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock |
assign o_uart_setup = 30'h0000208d; // 9600 MBaud, 8N1 |
|
initial o_tx_stb = 1'b0; |
initial o_tx_data = 8'h00; |
initial tx_stb = 1'b0; |
initial tx_data = 8'h00; |
always @(posedge i_clk) |
if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we)) |
begin |
o_tx_data <= wb_data[7:0]; |
o_tx_stb <= 1'b1; |
tx_data <= wb_data[7:0]; |
tx_stb <= 1'b1; |
end |
else if ((o_tx_stb)&&(~i_tx_busy)) |
o_tx_stb <= 1'b0; |
else if ((tx_stb)&&(!tx_busy)) |
tx_stb <= 1'b0; |
initial rx_rdy = 1'b0; |
always @(posedge i_clk) |
if (i_rx_stb) |
r_rx_data <= i_rx_data; |
if (rx_stb) |
r_rx_data <= rx_data; |
always @(posedge i_clk) |
begin |
if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we)) |
rx_rdy <= i_rx_stb; |
else if (i_rx_stb) |
rx_rdy <= (rx_rdy | i_rx_stb); |
if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(!wb_we)) |
rx_rdy <= rx_stb; |
else if (rx_stb) |
rx_rdy <= (rx_rdy | rx_stb); |
end |
assign o_uart_cts = (~rx_rdy); |
assign uart_data = { 23'h0, ~rx_rdy, r_rx_data }; |
assign o_uart_rts_n = (rx_rdy); |
assign uart_data = { 23'h0, !rx_rdy, r_rx_data }; |
// |
// uart_ack gets returned as part of io_ack, since that happens when |
// io_sel and wb_stb are defined |
463,45 → 512,44
// |
// FLASH MEMORY CONFIGURATION ACCESS |
// |
wbqspiflash #(24) flashmem(i_clk, |
`ifdef FLASH_ACCESS |
wbqspiflash #(LGFLASHSZ) flashmem(i_clk, |
wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we, |
wb_addr[(24-3):0], wb_data, |
wb_addr[(LGFLASHSZ-3):0], wb_data, |
flash_ack, flash_stall, flash_data, |
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat, |
flash_interrupt); |
|
// |
// MULTIBOOT/ICAPE2 CONFIGURATION ACCESS |
// |
wire [31:0] cfg_scope; |
`ifdef FANCY_ICAP_ACCESS |
wbicape6 fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we, |
wb_addr[5:0], wb_data, |
cfg_ack, cfg_stall, cfg_data, |
cfg_scope); |
`else |
reg r_cfg_ack; |
reg r_flash_ack; |
initial r_flash_ack = 1'b0; |
always @(posedge i_clk) |
r_cfg_ack <= (wb_cyc)&&(cfg_sel)&&(wb_stb); |
assign cfg_ack = r_cfg_ack; |
assign cfg_stall = 1'b0; |
assign cfg_data = 32'h00; |
assign cfg_scope = 32'h00; |
r_flash_ack <= (wb_stb)&&((flash_sel)||(flctl_sel)); |
|
assign flash_ack = r_flash_ack; |
assign flash_stall = 1'b0; |
assign flash_data = 32'h0000; |
assign flash_interrupt = 1'b0; |
|
assign o_qspi_sck = 1'b1; |
assign o_qspi_cs_n = 1'b1; |
assign o_qspi_mod = 2'b01; |
assign o_qspi_dat = 4'b1111; |
`endif |
|
|
// |
// ON-CHIP RAM MEMORY ACCESS |
// |
`ifdef IMPLEMENT_ONCHIP_RAM |
memdev #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we, |
wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data); |
memdev #(.LGMEMSZ(LGMEMSZ)) |
ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we, |
wb_addr[(LGMEMSZ-3):0], wb_data, wb_sel, |
mem_ack, mem_stall, mem_data); |
`else |
assign mem_data = 32'h00; |
assign mem_stall = 1'b0; |
reg r_mem_ack; |
always @(posedge i_clk) |
r_mem_ack <= (wb_cyc)&&(wb_stb)&&(mem_sel); |
r_mem_ack <= (wb_stb)&&(mem_sel); |
assign mem_ack = r_mem_ack; |
`endif |
|
512,19 → 560,16
// |
// |
// |
wire [31:0] scop_cfg_data; |
wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt; |
wire [31:0] scop_cpu_data; |
wire scop_cpu_ack, scop_cpu_stall, scop_cpu_interrupt; |
`ifdef DBG_SCOPE |
wire scop_cfg_trigger; |
assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel); |
// wire scop_trigger = scop_cfg_trigger; |
wire scop_trigger = (zip_cpu_int) || (cpu_reset); |
`ifdef COMPRESSED_SCOPE |
wbscopc #(5'ha) |
`else |
wbscope #(5'ha) |
wbscope #(.LGMEM(5'h6), .HOLDOFFBITS(9)) |
`endif |
wbcfgscope(i_clk, 1'b1, scop_trigger, |
cpuscope(i_clk, 1'b1, scop_trigger, |
`ifdef COMPRESSED_SCOPE |
// cfg_scope[30:0], |
zip_scope_data[30:0], |
535,21 → 580,21
// Wishbone interface |
i_clk, wb_cyc, (wb_stb)&&(scop_sel), |
wb_we, wb_addr[0], wb_data, |
scop_cfg_ack, scop_cfg_stall, scop_cfg_data, |
scop_cfg_interrupt); |
scop_cpu_ack, scop_cpu_stall, scop_cpu_data, |
scop_cpu_interrupt); |
`else |
reg r_scop_cfg_ack; |
reg r_scop_cpu_ack; |
always @(posedge i_clk) |
r_scop_cfg_ack <= (wb_cyc)&&(wb_stb)&&(scop_sel); |
assign scop_cfg_ack = r_scop_cfg_ack; |
assign scop_cfg_data = 32'h000; |
assign scop_cfg_stall= 1'b0; |
r_scop_cpu_ack <= (wb_stb)&&(scop_sel); |
assign scop_cpu_ack = r_scop_cpu_ack; |
assign scop_cpu_data = 32'h000; |
assign scop_cpu_stall= 1'b0; |
`endif |
|
assign scop_interrupt = scop_cfg_interrupt; |
assign scop_ack = scop_cfg_ack; |
assign scop_stall = scop_cfg_stall; |
assign scop_data = scop_cfg_data; |
assign scop_interrupt = scop_cpu_interrupt; |
assign scop_ack = scop_cpu_ack; |
assign scop_stall = scop_cpu_stall; |
assign scop_data = scop_cpu_data; |
|
endmodule |
|
/rtl/cpu/wbpriarbiter.v
File deleted
/rtl/cpu/busdelay.v
File deleted
/rtl/cpu/wbarbiter.v
File deleted
/rtl/cpu/cpudefs.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: cpudefs.v |
// |
26,9 → 26,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
40,11 → 40,18
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
`ifndef CPUDEFS_H |
`define CPUDEFS_H |
// |
62,8 → 69,8
// illegal instructions are quietly ignored and their behaviour is ... |
// undefined. (Many get treated like NOOPs ...) |
// |
// I recommend setting this flag, although it can be taken out if area is |
// critical ... |
// I recommend setting this flag so highly, that I'm likely going to remove |
// the option to turn this off in future versions of this CPU. |
// |
`define OPT_ILLEGAL_INSTRUCTION |
// |
76,11 → 83,17
// OPT_ILLEGAL_INSTRUCTION is set, then the multiply will create an illegal |
// instruction that will then trip the illegal instruction trap. |
// |
// Either not defining this value, or defining it to zero will disable the |
// hardware multiply. A value of '1' will cause the multiply to occurr in one |
// clock cycle only--often at the expense of the rest of the CPUs speed. |
// A value of 2 will cause the multiply to have a single delay cycle, 3 will |
// have two delay cycles, and 4 (or more) will have 3 delay cycles. |
// |
`define OPT_MULTIPLY 2 |
// |
`define OPT_MULTIPLY 4 |
// |
// |
// |
// OPT_DIVIDE controls whether or not the divide instruction is built and |
// included into the ZipCPU by default. Set this option and a parameter will |
// be set that causes the divide unit to be included. (This parameter may |
108,23 → 121,28
// |
// |
// |
// OPT_NEW_INSTRUCTION_SET controls whether or not the new instruction set |
// is in use. The new instruction set contains space for floating point |
// operations, signed and unsigned divide instructions, as well as bit reversal |
// and ... at least two other operations yet to be defined. The decoder alone |
// uses about 70 fewer LUTs, although in practice this works out to 12 fewer |
// when all works out in the wash. Further, floating point and divide |
// instructions will cause an illegal instruction exception if they are not |
// implemented--so software capability can be built to use these instructions |
// immediately, even if the hardware is not yet ready. |
// |
// This option is likely to go away in the future, obsoleting the previous |
// instruction set, so I recommend setting this option and switching to the |
// new instruction set as soon as possible. |
// The instruction set defines an optional compressed instruction set (CIS) |
// complement. These were at one time erroneously called Very Long Instruction |
// Words. They are more appropriately referred to as compressed instructions. |
// The compressed instruction format allows two instructions to be packed into |
// the same instruction word. Some instructions can be compressed, not all. |
// Compressed instructions take the same time to complete. Set OPT_CIS to |
// include these double instructions as part of the instruction set. These |
// instructions are designed to get more code density from the instruction set, |
// and to hopefully take some pain off of the performance of the pre-fetch and |
// instruction cache. |
// |
`define OPT_NEW_INSTRUCTION_SET |
// These new instructions, however, also necessitate a change in the Zip |
// CPU--the Zip CPU can no longer execute instructions atomically. It must |
// now execute non-CIS instructions, or CIS instruction pairs, atomically. |
// This logic has been added into the ZipCPU, but it has not (yet) been |
// tested thoroughly. |
// |
// Oh, and the debugger and the simulator also need to be updated as well |
// to properly handle these. |
// |
// `define OPT_CIS // Adds about 80 LUTs on a Spartan 6 |
// |
// |
// |
223,36 → 241,10
// |
// |
// |
`ifdef OPT_NEW_INSTRUCTION_SET |
// |
// |
// |
// The new instruction set also defines a set of very long instruction words. |
// Well, calling them "very long" instruction words is probably a misnomer, |
// although we're going to do it. They're really 2x16-bit instructions--- |
// instruction words that pack two instructions into one word. (2x14 bit |
// really--'cause you need a bit to note the instruction is a 2x instruction, |
// and then 3-bits for the condition codes ...) Set OPT_VLIW to include these |
// double instructions as part of the new instruction set. These allow a single |
// instruction to contain two instructions within. These instructions are |
// designed to get more code density from the instruction set, and to hopefully |
// take some pain off of the performance of the pre-fetch and instruction cache. |
// |
// These new instructions, however, also necessitate a change in the Zip |
// CPU--the Zip CPU can no longer execute instructions atomically. It must |
// now execute non-VLIW instructions, or VLIW instruction pairs, atomically. |
// This logic has been added into the ZipCPU, but it has not (yet) been |
// tested thoroughly. |
// |
// Oh, and the assembler, the debugger, and the object file dumper, and the |
// simulator all need to be updated as well .... |
// |
`define OPT_VLIW |
// |
// |
`endif // OPT_NEW_INSTRUCTION_SET |
// |
// |
`endif // OPT_SINGLE_FETCH |
// |
// |
/rtl/cpu/cpuops.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: cpuops.v |
// |
12,9 → 12,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
26,38 → 26,44
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
`define LONG_MPY |
module cpuops(i_clk,i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid, |
o_illegal, o_busy); |
parameter IMPLEMENT_MPY = 1; |
`include "cpudefs.v" |
// |
module cpuops(i_clk,i_rst, i_ce, i_op, i_a, i_b, o_c, o_f, o_valid, |
o_busy); |
parameter IMPLEMENT_MPY = `OPT_MULTIPLY; |
input i_clk, i_rst, i_ce; |
input [3:0] i_op; |
input [31:0] i_a, i_b; |
input i_valid; |
output reg [31:0] o_c; |
output wire [3:0] o_f; |
output reg o_valid; |
output wire o_illegal; |
output wire o_busy; |
|
// Rotate-left pre-logic |
wire [63:0] w_rol_tmp; |
assign w_rol_tmp = { i_a, i_a } << i_b[4:0]; |
wire [31:0] w_rol_result; |
assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags |
|
// Shift register pre-logic |
wire [32:0] w_lsr_result, w_asr_result; |
wire [32:0] w_lsr_result, w_asr_result, w_lsl_result; |
wire signed [32:0] w_pre_asr_input, w_pre_asr_shifted; |
assign w_pre_asr_input = { i_a, 1'b0 }; |
assign w_pre_asr_shifted = w_pre_asr_input >>> i_b[4:0]; |
assign w_asr_result = (|i_b[31:5])? {(33){i_a[31]}} |
: ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR |
assign w_lsr_result = (|i_b[31:5])? 33'h00 |
: ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR |
: w_pre_asr_shifted;// ASR |
assign w_lsr_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00 |
:((i_b[5])?{32'h0,i_a[31]} |
|
: ( { i_a, 1'b0 } >> (i_b[4:0]) ));// LSR |
assign w_lsl_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00 |
:((i_b[5])?{i_a[0], 32'h0} |
: ({1'b0, i_a } << i_b[4:0])); // LSL |
|
// Bit reversal pre-logic |
wire [31:0] w_brev_result; |
68,33 → 74,25
assign w_brev_result[k] = i_b[31-k]; |
end endgenerate |
|
// Popcount pre-logic |
wire [31:0] w_popc_result; |
assign w_popc_result[5:0]= |
({5'h0,i_b[ 0]}+{5'h0,i_b[ 1]}+{5'h0,i_b[ 2]}+{5'h0,i_b[ 3]}) |
+({5'h0,i_b[ 4]}+{5'h0,i_b[ 5]}+{5'h0,i_b[ 6]}+{5'h0,i_b[ 7]}) |
+({5'h0,i_b[ 8]}+{5'h0,i_b[ 9]}+{5'h0,i_b[10]}+{5'h0,i_b[11]}) |
+({5'h0,i_b[12]}+{5'h0,i_b[13]}+{5'h0,i_b[14]}+{5'h0,i_b[15]}) |
+({5'h0,i_b[16]}+{5'h0,i_b[17]}+{5'h0,i_b[18]}+{5'h0,i_b[19]}) |
+({5'h0,i_b[20]}+{5'h0,i_b[21]}+{5'h0,i_b[22]}+{5'h0,i_b[23]}) |
+({5'h0,i_b[24]}+{5'h0,i_b[25]}+{5'h0,i_b[26]}+{5'h0,i_b[27]}) |
+({5'h0,i_b[28]}+{5'h0,i_b[29]}+{5'h0,i_b[30]}+{5'h0,i_b[31]}); |
assign w_popc_result[31:6] = 26'h00; |
|
// Prelogic for our flags registers |
wire z, n, v; |
reg c, pre_sign, set_ovfl; |
reg c, pre_sign, set_ovfl, keep_sgn_on_ovfl; |
always @(posedge i_clk) |
if (i_ce) // 1 LUT |
set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP |
set_ovfl<=(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP |
||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD |
||(i_op == 4'h6) // LSL |
||(i_op == 4'h5)); // LSR |
always @(posedge i_clk) |
if (i_ce) // 1 LUT |
keep_sgn_on_ovfl<= |
(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP |
||((i_op==4'h2)&&(i_a[31] == i_b[31]))); // ADD |
|
`ifdef LONG_MPY |
reg mpyhi; |
wire mpybusy; |
`endif |
wire [63:0] mpy_result; // Where we dump the multiply result |
reg mpyhi; // Return the high half of the multiply |
wire mpybusy; // The multiply is busy if true |
wire mpydone; // True if we'll be valid on the next clock; |
|
// A 4-way multiplexer can be done in one 6-LUT. |
// A 16-way multiplexer can therefore be done in 4x 6-LUT's with |
101,260 → 99,266
// the Xilinx multiplexer fabric that follows. |
// Given that we wish to apply this multiplexer approach to 33-bits, |
// this will cost a minimum of 132 6-LUTs. |
|
wire this_is_a_multiply_op; |
assign this_is_a_multiply_op = (i_ce)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'hc)); |
|
generate |
if (IMPLEMENT_MPY == 0) |
begin |
begin // No multiply support. |
assign mpy_result = 63'h00; |
end else if (IMPLEMENT_MPY == 1) |
begin // Our single clock option (no extra clocks) |
wire signed [63:0] w_mpy_a_input, w_mpy_b_input; |
assign w_mpy_a_input = {{(32){(i_a[31])&(i_op[0])}},i_a[31:0]}; |
assign w_mpy_b_input = {{(32){(i_b[31])&(i_op[0])}},i_b[31:0]}; |
assign mpy_result = w_mpy_a_input * w_mpy_b_input; |
assign mpybusy = 1'b0; |
assign mpydone = 1'b0; |
always @(*) mpyhi = 1'b0; // Not needed |
end else if (IMPLEMENT_MPY == 2) |
begin // Our two clock option (ALU must pause for 1 clock) |
reg signed [63:0] r_mpy_a_input, r_mpy_b_input; |
always @(posedge i_clk) |
if (i_ce) |
begin |
pre_sign <= (i_a[31]); |
c <= 1'b0; |
casez(i_op) |
4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB |
4'b0001: o_c <= i_a & i_b; // BTST/And |
4'b0010:{c,o_c } <= i_a + i_b; // Add |
4'b0011: o_c <= i_a | i_b; // Or |
4'b0100: o_c <= i_a ^ i_b; // Xor |
4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR |
4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL |
4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR |
`ifndef LONG_MPY |
4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI |
`endif |
4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO |
// 4'h1010: The unimplemented MPYU, |
// 4'h1011: and here for the unimplemented MPYS |
4'b1100: o_c <= w_brev_result; // BREV |
4'b1101: o_c <= w_popc_result; // POPC |
4'b1110: o_c <= w_rol_result; // ROL |
default: o_c <= i_b; // MOV, LDI |
endcase |
r_mpy_a_input <={{(32){(i_a[31])&(i_op[0])}},i_a[31:0]}; |
r_mpy_b_input <={{(32){(i_b[31])&(i_op[0])}},i_b[31:0]}; |
end |
|
assign o_busy = 1'b0; |
assign mpy_result = r_mpy_a_input * r_mpy_b_input; |
assign mpybusy = 1'b0; |
|
reg r_illegal; |
initial mpypipe = 1'b0; |
reg mpypipe; |
always @(posedge i_clk) |
r_illegal <= (i_ce)&&((i_op == 4'ha)||(i_op == 4'hb) |
`ifdef LONG_MPY |
||(i_op == 4'h8) |
if (i_rst) |
mpypipe <= 1'b0; |
else |
mpypipe <= (this_is_a_multiply_op); |
|
assign mpydone = mpypipe; // this_is_a_multiply_op; |
always @(posedge i_clk) |
if (this_is_a_multiply_op) |
mpyhi = i_op[1]; |
end else if (IMPLEMENT_MPY == 3) |
begin // Our three clock option (ALU pauses for 2 clocks) |
reg signed [63:0] r_smpy_result; |
reg [63:0] r_umpy_result; |
reg signed [31:0] r_mpy_a_input, r_mpy_b_input; |
reg [1:0] mpypipe; |
reg [1:0] r_sgn; |
|
initial mpypipe = 2'b0; |
always @(posedge i_clk) |
if (i_rst) |
mpypipe <= 2'b0; |
else |
mpypipe <= { mpypipe[0], this_is_a_multiply_op }; |
|
// First clock |
always @(posedge i_clk) |
begin |
r_mpy_a_input <= i_a[31:0]; |
r_mpy_b_input <= i_b[31:0]; |
r_sgn <= { r_sgn[0], i_op[0] }; |
end |
|
// Second clock |
`ifdef VERILATOR |
wire signed [63:0] s_mpy_a_input, s_mpy_b_input; |
wire [63:0] u_mpy_a_input, u_mpy_b_input; |
|
assign s_mpy_a_input = {{(32){r_mpy_a_input[31]}},r_mpy_a_input}; |
assign s_mpy_b_input = {{(32){r_mpy_b_input[31]}},r_mpy_b_input}; |
assign u_mpy_a_input = {32'h00,r_mpy_a_input}; |
assign u_mpy_b_input = {32'h00,r_mpy_b_input}; |
always @(posedge i_clk) |
r_smpy_result = s_mpy_a_input * s_mpy_b_input; |
always @(posedge i_clk) |
r_umpy_result = u_mpy_a_input * u_mpy_b_input; |
`else |
|
wire [31:0] u_mpy_a_input, u_mpy_b_input; |
|
assign u_mpy_a_input = r_mpy_a_input; |
assign u_mpy_b_input = r_mpy_b_input; |
|
always @(posedge i_clk) |
r_smpy_result = r_mpy_a_input * r_mpy_b_input; |
always @(posedge i_clk) |
r_umpy_result = u_mpy_a_input * u_mpy_b_input; |
`endif |
); |
assign o_illegal = r_illegal; |
end else begin |
// |
// Multiply pre-logic |
// |
`ifdef LONG_MPY |
|
always @(posedge i_clk) |
if (this_is_a_multiply_op) |
mpyhi = i_op[1]; |
assign mpybusy = mpypipe[0]; |
assign mpy_result = (r_sgn[1])?r_smpy_result:r_umpy_result; |
assign mpydone = mpypipe[1]; |
|
// Results are then set on the third clock |
end else // if (IMPLEMENT_MPY <= 4) |
begin // The three clock option |
reg [63:0] r_mpy_result; |
if (IMPLEMENT_MPY == 1) |
begin // Our two clock option (one clock extra) |
reg signed [64:0] r_mpy_a_input, r_mpy_b_input; |
reg mpypipe, x; |
initial mpypipe = 1'b0; |
always @(posedge i_clk) |
mpypipe <= (i_ce)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'h8)); |
always @(posedge i_clk) |
if (i_ce) |
begin |
r_mpy_a_input <= {{(33){(i_a[31])&(i_op[0])}}, |
i_a[31:0]}; |
r_mpy_b_input <= {{(33){(i_b[31])&(i_op[0])}}, |
i_b[31:0]}; |
end |
always @(posedge i_clk) |
if (mpypipe) |
{x, r_mpy_result} = r_mpy_a_input |
* r_mpy_b_input; |
always @(posedge i_clk) |
if (i_ce) |
mpyhi = i_op[1]; |
assign mpybusy = mpypipe; |
end else if (IMPLEMENT_MPY == 2) |
begin // The three clock option |
reg [31:0] r_mpy_a_input, r_mpy_b_input; |
reg r_mpy_signed; |
reg [1:0] mpypipe; |
reg [31:0] r_mpy_a_input, r_mpy_b_input; |
reg r_mpy_signed; |
reg [2:0] mpypipe; |
|
// First clock, latch in the inputs |
always @(posedge i_clk) |
begin |
// mpypipe indicates we have a multiply in the |
// pipeline. In this case, the multiply |
// pipeline is a two stage pipeline, so we need |
// two bits in the pipe. |
mpypipe[0] <= (i_ce)&&((i_op[3:1]==3'h5) |
||(i_op[3:0]==4'h8)); |
// First clock, latch in the inputs |
always @(posedge i_clk) |
begin |
// mpypipe indicates we have a multiply in the |
// pipeline. In this case, the multiply |
// pipeline is a two stage pipeline, so we need |
// two bits in the pipe. |
if (i_rst) |
mpypipe <= 3'h0; |
else begin |
mpypipe[0] <= this_is_a_multiply_op; |
mpypipe[1] <= mpypipe[0]; |
|
if (i_op[0]) // i.e. if signed multiply |
begin |
r_mpy_a_input <= {(~i_a[31]),i_a[30:0]}; |
r_mpy_b_input <= {(~i_b[31]),i_b[30:0]}; |
end else begin |
r_mpy_a_input <= i_a[31:0]; |
r_mpy_b_input <= i_b[31:0]; |
end |
// The signed bit really only matters in the |
// case of 64 bit multiply. We'll keep track |
// of it, though, and pretend in all other |
// cases. |
r_mpy_signed <= i_op[0]; |
|
if (i_ce) |
mpyhi = i_op[1]; |
mpypipe[2] <= mpypipe[1]; |
end |
|
assign mpybusy = |mpypipe; |
|
// Second clock, do the multiplies, get the "partial |
// products". Here, we break our input up into two |
// halves, |
// |
// A = (2^16 ah + al) |
// B = (2^16 bh + bl) |
// |
// and use these to compute partial products. |
// |
// AB = (2^32 ah*bh + 2^16 (ah*bl + al*bh) + (al*bl) |
// |
// Since we're following the FOIL algorithm to get here, |
// we'll name these partial products according to FOIL. |
// |
// The trick is what happens if A or B is signed. In |
// those cases, the real value of A will not be given by |
// A = (2^16 ah + al) |
// but rather |
// A = (2^16 ah[31^] + al) - 2^31 |
// (where we have flipped the sign bit of A) |
// and so ... |
// |
// AB= (2^16 ah + al - 2^31) * (2^16 bh + bl - 2^31) |
// = 2^32(ah*bh) |
// +2^16 (ah*bl+al*bh) |
// +(al*bl) |
// - 2^31 (2^16 bh+bl + 2^16 ah+al) |
// - 2^62 |
// = 2^32(ah*bh) |
// +2^16 (ah*bl+al*bh) |
// +(al*bl) |
// - 2^31 (2^16 bh+bl + 2^16 ah+al + 2^31) |
// |
reg [31:0] pp_f, pp_l; // F and L from FOIL |
reg [32:0] pp_oi; // The O and I from FOIL |
reg [32:0] pp_s; |
always @(posedge i_clk) |
if (i_op[0]) // i.e. if signed multiply |
begin |
pp_f<=r_mpy_a_input[31:16]*r_mpy_b_input[31:16]; |
pp_oi<=r_mpy_a_input[31:16]*r_mpy_b_input[15: 0] |
+ r_mpy_a_input[15: 0]*r_mpy_b_input[31:16]; |
pp_l<=r_mpy_a_input[15: 0]*r_mpy_b_input[15: 0]; |
// And a special one for the sign |
if (r_mpy_signed) |
pp_s <= 32'h8000_0000-( |
r_mpy_a_input[31:0] |
+ r_mpy_b_input[31:0]); |
else |
pp_s <= 33'h0; |
r_mpy_a_input <= {(~i_a[31]),i_a[30:0]}; |
r_mpy_b_input <= {(~i_b[31]),i_b[30:0]}; |
end else begin |
r_mpy_a_input <= i_a[31:0]; |
r_mpy_b_input <= i_b[31:0]; |
end |
// The signed bit really only matters in the |
// case of 64 bit multiply. We'll keep track |
// of it, though, and pretend in all other |
// cases. |
r_mpy_signed <= i_op[0]; |
|
// Third clock, add the results and produce a product |
always @(posedge i_clk) |
begin |
r_mpy_result[15:0] <= pp_l[15:0]; |
r_mpy_result[63:16] <= |
{ 32'h00, pp_l[31:16] } |
+ { 15'h00, pp_oi } |
+ { pp_s, 15'h00 } |
+ { pp_f, 16'h00 }; |
end |
end // Fourth clock -- results are available for writeback. |
`else |
wire signed [16:0] w_mpy_a_input, w_mpy_b_input; |
wire [33:0] w_mpy_result; |
reg [31:0] r_mpy_result; |
assign w_mpy_a_input ={ ((i_a[15])&(i_op[0])), i_a[15:0] }; |
assign w_mpy_b_input ={ ((i_b[15])&(i_op[0])), i_b[15:0] }; |
assign w_mpy_result = w_mpy_a_input * w_mpy_b_input; |
always @(posedge i_clk) |
if (i_ce) |
r_mpy_result = w_mpy_result[31:0]; |
`endif |
if (this_is_a_multiply_op) |
mpyhi = i_op[1]; |
end |
|
assign mpybusy = |mpypipe[1:0]; |
assign mpydone = mpypipe[2]; |
|
// Second clock, do the multiplies, get the "partial |
// products". Here, we break our input up into two |
// halves, |
// |
// The master ALU case statement |
// A = (2^16 ah + al) |
// B = (2^16 bh + bl) |
// |
// and use these to compute partial products. |
// |
// AB = (2^32 ah*bh + 2^16 (ah*bl + al*bh) + (al*bl) |
// |
// Since we're following the FOIL algorithm to get here, |
// we'll name these partial products according to FOIL. |
// |
// The trick is what happens if A or B is signed. In |
// those cases, the real value of A will not be given by |
// A = (2^16 ah + al) |
// but rather |
// A = (2^16 ah[31^] + al) - 2^31 |
// (where we have flipped the sign bit of A) |
// and so ... |
// |
// AB= (2^16 ah + al - 2^31) * (2^16 bh + bl - 2^31) |
// = 2^32(ah*bh) |
// +2^16 (ah*bl+al*bh) |
// +(al*bl) |
// - 2^31 (2^16 bh+bl + 2^16 ah+al) |
// - 2^62 |
// = 2^32(ah*bh) |
// +2^16 (ah*bl+al*bh) |
// +(al*bl) |
// - 2^31 (2^16 bh+bl + 2^16 ah+al + 2^31) |
// |
reg [31:0] pp_f, pp_l; // F and L from FOIL |
reg [32:0] pp_oi; // The O and I from FOIL |
reg [32:0] pp_s; |
always @(posedge i_clk) |
if (i_ce) |
begin |
pre_sign <= (i_a[31]); |
c <= 1'b0; |
casez(i_op) |
4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB |
4'b0001: o_c <= i_a & i_b; // BTST/And |
4'b0010:{c,o_c } <= i_a + i_b; // Add |
4'b0011: o_c <= i_a | i_b; // Or |
4'b0100: o_c <= i_a ^ i_b; // Xor |
4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR |
4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL |
4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR |
`ifdef LONG_MPY |
4'b1000: o_c <= r_mpy_result[31:0]; // MPY |
`else |
4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI |
`endif |
4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO |
`ifdef LONG_MPY |
4'b1010: o_c <= r_mpy_result[63:32]; // MPYHU |
4'b1011: o_c <= r_mpy_result[63:32]; // MPYHS |
`else |
4'b1010: o_c <= r_mpy_result; // MPYU |
4'b1011: o_c <= r_mpy_result; // MPYS |
`endif |
4'b1100: o_c <= w_brev_result; // BREV |
4'b1101: o_c <= w_popc_result; // POPC |
4'b1110: o_c <= w_rol_result; // ROL |
default: o_c <= i_b; // MOV, LDI |
endcase |
end else if (r_busy) |
`ifdef LONG_MPY |
o_c <= (mpyhi)?r_mpy_result[63:32]:r_mpy_result[31:0]; |
`else |
o_c <= r_mpy_result; |
`endif |
pp_f<=r_mpy_a_input[31:16]*r_mpy_b_input[31:16]; |
pp_oi<=r_mpy_a_input[31:16]*r_mpy_b_input[15: 0] |
+ r_mpy_a_input[15: 0]*r_mpy_b_input[31:16]; |
pp_l<=r_mpy_a_input[15: 0]*r_mpy_b_input[15: 0]; |
// And a special one for the sign |
if (r_mpy_signed) |
pp_s <= 32'h8000_0000-( |
r_mpy_a_input[31:0] |
+ r_mpy_b_input[31:0]); |
else |
pp_s <= 33'h0; |
end |
|
reg r_busy; |
initial r_busy = 1'b0; |
// Third clock, add the results and produce a product |
always @(posedge i_clk) |
r_busy <= (~i_rst)&&(i_ce)&&(i_valid) |
`ifdef LONG_MPY |
&&((i_op[3:1] == 3'h5) |
||(i_op[3:0] == 4'h8))||mpybusy; |
`else |
&&(i_op[3:1] == 3'h5); |
`endif |
begin |
r_mpy_result[15:0] <= pp_l[15:0]; |
r_mpy_result[63:16] <= |
{ 32'h00, pp_l[31:16] } |
+ { 15'h00, pp_oi } |
+ { pp_s, 15'h00 } |
+ { pp_f, 16'h00 }; |
end |
|
assign o_busy = r_busy; |
assign mpy_result = r_mpy_result; |
// Fourth clock -- results are clocked into writeback |
end |
endgenerate // All possible multiply results have been determined |
|
assign o_illegal = 1'b0; |
end endgenerate |
// |
// The master ALU case statement |
// |
always @(posedge i_clk) |
if (i_ce) |
begin |
pre_sign <= (i_a[31]); |
c <= 1'b0; |
casez(i_op) |
4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB |
4'b0001: o_c <= i_a & i_b; // BTST/And |
4'b0010:{c,o_c } <= i_a + i_b; // Add |
4'b0011: o_c <= i_a | i_b; // Or |
4'b0100: o_c <= i_a ^ i_b; // Xor |
4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR |
4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL |
4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR |
4'b1000: o_c <= w_brev_result; // BREV |
4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO |
4'b1010: o_c <= mpy_result[63:32]; // MPYHU |
4'b1011: o_c <= mpy_result[63:32]; // MPYHS |
4'b1100: o_c <= mpy_result[31:0]; // MPY |
default: o_c <= i_b; // MOV, LDI |
endcase |
end else // if (mpydone) |
o_c <= (mpyhi)?mpy_result[63:32]:mpy_result[31:0]; |
|
reg r_busy; |
initial r_busy = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_busy <= 1'b0; |
else |
r_busy <= ((IMPLEMENT_MPY > 1) |
&&(this_is_a_multiply_op))||mpybusy; |
assign o_busy = (r_busy); // ||((IMPLEMENT_MPY>1)&&(this_is_a_multiply_op)); |
|
|
assign z = (o_c == 32'h0000); |
assign n = (o_c[31]); |
assign v = (set_ovfl)&&(pre_sign != o_c[31]); |
wire vx = (keep_sgn_on_ovfl)&&(pre_sign != o_c[31]); |
|
assign o_f = { v, n, c, z }; |
assign o_f = { v, n^vx, c, z }; |
|
initial o_valid = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
o_valid <= 1'b0; |
else if (IMPLEMENT_MPY <= 1) |
o_valid <= (i_ce); |
else |
o_valid <= (i_ce)&&(i_valid) |
`ifdef LONG_MPY |
&&(i_op[3:1] != 3'h5)&&(i_op[3:0] != 4'h8) |
||(o_busy)&&(~mpybusy); |
`else |
&&(i_op[3:1] != 3'h5)||(o_busy); |
`endif |
o_valid <=((i_ce)&&(!this_is_a_multiply_op))||(mpydone); |
|
endmodule |
/rtl/cpu/div.v
0,0 → 1,260
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: div.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: Provide an Integer divide capability to the Zip CPU. Provides |
// for both signed and unsigned divide. |
// |
// Steps: |
// i_rst The DIVide unit starts in idle. It can also be placed into an |
// idle by asserting the reset input. |
// |
// i_wr When i_rst is asserted, a divide begins. On the next clock: |
// |
// o_busy is set high so everyone else knows we are at work and they can |
// wait for us to complete. |
// |
// pre_sign is set to true if we need to do a signed divide. In this |
// case, we take a clock cycle to turn the divide into an unsigned |
// divide. |
// |
// o_quotient, a place to store our result, is initialized to all zeros. |
// |
// r_dividend is set to the numerator |
// |
// r_divisor is set to 2^31 * the denominator (shift left by 31, or add |
// 31 zeros to the right of the number. |
// |
// pre_sign When true (clock cycle after i_wr), a clock cycle is used |
// to take the absolute value of the various arguments (r_dividend |
// and r_divisor), and to calculate what sign the output result |
// should be. |
// |
// |
// At this point, the divide is has started. The divide works by walking |
// through every shift of the |
// |
// DIVIDEND over the |
// DIVISOR |
// |
// If the DIVISOR is bigger than the dividend, the divisor is shifted |
// right, and nothing is done to the output quotient. |
// |
// DIVIDEND |
// DIVISOR |
// |
// This repeats, until DIVISOR is less than or equal to the divident, as in |
// |
// DIVIDEND |
// DIVISOR |
// |
// At this point, if the DIVISOR is less than the dividend, the |
// divisor is subtracted from the dividend, and the DIVISOR is again |
// shifted to the right. Further, a '1' bit gets set in the output |
// quotient. |
// |
// Once we've done this for 32 clocks, we've accumulated our answer into |
// the output quotient, and we can proceed to the next step. If the |
// result will be signed, the next step negates the quotient, otherwise |
// it returns the result. |
// |
// On the clock when we are done, o_busy is set to false, and o_valid set |
// to true. (It is a violation of the ZipCPU internal protocol for both |
// busy and valid to ever be true on the same clock. It is also a |
// violation for busy to be false with valid true thereafter.) |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// `include "cpudefs.v" |
// |
module div(i_clk, i_rst, i_wr, i_signed, i_numerator, i_denominator, |
o_busy, o_valid, o_err, o_quotient, o_flags); |
parameter BW=32, LGBW = 5; |
input i_clk, i_rst; |
// Input parameters |
input i_wr, i_signed; |
input [(BW-1):0] i_numerator, i_denominator; |
// Output parameters |
output reg o_busy, o_valid, o_err; |
output reg [(BW-1):0] o_quotient; |
output wire [3:0] o_flags; |
|
// r_busy is an internal busy register. It will clear one clock |
// before we are valid, so it can't be o_busy ... |
// |
reg r_busy; |
reg [(2*BW-2):0] r_divisor; |
reg [(BW-1):0] r_dividend; |
wire [(BW):0] diff; // , xdiff[(BW-1):0]; |
assign diff = r_dividend - r_divisor[(BW-1):0]; |
// assign xdiff= r_dividend - { 1'b0, r_divisor[(BW-1):1] }; |
|
reg r_sign, pre_sign, r_z, r_c, last_bit; |
reg [(LGBW-1):0] r_bit; |
|
reg zero_divisor; |
initial zero_divisor = 1'b0; |
always @(posedge i_clk) |
zero_divisor <= (r_divisor == 0)&&(r_busy); |
|
initial r_busy = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_busy <= 1'b0; |
else if (i_wr) |
r_busy <= 1'b1; |
else if ((last_bit)||(zero_divisor)) |
r_busy <= 1'b0; |
|
initial o_busy = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
o_busy <= 1'b0; |
else if (i_wr) |
o_busy <= 1'b1; |
else if (((last_bit)&&(~r_sign))||(zero_divisor)) |
o_busy <= 1'b0; |
else if (~r_busy) |
o_busy <= 1'b0; |
|
always @(posedge i_clk) |
if ((i_rst)||(i_wr)) |
o_valid <= 1'b0; |
else if (r_busy) |
begin |
if ((last_bit)||(zero_divisor)) |
o_valid <= (zero_divisor)||(~r_sign); |
end else if (r_sign) |
begin |
o_valid <= (~zero_divisor); // 1'b1; |
end else |
o_valid <= 1'b0; |
|
initial o_err = 1'b0; |
always @(posedge i_clk) |
if((i_rst)||(o_valid)) |
o_err <= 1'b0; |
else if (((r_busy)||(r_sign))&&(zero_divisor)) |
o_err <= 1'b1; |
else |
o_err <= 1'b0; |
|
initial last_bit = 1'b0; |
always @(posedge i_clk) |
if ((i_wr)||(pre_sign)||(i_rst)) |
last_bit <= 1'b0; |
else if (r_busy) |
last_bit <= (r_bit == {{(LGBW-1){1'b0}},1'b1}); |
|
always @(posedge i_clk) |
// if (i_rst) r_busy <= 1'b0; |
// else |
if (i_wr) |
begin |
// |
// Set our values upon an initial command. Here's |
// where we come in and start. |
// |
// r_busy <= 1'b1; |
// |
o_quotient <= 0; |
r_bit <= {(LGBW){1'b1}}; |
r_divisor <= { i_denominator, {(BW-1){1'b0}} }; |
r_dividend <= i_numerator; |
r_sign <= 1'b0; |
pre_sign <= i_signed; |
r_z <= 1'b1; |
end else if (pre_sign) |
begin |
// |
// Note that we only come in here, for one clock, if |
// our initial value may have been signed. If we are |
// doing an unsigned divide, we then skip this step. |
// |
r_sign <= ((r_divisor[(2*BW-2)])^(r_dividend[(BW-1)])); |
// Negate our dividend if necessary so that it becomes |
// a magnitude only value |
if (r_dividend[BW-1]) |
r_dividend <= -r_dividend; |
// Do the same with the divisor--rendering it into |
// a magnitude only. |
if (r_divisor[(2*BW-2)]) |
r_divisor[(2*BW-2):(BW-1)] <= -r_divisor[(2*BW-2):(BW-1)]; |
// |
// We only do this stage for a single clock, so go on |
// with the rest of the divide otherwise. |
pre_sign <= 1'b0; |
end else if (r_busy) |
begin |
// While the divide is taking place, we examine each bit |
// in turn here. |
// |
r_bit <= r_bit + {(LGBW){1'b1}}; // r_bit = r_bit - 1; |
r_divisor <= { 1'b0, r_divisor[(2*BW-2):1] }; |
if (|r_divisor[(2*BW-2):(BW)]) |
begin |
end else if (diff[BW]) |
begin |
// |
// diff = r_dividend - r_divisor[(BW-1):0]; |
// |
// If this value was negative, there wasn't |
// enough value in the dividend to support |
// pulling off a bit. We'll move down a bit |
// therefore and try again. |
// |
end else begin |
// |
// Put a '1' into our output accumulator. |
// Subtract the divisor from the dividend, |
// and then move on to the next bit |
// |
r_dividend <= diff[(BW-1):0]; |
o_quotient[r_bit[(LGBW-1):0]] <= 1'b1; |
r_z <= 1'b0; |
end |
r_sign <= (r_sign)&&(~zero_divisor); |
end else if (r_sign) |
begin |
r_sign <= 1'b0; |
o_quotient <= -o_quotient; |
end |
|
// Set Carry on an exact divide |
wire w_n; |
always @(posedge i_clk) |
r_c <= (r_busy)&&((diff == 0)||(r_dividend == 0)); |
assign w_n = o_quotient[(BW-1)]; |
|
assign o_flags = { 1'b0, w_n, r_c, r_z }; |
endmodule |
/rtl/cpu/icontrol.v
52,7 → 52,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
64,6 → 64,11
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
70,6 → 75,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module icontrol(i_clk, i_reset, i_wr, i_proc_bus, o_proc_bus, |
i_brd_ints, o_interrupt); |
parameter IUSED = 15; |
/rtl/cpu/idecode.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: idecode.v |
// |
17,9 → 17,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
31,14 → 31,20
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// |
`define CPU_SP_REG 4'hd |
`define CPU_CC_REG 4'he |
`define CPU_PC_REG 4'hf |
// |
56,7 → 62,8
o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock, |
o_wR, o_rA, o_rB, |
o_early_branch, o_branch_pc, o_ljmp, |
o_pipe |
o_pipe, |
o_sim, o_sim_immv |
); |
parameter ADDRESS_WIDTH=24, IMPLEMENT_MPY=1, EARLY_BRANCHING=1, |
IMPLEMENT_DIVIDE=1, IMPLEMENT_FPU=0, AW = ADDRESS_WIDTH; |
67,11 → 74,11
input i_pf_valid, i_illegal; |
output wire o_phase; |
output reg o_illegal; |
output reg [(AW-1):0] o_pc; |
output reg [AW:0] o_pc; |
output reg o_gie; |
output reg [6:0] o_dcdR, o_dcdA, o_dcdB; |
output wire [31:0] o_I; |
output wire o_zI; |
output reg o_zI; |
output reg [3:0] o_cond; |
output reg o_wF; |
output reg [3:0] o_op; |
82,13 → 89,19
output wire [(AW-1):0] o_branch_pc; |
output wire o_ljmp; |
output wire o_pipe; |
output reg o_sim /* verilator public_flat */; |
output reg [22:0] o_sim_immv /* verilator public_flat */; |
|
wire dcdA_stall, dcdB_stall, dcdF_stall; |
wire o_dcd_early_branch; |
wire [(AW-1):0] o_dcd_branch_pc; |
reg o_dcdI, o_dcdIz; |
`ifdef OPT_PIPELINED |
reg r_lock, r_pipe, r_zI; |
reg r_lock; |
`endif |
`ifdef OPT_PIPELINED_BUS_ACCESS |
reg r_pipe; |
`endif |
|
|
wire [4:0] w_op; |
98,18 → 111,18
wire w_dcdA_pc, w_dcdA_cc; |
wire w_dcdB_pc, w_dcdB_cc; |
wire [3:0] w_cond; |
wire w_wF, w_dcdM, w_dcdDV, w_dcdFP; |
wire w_wF, w_mem, w_sto, w_lod, w_div, w_fpu; |
wire w_wR, w_rA, w_rB, w_wR_n; |
wire w_ljmp; |
wire w_ljmp, w_ljmp_dly, w_cis_ljmp; |
wire [31:0] iword; |
|
|
`ifdef OPT_VLIW |
reg [16:0] r_nxt_half; |
`ifdef OPT_CIS |
reg [15:0] r_nxt_half; |
assign iword = (o_phase) |
// set second half as a NOOP ... but really |
// set second half as a NOOP ... but really |
// shouldn't matter |
? { r_nxt_half[16:7], 1'b0, r_nxt_half[6:0], 5'b11000, 3'h7, 6'h00 } |
? { r_nxt_half[15:0], i_instruction[15:0] } |
: i_instruction; |
`else |
assign iword = { 1'b0, i_instruction[30:0] }; |
117,27 → 130,87
|
generate |
if (EARLY_BRANCHING != 0) |
begin |
`ifdef OPT_CIS |
reg r_pre_ljmp; |
always @(posedge i_clk) |
if ((i_rst)||(o_early_branch)) |
r_pre_ljmp <= 1'b0; |
else if ((i_ce)&&(i_pf_valid)) |
r_pre_ljmp <= (!o_phase)&&(i_instruction[31]) |
&&(i_instruction[14:0] == 15'h7cf8); |
else if (i_ce) |
r_pre_ljmp <= 1'b0; |
|
assign w_cis_ljmp = r_pre_ljmp; |
`else |
assign w_cis_ljmp = 1'b0; |
`endif |
// 0.1111.10010.000.1.1111.000000000... |
// 0111.1100.1000.0111.11000.... |
assign w_ljmp = (iword == 32'h7c87c000); |
else |
end else begin |
assign w_cis_ljmp = 1'b0; |
assign w_ljmp = 1'b0; |
end |
endgenerate |
|
`ifdef OPT_CIS |
`ifdef VERILATOR |
wire [4:0] w_cis_op; |
always @(iword) |
if (!iword[31]) |
w_cis_op = w_op; |
else case(iword[26:24]) |
3'h0: w_cis_op = 5'h00; |
3'h1: w_cis_op = 5'h01; |
3'h2: w_cis_op = 5'h02; |
3'h3: w_cis_op = 5'h10; |
3'h4: w_cis_op = 5'h12; |
3'h5: w_cis_op = 5'h13; |
3'h6: w_cis_op = 5'h18; |
3'h7: w_cis_op = 5'h0d; |
endcase |
`else |
reg [4:0] w_cis_op; |
always @(iword,w_op) |
if (!iword[31]) |
w_cis_op <= w_op; |
else case(iword[26:24]) |
3'h0: w_cis_op <= 5'h00; |
3'h1: w_cis_op <= 5'h01; |
3'h2: w_cis_op <= 5'h02; |
3'h3: w_cis_op <= 5'h10; |
3'h4: w_cis_op <= 5'h12; |
3'h5: w_cis_op <= 5'h13; |
3'h6: w_cis_op <= 5'h18; |
3'h7: w_cis_op <= 5'h0d; |
endcase |
`endif |
`else |
wire [4:0] w_cis_op; |
assign w_cis_op = w_op; |
`endif |
|
assign w_op= iword[26:22]; |
assign w_mov = (w_op == 5'h0f); |
assign w_ldi = (w_op[4:1] == 4'hb); |
assign w_brev = (w_op == 5'hc); |
assign w_cmptst = (w_op[4:1] == 4'h8); |
assign w_ldilo = (w_op[4:0] == 5'h9); |
assign w_ALU = (~w_op[4]); |
assign w_mov = (w_cis_op == 5'h0d); |
assign w_ldi = (w_cis_op[4:1] == 4'hc); |
assign w_brev = (w_cis_op == 5'h8); |
assign w_cmptst = (w_cis_op[4:1] == 4'h8); |
assign w_ldilo = (w_cis_op[4:0] == 5'h9); |
assign w_ALU = (!w_cis_op[4]) // anything with [4]==0, but ... |
&&(w_cis_op[3:1] != 3'h7); // not the divide |
|
// 4 LUTs |
|
// w_dcdR (4 LUTs) |
// |
// What register will we be placing results into (if at all)? |
// |
// Two parts to the result register: the register set, given for |
// moves in i_word[18] but only for the supervisor, and the other |
// moves in iword[18] but only for the supervisor, and the other |
// four bits encoded in the instruction. |
// |
assign w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie, |
assign w_dcdR = { ((!iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie, |
iword[30:27] }; |
// 2 LUTs |
// |
144,14 → 217,20
// If the result register is either CC or PC, and this would otherwise |
// be a floating point instruction with floating point opcode of 0, |
// then this is a NOOP. |
assign w_noop = (w_op[4:0] == 5'h18)&&(w_dcdR[3:1] == 3'h7); |
assign w_noop = (!iword[31])&&(w_op[4:0] == 5'h1f)&&( |
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1] == 3'h7)) |
||(IMPLEMENT_FPU==0)); |
|
// 4 LUTs |
assign w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie, |
iword[17:14] }; |
// dcdB - What register is used in the opB? |
// |
assign w_dcdB[4] = ((!iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie; |
assign w_dcdB[3:0]= (iword[31]) |
? (((!iword[23])&&(iword[26:25]==2'b10)) |
? `CPU_SP_REG : iword[22:19]) |
: iword[17:14]; |
|
// 0 LUTs |
assign w_dcdA = w_dcdR; |
assign w_dcdA = w_dcdR; // on ZipCPU, A is always result reg |
// 2 LUTs, 1 delay each |
assign w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG}); |
assign w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG}); |
159,8 → 238,8
assign w_dcdA_pc = w_dcdR_pc; |
assign w_dcdA_cc = w_dcdR_cc; |
// 2 LUTs, 1 delays each |
assign w_dcdB_pc = (w_dcdB[3:0] == `CPU_PC_REG); |
assign w_dcdB_cc = (w_dcdB[3:0] == `CPU_CC_REG); |
assign w_dcdB_pc = (w_rB)&&(w_dcdB[3:0] == `CPU_PC_REG); |
assign w_dcdB_cc = (w_rB)&&(w_dcdB[3:0] == `CPU_CC_REG); |
|
// Under what condition will we execute this |
// instruction? Only the load immediate instruction |
167,46 → 246,55
// is completely unconditional. |
// |
// 3+4 LUTs |
assign w_cond = (w_ldi) ? 4'h8 : |
(iword[31])?{(iword[20:19]==2'b00), |
1'b0,iword[20:19]} |
: { (iword[21:19]==3'h0), iword[21:19] }; |
assign w_cond = ((w_ldi)||(iword[31])) ? 4'h8 : |
{ (iword[21:19]==3'h0), iword[21:19] }; |
|
// 1 LUT |
assign w_dcdM = (w_op[4:1] == 4'h9); |
assign w_mem = (w_cis_op[4:3] == 2'b10)&&(w_cis_op[2:1] !=2'b00); |
assign w_sto = (w_mem)&&( w_cis_op[0]); |
assign w_lod = (w_mem)&&(!w_cis_op[0]); |
// 1 LUT |
assign w_dcdDV = (w_op[4:1] == 4'ha); |
// 1 LUT |
assign w_dcdFP = (w_op[4:3] == 2'b11)&&(w_dcdR[3:1] != 3'h7); |
// 4 LUT's--since it depends upon FP/NOOP condition (vs 1 before) |
// Everything reads A but ... NOOP/BREAK/LOCK, LDI, LOD, MOV |
assign w_rA = (w_dcdFP) |
// Divide's read A |
||(w_dcdDV) |
// ALU read's A, unless it's a MOV to A |
// This includes LDIHI/LDILO |
||((~w_op[4])&&(w_op[3:0]!=4'hf)) |
// STO's read A |
||((w_dcdM)&&(w_op[0])) |
// Test/compares |
||(w_op[4:1]== 4'h8); |
// 1 LUTs -- do we read a register for operand B? Specifically, do |
// we need to stall if the register is not (yet) ready? |
assign w_rB = (w_mov)||((iword[18])&&(~w_ldi)); |
assign w_div = (!iword[31])&&(w_op[4:1] == 4'h7); |
// 2 LUTs |
assign w_fpu = (!iword[31])&&(w_op[4:3] == 2'b11) |
&&(w_dcdR[3:1] != 3'h7)&&(w_op[2:1] != 2'b00); |
// |
// rA - do we need to read register A? |
assign w_rA = // Floating point reads reg A |
((w_fpu)&&(w_cis_op[4:1] != 4'hf)) |
// Divide's read A |
||(w_div) |
// ALU ops read A, |
// except for MOV's and BREV's which don't |
||((w_ALU)&&(!w_brev)&&(!w_mov)) |
// STO's read A |
||(w_sto) |
// Test/compares |
||(w_cmptst); |
// rB -- do we read a register for operand B? Specifically, do we |
// add the registers value to the immediate to create opB? |
assign w_rB = (w_mov) |
||((!iword[31])&&(iword[18])&&(!w_ldi)) |
||(( iword[31])&&(iword[23])&&(!w_ldi)) |
// If using compressed instruction sets, |
// we *always* read on memory operands. |
||(( iword[31])&&(w_mem)); |
// wR -- will we be writing our result back? |
// wR_n = !wR |
// 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR |
assign w_wR_n = ((w_dcdM)&&(w_op[0])) |
||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)) |
assign w_wR_n = (w_sto) |
||((!iword[31])&&(w_cis_op[4:3]==2'b11) |
&&(w_cis_op[2:1]!=2'b00) |
&&(w_dcdR[3:1]==3'h7)) |
||(w_cmptst); |
assign w_wR = ~w_wR_n; |
// |
// 1-output bit (5 Opcode bits, 4 out-reg bits, 3 condition bits) |
// |
// This'd be 4 LUTs, save that we have the carve out for NOOPs |
// and writes to the PC/CC register(s). |
// wF -- do we write flags when we are done? |
// |
assign w_wF = (w_cmptst) |
||((w_cond[3])&&((w_dcdFP)||(w_dcdDV) |
||((w_ALU)&&(~w_mov)&&(~w_ldilo)&&(~w_brev) |
&&(iword[30:28] != 3'h7)))); |
||((w_cond[3])&&((w_fpu)||(w_div) |
||((w_ALU)&&(!w_mov)&&(!w_ldilo)&&(!w_brev) |
&&(w_dcdR[3:1] != 3'h7)))); |
|
// Bottom 13 bits: no LUT's |
// w_dcd[12: 0] -- no LUTs |
218,16 → 306,23
wire w_Iz; |
|
assign w_fullI = (w_ldi) ? { iword[22:0] } // LDI |
:((w_mov) ?{ {(23-13){iword[12]}}, iword[12:0] } // Move |
// MOVE immediates have one less bit |
:((w_mov) ?{ {(23-13){iword[12]}}, iword[12:0] } |
// Normal Op-B immediate ... 18 or 14 bits |
:((~iword[18]) ? { {(23-18){iword[17]}}, iword[17:0] } |
: { {(23-14){iword[13]}}, iword[13:0] } |
)); |
|
`ifdef OPT_VLIW |
wire [5:0] w_halfI; |
assign w_halfI = (w_ldi) ? iword[5:0] |
:((iword[5]) ? 6'h00 : {iword[4],iword[4:0]}); |
assign w_I = (iword[31])? {{(23-6){w_halfI[5]}}, w_halfI }:w_fullI; |
`ifdef OPT_CIS |
wire [7:0] w_halfbits; |
assign w_halfbits = iword[23:16]; |
|
wire [7:0] w_halfI; |
assign w_halfI = (iword[26:24]==3'h6) ? w_halfbits[7:0] |
:(w_halfbits[7])? |
{ {(6){w_halfbits[2]}}, w_halfbits[1:0]} |
:{ w_halfbits[6], w_halfbits[6:0] }; |
assign w_I = (iword[31])?{{(23-8){w_halfI[7]}}, w_halfI }:w_fullI; |
`else |
assign w_I = w_fullI; |
`endif |
234,21 → 329,25
assign w_Iz = (w_I == 0); |
|
|
`ifdef OPT_VLIW |
`ifdef OPT_CIS |
// |
// The o_phase parameter is special. It needs to let the software |
// following know that it cannot break/interrupt on an o_phase asserted |
// instruction, lest the break take place between the first and second |
// half of a VLIW instruction. To do this, o_phase must be asserted |
// half of a CIS instruction. To do this, o_phase must be asserted |
// when the first instruction half is valid, but not asserted on either |
// a 32-bit instruction or the second half of a 2x16-bit instruction. |
reg r_phase; |
initial r_phase = 1'b0; |
always @(posedge i_clk) |
if (i_rst) // When no instruction is in the pipe, phase is zero |
if ((i_rst) // When no instruction is in the pipe, phase is zero |
||(o_early_branch)||(w_ljmp_dly)) |
r_phase <= 1'b0; |
else if ((i_ce)&&(i_pf_valid)) |
r_phase <= (o_phase)? 1'b0 |
: ((i_instruction[31])&&(i_pf_valid)); |
else if (i_ce) |
r_phase <= (o_phase)? 1'b0:(i_instruction[31]); |
r_phase <= 1'b0; |
// Phase is '1' on the first instruction of a two-part set |
// But, due to the delay in processing, it's '1' when our output is |
// valid for that first part, but that'll be the same time we |
267,32 → 366,32
o_illegal <= 1'b0; |
else if (i_ce) |
begin |
`ifdef OPT_VLIW |
`ifdef OPT_CIS |
o_illegal <= (i_illegal); |
`else |
o_illegal <= ((i_illegal) || (i_instruction[31])); |
`endif |
if ((IMPLEMENT_MPY!=1)&&(w_op[4:1]==4'h5)) |
if ((IMPLEMENT_MPY==0)&&((w_cis_op[4:1]==4'h5)||(w_cis_op[4:0]==5'h0c))) |
o_illegal <= 1'b1; |
|
if ((IMPLEMENT_DIVIDE==0)&&(w_dcdDV)) |
if ((IMPLEMENT_DIVIDE==0)&&(w_div)) |
o_illegal <= 1'b1; |
else if ((IMPLEMENT_DIVIDE!=0)&&(w_dcdDV)&&(w_dcdR[3:1]==3'h7)) |
else if ((IMPLEMENT_DIVIDE!=0)&&(w_div)&&(w_dcdR[3:1]==3'h7)) |
o_illegal <= 1'b1; |
|
|
if ((IMPLEMENT_FPU!=0)&&(w_dcdFP)&&(w_dcdR[3:1]==3'h7)) |
if ((IMPLEMENT_FPU==0)&&(w_fpu)) |
o_illegal <= 1'b1; |
else if ((IMPLEMENT_FPU==0)&&(w_dcdFP)) |
o_illegal <= 1'b1; |
|
if ((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7) |
if ((w_cis_op[4:3]==2'b11)&&(w_cis_op[2:1]!=2'b00) |
&&(w_dcdR[3:1]==3'h7) |
&&( |
(w_op[2:0] != 3'h1) // BREAK |
(w_cis_op[2:0] != 3'h4) // BREAK |
`ifdef OPT_PIPELINED |
&&(w_op[2:0] != 3'h2) // LOCK |
&&(w_cis_op[2:0] != 3'h5) // LOCK |
`endif |
&&(w_op[2:0] != 3'h0))) // NOOP |
// SIM instructions are always illegal |
&&(w_cis_op[2:0] != 3'h7))) // NOOP |
o_illegal <= 1'b1; |
end |
|
300,16 → 399,19
always @(posedge i_clk) |
if (i_ce) |
begin |
`ifdef OPT_VLIW |
if (~o_phase) |
begin |
`ifdef OPT_CIS |
if (!o_phase) |
o_gie<= i_gie; |
// i.e. dcd_pc+1 |
o_pc <= i_pc+{{(AW-1){1'b0}},1'b1}; |
end |
|
if ((iword[31])&&(!o_phase)) |
o_pc <= { i_pc, 1'b1 }; |
else if ((iword[31])&&(i_pf_valid)) |
o_pc <= { i_pc, 1'b0 }; |
else |
o_pc <= { i_pc + 1'b1, 1'b0 }; |
`else |
o_gie<= i_gie; |
o_pc <= i_pc+{{(AW-1){1'b0}},1'b1}; |
o_pc <= { i_pc + 1'b1, 1'b0 }; |
`endif |
|
// Under what condition will we execute this |
327,12 → 429,12
// the ALU. Likewise, the two compare instructions |
// CMP and TST becomes SUB and AND here as well. |
// We keep only the bottom four bits, since we've |
// already done the rest of the decode necessary to |
// already done the rest of the decode necessary to |
// settle between the other instructions. For example, |
// o_FP plus these four bits uniquely defines the FP |
// instruction, o_DV plus the bottom of these defines |
// the divide, etc. |
o_op <= (w_ldi)||(w_noop)? 4'hf:w_op[3:0]; |
o_op <= ((w_ldi)||(w_noop))? 4'hd : w_cis_op[3:0]; |
|
// Default values |
o_dcdR <= { w_dcdR_cc, w_dcdR_pc, w_dcdR}; |
342,37 → 444,44
o_rA <= w_rA; |
o_rB <= w_rB; |
r_I <= w_I; |
`ifdef OPT_PIPELINED |
r_zI <= w_Iz; |
`endif |
o_zI <= w_Iz; |
|
// Turn a NOOP into an ALU operation--subtract in |
// Turn a NOOP into an ALU operation--subtract in |
// particular, although it doesn't really matter as long |
// as it doesn't take longer than one clock. Note |
// also that this depends upon not setting any registers |
// or flags, which should already be true. |
o_ALU <= (w_ALU)||(w_ldi)||(w_cmptst)||(w_noop); // 2 LUT |
o_M <= w_dcdM; |
o_DV <= w_dcdDV; |
o_FP <= w_dcdFP; |
o_ALU <= (w_ALU)||(w_ldi)||(w_cmptst)||(w_noop); |
o_M <= w_mem; |
o_DV <= w_div; |
o_FP <= w_fpu; |
|
o_break <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b001); |
o_break <= (!iword[31])&&(w_op[4:0]==5'h1c)&&( |
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7)) |
||(IMPLEMENT_FPU==0)); |
`ifdef OPT_PIPELINED |
r_lock <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b010); |
r_lock <= (!iword[31])&&(w_op[4:0]==5'h1d)&&( |
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7)) |
||(IMPLEMENT_FPU==0)); |
`endif |
`ifdef OPT_VLIW |
r_nxt_half <= { iword[31], iword[13:5], |
((iword[21])? iword[20:19] : 2'h0), |
iword[4:0] }; |
`ifdef OPT_CIS |
r_nxt_half <= { iword[31], iword[14:0] }; |
`endif |
|
`ifdef VERILATOR |
// Support the SIM instruction(s) |
o_sim <= (!iword[31])&&(w_op[4:1] == 4'hf) |
&&(w_dcdR[3:1] == 3'h7); |
`else |
o_sim <= 1'b0; |
`endif |
o_sim_immv <= iword[22:0]; |
end |
|
`ifdef OPT_PIPELINED |
assign o_lock = r_lock; |
assign o_zI = r_zI; |
`else |
assign o_lock = 1'b0; |
assign o_zI = 1'b0; |
`endif |
|
generate |
385,6 → 494,10
always @(posedge i_clk) |
if (i_rst) |
r_ljmp <= 1'b0; |
`ifdef OPT_CIS |
else if ((i_ce)&&(o_phase)) |
r_ljmp <= w_cis_ljmp; |
`endif |
else if ((i_ce)&&(i_pf_valid)) |
r_ljmp <= (w_ljmp); |
assign o_ljmp = r_ljmp; |
397,17 → 510,14
if (r_ljmp) |
// LOD (PC),PC |
r_early_branch <= 1'b1; |
else if ((~iword[31])&&(iword[30:27]==`CPU_PC_REG)&&(w_cond[3])) |
else if ((!iword[31])&&(iword[30:27]==`CPU_PC_REG) |
&&(w_cond[3])) |
begin |
if (w_op[4:1] == 4'hb) // LDI to PC |
// LDI x,PC |
r_early_branch <= 1'b1; |
else if ((w_op[4:0]==5'h02)&&(~iword[18])) |
if ((w_op[4:0]==5'h02)&&(!iword[18])) |
// Add x,PC |
r_early_branch <= 1'b1; |
else begin |
else |
r_early_branch <= 1'b0; |
end |
end else |
r_early_branch <= 1'b0; |
end else if (i_ce) |
417,18 → 527,18
if (i_ce) |
begin |
if (r_ljmp) |
r_branch_pc <= iword[(AW-1):0]; |
else if (w_op[4:1] == 4'hb) // LDI |
r_branch_pc <= {{(AW-23){iword[22]}},iword[22:0]}; |
r_branch_pc <= iword[(AW+1):2]; |
else // Add x,PC |
r_branch_pc <= i_pc |
+ {{(AW-17){iword[17]}},iword[16:0]} |
+ {{(AW-15){iword[17]}},iword[16:2]} |
+ {{(AW-1){1'b0}},1'b1}; |
end |
|
assign w_ljmp_dly = r_ljmp; |
assign o_early_branch = r_early_branch; |
assign o_branch_pc = r_branch_pc; |
end else begin |
assign w_ljmp_dly = 1'b0; |
assign o_early_branch = 1'b0; |
assign o_branch_pc = {(AW){1'b0}}; |
assign o_ljmp = 1'b0; |
445,22 → 555,35
// Note that we're not using iword here ... there's a lot of logic |
// taking place, and it's only valid if the new word is not compressed. |
// |
`ifdef OPT_PIPELINED |
reg r_valid; |
reg r_pipe; |
`ifdef OPT_PIPELINED_BUS_ACCESS |
initial r_pipe = 1'b0; |
always @(posedge i_clk) |
if (i_ce) |
r_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31]) |
&&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22]) |
&&(i_instruction[17:14] == o_dcdB[3:0]) |
&&(i_instruction[17:14] != o_dcdA[3:0]) |
r_pipe <= (r_valid)&&((i_pf_valid)||(o_phase)) |
// Both must be memory operations |
&&(w_mem)&&(o_M) |
// Both must be writes, or both stores |
&&(o_op[0] == w_cis_op[0]) |
// Both must be register ops |
&&(w_rB) |
// Both must use the same register for B |
&&(w_dcdB[3:0] == o_dcdB[3:0]) |
// But ... the result can never be B |
&&((o_op[0]) |
||(w_dcdB[3:0] != o_dcdA[3:0])) |
// Needs to be to the mode, supervisor or user |
&&(i_gie == o_gie) |
// Same condition, or no condition before |
&&((i_instruction[21:19]==o_cond[2:0]) |
||(o_cond[2:0] == 3'h0)) |
&&((i_instruction[13:0]==r_I[13:0]) |
||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1))); |
// Same immediate |
&&((w_I[13:2]==r_I[13:2]) |
||({1'b0, w_I[13:2]}==(r_I[13:2]+12'h1))); |
assign o_pipe = r_pipe; |
`else |
assign o_pipe = 1'b0; |
`endif |
|
always @(posedge i_clk) |
if (i_rst) |
471,11 → 594,8
r_valid <= 1'b1; |
else if (~i_stalled) |
r_valid <= 1'b0; |
`else |
assign o_pipe = 1'b0; |
`endif |
|
|
|
assign o_I = { {(32-22){r_I[22]}}, r_I[21:0] }; |
|
endmodule |
/rtl/cpu/memops.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: memops.v |
// |
17,9 → 17,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
31,24 → 31,31
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module memops(i_clk, i_rst, i_stb, i_lock, |
i_op, i_addr, i_data, i_oreg, |
o_busy, o_valid, o_err, o_wreg, o_result, |
o_wb_cyc_gbl, o_wb_cyc_lcl, |
o_wb_stb_gbl, o_wb_stb_lcl, |
o_wb_we, o_wb_addr, o_wb_data, |
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data); |
parameter ADDRESS_WIDTH=24, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH; |
parameter ADDRESS_WIDTH=30, IMPLEMENT_LOCK=0, WITH_LOCAL_BUS=0; |
localparam AW=ADDRESS_WIDTH; |
input i_clk, i_rst; |
input i_stb, i_lock; |
// CPU interface |
input i_op; |
input [2:0] i_op; |
input [31:0] i_addr; |
input [31:0] i_data; |
input [4:0] i_oreg; |
66,6 → 73,7
output reg o_wb_we; |
output reg [(AW-1):0] o_wb_addr; |
output reg [31:0] o_wb_data; |
output reg [3:0] o_wb_sel; |
// Wishbone inputs |
input i_wb_ack, i_wb_stall, i_wb_err; |
input [31:0] i_wb_data; |
72,8 → 80,8
|
reg r_wb_cyc_gbl, r_wb_cyc_lcl; |
wire gbl_stb, lcl_stb; |
assign lcl_stb = (i_stb)&&(i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0); |
assign gbl_stb = (i_stb)&&((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0)); |
assign lcl_stb = (i_stb)&&(WITH_LOCAL_BUS!=0)&&(i_addr[31:24]==8'hff); |
assign gbl_stb = (i_stb)&&((WITH_LOCAL_BUS==0)||(i_addr[31:24]!=8'hff)); |
|
initial r_wb_cyc_gbl = 1'b0; |
initial r_wb_cyc_lcl = 1'b0; |
104,13 → 112,54
o_wb_stb_lcl <= (o_wb_stb_lcl)&&(i_wb_stall); |
else |
o_wb_stb_lcl <= lcl_stb; // Grab wishbone on new operation |
|
reg [3:0] r_op; |
always @(posedge i_clk) |
if (i_stb) |
begin |
o_wb_we <= i_op; |
o_wb_data <= i_data; |
o_wb_addr <= i_addr[(AW-1):0]; |
o_wb_we <= i_op[0]; |
casez({ i_op[2:1], i_addr[1:0] }) |
`ifdef ZERO_ON_IDLE |
4'b100?: o_wb_data <= { i_data[15:0], 16'h00 }; |
4'b101?: o_wb_data <= { 16'h00, i_data[15:0] }; |
4'b1100: o_wb_data <= { i_data[7:0], 24'h00 }; |
4'b1101: o_wb_data <= { 8'h00, i_data[7:0], 16'h00 }; |
4'b1110: o_wb_data <= { 16'h00, i_data[7:0], 8'h00 }; |
4'b1111: o_wb_data <= { 24'h00, i_data[7:0] }; |
`else |
4'b10??: o_wb_data <= { (2){ i_data[15:0] } }; |
4'b11??: o_wb_data <= { (4){ i_data[7:0] } }; |
`endif |
default: o_wb_data <= i_data; |
endcase |
|
o_wb_addr <= i_addr[(AW+1):2]; |
`ifdef SET_SEL_ON_READ |
if (i_op[0] == 1'b0) |
o_wb_sel <= 4'hf; |
else |
`endif |
casez({ i_op[2:1], i_addr[1:0] }) |
4'b01??: o_wb_sel <= 4'b1111; |
4'b100?: o_wb_sel <= 4'b1100; |
4'b101?: o_wb_sel <= 4'b0011; |
4'b1100: o_wb_sel <= 4'b1000; |
4'b1101: o_wb_sel <= 4'b0100; |
4'b1110: o_wb_sel <= 4'b0010; |
4'b1111: o_wb_sel <= 4'b0001; |
default: o_wb_sel <= 4'b1111; |
endcase |
r_op <= { i_op[2:1] , i_addr[1:0] }; |
end |
`ifdef ZERO_ON_IDLE |
else if ((!o_wb_cyc_gbl)&&(!o_wb_cyc_lcl)) |
begin |
o_wb_we <= 1'b0; |
o_wb_addr <= 0; |
o_wb_data <= 32'h0; |
o_wb_sel <= 4'h0; |
end |
`endif |
|
initial o_valid = 1'b0; |
always @(posedge i_clk) |
124,8 → 173,21
if (i_stb) |
o_wreg <= i_oreg; |
always @(posedge i_clk) |
if (i_wb_ack) |
o_result <= i_wb_data; |
`ifdef ZERO_ON_IDLE |
if (!i_wb_ack) |
o_result <= 32'h0; |
else |
`endif |
casez(r_op) |
4'b01??: o_result <= i_wb_data; |
4'b100?: o_result <= { 16'h00, i_wb_data[31:16] }; |
4'b101?: o_result <= { 16'h00, i_wb_data[15: 0] }; |
4'b1100: o_result <= { 24'h00, i_wb_data[31:24] }; |
4'b1101: o_result <= { 24'h00, i_wb_data[23:16] }; |
4'b1110: o_result <= { 24'h00, i_wb_data[15: 8] }; |
4'b1111: o_result <= { 24'h00, i_wb_data[ 7: 0] }; |
default: o_result <= i_wb_data; |
endcase |
|
generate |
if (IMPLEMENT_LOCK != 0) |
/rtl/cpu/prefetch.v
24,7 → 24,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
36,6 → 36,11
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
42,6 → 47,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// Flash requires a minimum of 4 clocks per byte to read, so that would be |
// 4*(4bytes/32bit word) = 16 clocks per word read---and that's in pipeline |
// mode which this prefetch does not support. In non--pipelined mode, the |
114,7 → 120,7
if ((o_wb_cyc)&&(i_wb_ack)) |
begin |
o_valid <= (i_pc == o_wb_addr)&&(~i_wb_err); |
o_illegal <= i_wb_err; |
o_illegal <= (i_wb_err)&&(i_pc == o_wb_addr); |
end else if (i_stalled_n) |
begin |
o_valid <= 1'b0; |
/rtl/cpu/wbdblpriarb.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbdblpriarb.v |
// |
42,9 → 42,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
56,19 → 56,25
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
module wbdblpriarb(i_clk, i_rst, |
// |
module wbdblpriarb(i_clk, i_rst, |
// Bus A |
i_a_cyc_a,i_a_cyc_b,i_a_stb_a,i_a_stb_b,i_a_we,i_a_adr, i_a_dat, o_a_ack, o_a_stall, o_a_err, |
i_a_cyc_a,i_a_cyc_b,i_a_stb_a,i_a_stb_b,i_a_we,i_a_adr, i_a_dat, i_a_sel, o_a_ack, o_a_stall, o_a_err, |
// Bus B |
i_b_cyc_a,i_b_cyc_b,i_b_stb_a,i_b_stb_b,i_b_we,i_b_adr, i_b_dat, o_b_ack, o_b_stall, o_b_err, |
i_b_cyc_a,i_b_cyc_b,i_b_stb_a,i_b_stb_b,i_b_we,i_b_adr, i_b_dat, i_b_sel, o_b_ack, o_b_stall, o_b_err, |
// Both buses |
o_cyc_a, o_cyc_b, o_stb_a, o_stb_b, o_we, o_adr, o_dat, |
o_cyc_a, o_cyc_b, o_stb_a, o_stb_b, o_we, o_adr, o_dat, o_sel, |
i_ack, i_stall, i_err); |
parameter DW=32, AW=32; |
// Wishbone doesn't use an i_ce signal. While it could, they dislike |
78,28 → 84,31
input i_a_cyc_a, i_a_cyc_b, i_a_stb_a, i_a_stb_b, i_a_we; |
input [(AW-1):0] i_a_adr; |
input [(DW-1):0] i_a_dat; |
input [(DW/8-1):0] i_a_sel; |
output wire o_a_ack, o_a_stall, o_a_err; |
// Bus B |
input i_b_cyc_a, i_b_cyc_b, i_b_stb_a, i_b_stb_b, i_b_we; |
input [(AW-1):0] i_b_adr; |
input [(DW-1):0] i_b_dat; |
input [(DW/8-1):0] i_b_sel; |
output wire o_b_ack, o_b_stall, o_b_err; |
// |
// |
output wire o_cyc_a,o_cyc_b, o_stb_a, o_stb_b, o_we; |
output wire [(AW-1):0] o_adr; |
output wire [(DW-1):0] o_dat; |
output wire [(DW/8-1):0] o_sel; |
input i_ack, i_stall, i_err; |
|
// All of our logic is really captured in the 'r_a_owner' register. |
// This register determines who owns the bus. If no one is requesting |
// the bus, ownership goes to A on the next clock. Otherwise, if B is |
// the bus, ownership goes to A on the next clock. Otherwise, if B is |
// requesting the bus and A is not, then ownership goes to not A on |
// the next clock. (Sounds simple ...) |
// |
// The CYC logic is here to make certain that, by the time we determine |
// who the bus owner is, we can do so based upon determined criteria. |
assign o_cyc_a = (~i_rst)&&((r_a_owner) ? i_a_cyc_a : i_b_cyc_a); |
assign o_cyc_b = (~i_rst)&&((r_a_owner) ? i_a_cyc_b : i_b_cyc_b); |
assign o_cyc_a = ((r_a_owner) ? i_a_cyc_a : i_b_cyc_a); |
assign o_cyc_b = ((r_a_owner) ? i_a_cyc_b : i_b_cyc_b); |
reg r_a_owner; |
initial r_a_owner = 1'b1; |
always @(posedge i_clk) |
109,9 → 118,34
r_a_owner <= ((i_b_cyc_a)||(i_b_cyc_b))? 1'b0:1'b1; |
|
|
assign o_we = (r_a_owner) ? i_a_we : i_b_we; |
`ifdef ZERO_ON_IDLE |
// |
// ZERO_ON_IDLE uses more logic than the alternative. It should be |
// useful for reducing power, as these circuits tend to drive wires |
// all the way across the design, but it may also slow down the master |
// clock. I've used it as an option when using VERILATOR, 'cause |
// zeroing things on idle can make them stand out all the more when |
// staring at wires and dumps and such. |
// |
wire o_cyc, o_stb; |
assign o_cyc = ((o_cyc_a)||(o_cyc_b)); |
assign o_stb = (o_cyc)&&((o_stb_a)||(o_stb_b)); |
assign o_stb_a = (r_a_owner) ? (i_a_stb_a)&&(o_cyc_a) : (i_b_stb_a)&&(o_cyc_a); |
assign o_stb_b = (r_a_owner) ? (i_a_stb_b)&&(o_cyc_b) : (i_b_stb_b)&&(o_cyc_b); |
assign o_adr = ((o_stb_a)|(o_stb_b))?((r_a_owner) ? i_a_adr : i_b_adr):0; |
assign o_dat = (o_stb)?((r_a_owner) ? i_a_dat : i_b_dat):0; |
assign o_sel = (o_stb)?((r_a_owner) ? i_a_sel : i_b_sel):0; |
assign o_a_ack = (o_cyc)&&( r_a_owner) ? i_ack : 1'b0; |
assign o_b_ack = (o_cyc)&&(~r_a_owner) ? i_ack : 1'b0; |
assign o_a_stall = (o_cyc)&&( r_a_owner) ? i_stall : 1'b1; |
assign o_b_stall = (o_cyc)&&(~r_a_owner) ? i_stall : 1'b1; |
assign o_a_err = (o_cyc)&&( r_a_owner) ? i_err : 1'b0; |
assign o_b_err = (o_cyc)&&(~r_a_owner) ? i_err : 1'b0; |
`else |
// Realistically, if neither master owns the bus, the output is a |
// don't care. Thus we trigger off whether or not 'A' owns the bus. |
// If 'B' owns it all we care is that 'A' does not. Likewise, if |
// If 'B' owns it all we care is that 'A' does not. Likewise, if |
// neither owns the bus than the values on these various lines are |
// irrelevant. |
assign o_stb_a = (r_a_owner) ? i_a_stb_a : i_b_stb_a; |
119,6 → 153,7
assign o_we = (r_a_owner) ? i_a_we : i_b_we; |
assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr; |
assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat; |
assign o_sel = (r_a_owner) ? i_a_sel : i_b_sel; |
|
// We cannot allow the return acknowledgement to ever go high if |
// the master in question does not own the bus. Hence we force it |
137,6 → 172,7
// |
assign o_a_err = ( r_a_owner) ? i_err : 1'b0; |
assign o_b_err = (~r_a_owner) ? i_err : 1'b0; |
`endif |
|
endmodule |
|
/rtl/cpu/wbdmac.v
0,0 → 1,491
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbdmac.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: Wishbone DMA controller |
// |
// This module is controllable via the wishbone, and moves values from |
// one location in the wishbone address space to another. The amount of |
// memory moved at any given time can be up to 4kB, or equivalently 1kW. |
// Four registers control this DMA controller: a control/status register, |
// a length register, a source WB address and a destination WB address. |
// These register may be read at any time, but they may only be written |
// to when the controller is idle. |
// |
// The meanings of three of the setup registers should be self explanatory: |
// - The length register controls the total number of words to |
// transfer. |
// - The source address register controls where the DMA controller |
// reads from. This address may or may not be incremented |
// after each read, depending upon the setting in the |
// control/status register. |
// - The destination address register, which controls where the DMA |
// controller writes to. This address may or may not be |
// incremented after each write, also depending upon the |
// setting in the control/status register. |
// |
// It is the control/status register, at local address zero, that needs |
// more definition: |
// |
// Bits: |
// 31 R Write protect If this is set to one, it means the |
// write protect bit is set and the controller |
// is therefore idle. This bit will be set upon |
// completing any transfer. |
// 30 R Error. The controller stopped mid-transfer |
// after receiving a bus error. |
// 29 R/W inc_s_n If set to one, the source address |
// will not increment from one read to the next. |
// 28 R/W inc_d_n If set to one, the destination address |
// will not increment from one write to the next. |
// 27 R Always 0 |
// 26..16 R nread Indicates how many words have been read, |
// and not necessarily written (yet). This |
// combined with the cfg_len parameter should tell |
// exactly where the controller is at mid-transfer. |
// 27..16 W WriteProtect When a 12'h3db is written to these |
// bits, the write protect bit will be cleared. |
// |
// 15 R/W on_dev_trigger When set to '1', the controller will |
// wait for an external interrupt before starting. |
// 14..10 R/W device_id This determines which external interrupt |
// will trigger a transfer. |
// 9..0 R/W transfer_len How many bytes to transfer at one time. |
// The minimum transfer length is one, while zero |
// is mapped to a transfer length of 1kW. |
// |
// |
// To use this, follow this checklist: |
// 1. Wait for any prior DMA operation to complete |
// (Read address 0, wait 'till either top bit is set or cfg_len==0) |
// 2. Write values into length, source and destination address. |
// (writei(3, &vals) should be sufficient for this.) |
// 3. Enable the DMAC interrupt in whatever interrupt controller is present |
// on the system. |
// 4. Write the final start command to the setup/control/status register: |
// Set inc_s_n, inc_d_n, on_dev_trigger, dev_trigger, |
// appropriately for your task |
// Write 12'h3db to the upper word. |
// Set the lower word to either all zeros, or a smaller transfer |
// length if desired. |
// 5. wait() for the interrupt and the operation to complete. |
// Prior to completion, number of items successfully transferred |
// be read from the length register. If the internal buffer is |
// being used, then you can read how much has been read into that |
// buffer by reading from bits 25..16 of this control/status |
// register. |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
`define DMA_IDLE 3'b000 |
`define DMA_WAIT 3'b001 |
`define DMA_READ_REQ 3'b010 |
`define DMA_READ_ACK 3'b011 |
`define DMA_PRE_WRITE 3'b100 |
`define DMA_WRITE_REQ 3'b101 |
`define DMA_WRITE_ACK 3'b110 |
|
module wbdmac(i_clk, i_rst, |
i_swb_cyc, i_swb_stb, i_swb_we, i_swb_addr, i_swb_data, |
o_swb_ack, o_swb_stall, o_swb_data, |
o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data, |
i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err, |
i_dev_ints, |
o_interrupt); |
parameter ADDRESS_WIDTH=32, LGMEMLEN = 10, |
DW=32, LGDV=5,AW=ADDRESS_WIDTH; |
input i_clk, i_rst; |
// Slave/control wishbone inputs |
input i_swb_cyc, i_swb_stb, i_swb_we; |
input [1:0] i_swb_addr; |
input [(DW-1):0] i_swb_data; |
// Slave/control wishbone outputs |
output reg o_swb_ack; |
output wire o_swb_stall; |
output reg [(DW-1):0] o_swb_data; |
// Master/DMA wishbone control |
output wire o_mwb_cyc, o_mwb_stb, o_mwb_we; |
output reg [(AW-1):0] o_mwb_addr; |
output reg [(DW-1):0] o_mwb_data; |
// Master/DMA wishbone responses from the bus |
input i_mwb_ack, i_mwb_stall; |
input [(DW-1):0] i_mwb_data; |
input i_mwb_err; |
// The interrupt device interrupt lines |
input [(DW-1):0] i_dev_ints; |
// An interrupt to be set upon completion |
output reg o_interrupt; |
// Need to release the bus for a higher priority user |
// This logic had lots of problems, so it is being |
// removed. If you want to make sure the bus is available |
// for a higher priority user, adjust the transfer length |
// accordingly. |
// |
// input i_other_busmaster_requests_bus; |
// |
|
|
reg [2:0] dma_state; |
reg cfg_err, cfg_len_nonzero; |
reg [(AW-1):0] cfg_waddr, cfg_raddr, cfg_len; |
reg [(LGMEMLEN-1):0] cfg_blocklen_sub_one; |
reg cfg_incs, cfg_incd; |
reg [(LGDV-1):0] cfg_dev_trigger; |
reg cfg_on_dev_trigger; |
|
// Single block operations: We'll read, then write, up to a single |
// memory block here. |
|
reg [(DW-1):0] dma_mem [0:(((1<<LGMEMLEN))-1)]; |
reg [(LGMEMLEN):0] nread, nwritten, nwacks, nracks; |
wire [(AW-1):0] bus_nracks; |
assign bus_nracks = { {(AW-LGMEMLEN-1){1'b0}}, nracks }; |
|
reg last_read_request, last_read_ack, |
last_write_request, last_write_ack; |
reg trigger, abort, user_halt; |
|
initial dma_state = `DMA_IDLE; |
initial o_interrupt = 1'b0; |
initial cfg_len = {(AW){1'b0}}; |
initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}}; |
initial cfg_on_dev_trigger = 1'b0; |
initial cfg_len_nonzero = 1'b0; |
always @(posedge i_clk) |
case(dma_state) |
`DMA_IDLE: begin |
o_mwb_addr <= cfg_raddr; |
nwritten <= 0; |
nread <= 0; |
nracks <= 0; |
nwacks <= 0; |
cfg_len_nonzero <= (|cfg_len); |
|
// When the slave wishbone writes, and we are in this |
// (ready) configuration, then allow the DMA to be controlled |
// and thus to start. |
if ((i_swb_stb)&&(i_swb_we)) |
begin |
case(i_swb_addr) |
2'b00: begin |
if ((i_swb_data[31:16] == 16'h0fed) |
&&(cfg_len_nonzero)) |
dma_state <= `DMA_WAIT; |
cfg_blocklen_sub_one |
<= i_swb_data[(LGMEMLEN-1):0] |
+ {(LGMEMLEN){1'b1}}; |
// i.e. -1; |
cfg_dev_trigger <= i_swb_data[14:10]; |
cfg_on_dev_trigger <= i_swb_data[15]; |
cfg_incs <= ~i_swb_data[29]; |
cfg_incd <= ~i_swb_data[28]; |
end |
2'b01: begin |
cfg_len <= i_swb_data[(AW-1):0]; |
cfg_len_nonzero <= (|i_swb_data[(AW-1):0]); |
end |
2'b10: cfg_raddr <= i_swb_data[(AW-1):0]; |
2'b11: cfg_waddr <= i_swb_data[(AW-1):0]; |
endcase |
end end |
`DMA_WAIT: begin |
o_mwb_addr <= cfg_raddr; |
nracks <= 0; |
nwacks <= 0; |
nwritten <= 0; |
nread <= 0; |
if (abort) |
dma_state <= `DMA_IDLE; |
else if (user_halt) |
dma_state <= `DMA_IDLE; |
else if (trigger) |
dma_state <= `DMA_READ_REQ; |
end |
`DMA_READ_REQ: begin |
nwritten <= 0; |
|
if (~i_mwb_stall) |
begin |
// Number of read acknowledgements needed |
nracks <= nracks+1; |
if (last_read_request) |
//((nracks == {1'b0, cfg_blocklen_sub_one})||(bus_nracks == cfg_len-1)) |
// Wishbone interruptus |
dma_state <= `DMA_READ_ACK; |
if (cfg_incs) |
o_mwb_addr <= o_mwb_addr |
+ {{(AW-1){1'b0}},1'b1}; |
end |
|
if (user_halt) |
dma_state <= `DMA_READ_ACK; |
if (i_mwb_err) |
begin |
cfg_len <= 0; |
dma_state <= `DMA_IDLE; |
end |
|
if (abort) |
dma_state <= `DMA_IDLE; |
if (i_mwb_ack) |
begin |
nread <= nread+1; |
if (cfg_incs) |
cfg_raddr <= cfg_raddr |
+ {{(AW-1){1'b0}},1'b1}; |
end end |
`DMA_READ_ACK: begin |
nwritten <= 0; |
|
if (i_mwb_err) |
begin |
cfg_len <= 0; |
dma_state <= `DMA_IDLE; |
end else if (i_mwb_ack) |
begin |
nread <= nread+1; |
if (last_read_ack) // (nread+1 == nracks) |
dma_state <= `DMA_PRE_WRITE; |
if (user_halt) |
dma_state <= `DMA_IDLE; |
if (cfg_incs) |
cfg_raddr <= cfg_raddr |
+ {{(AW-1){1'b0}},1'b1}; |
end |
if (abort) |
dma_state <= `DMA_IDLE; |
end |
`DMA_PRE_WRITE: begin |
o_mwb_addr <= cfg_waddr; |
dma_state <= (abort)?`DMA_IDLE:`DMA_WRITE_REQ; |
end |
`DMA_WRITE_REQ: begin |
if (~i_mwb_stall) |
begin |
nwritten <= nwritten+1; |
if (last_write_request) // (nwritten == nread-1) |
// Wishbone interruptus |
dma_state <= `DMA_WRITE_ACK; |
if (cfg_incd) |
begin |
o_mwb_addr <= o_mwb_addr |
+ {{(AW-1){1'b0}},1'b1}; |
cfg_waddr <= cfg_waddr |
+ {{(AW-1){1'b0}},1'b1}; |
end |
end |
|
if (i_mwb_err) |
begin |
cfg_len <= 0; |
dma_state <= `DMA_IDLE; |
end |
if (i_mwb_ack) |
begin |
nwacks <= nwacks+1; |
cfg_len <= cfg_len +{(AW){1'b1}}; // -1 |
end |
if (user_halt) |
dma_state <= `DMA_WRITE_ACK; |
if (abort) |
dma_state <= `DMA_IDLE; |
end |
`DMA_WRITE_ACK: begin |
if (i_mwb_err) |
begin |
cfg_len <= 0; |
nread <= 0; |
dma_state <= `DMA_IDLE; |
end else if (i_mwb_ack) |
begin |
nwacks <= nwacks+1; |
cfg_len <= cfg_len +{(AW){1'b1}};//cfg_len -= 1; |
if (last_write_ack) // (nwacks+1 == nwritten) |
begin |
nread <= 0; |
dma_state <= (cfg_len == 1)?`DMA_IDLE:`DMA_WAIT; |
end |
end |
|
if (abort) |
dma_state <= `DMA_IDLE; |
end |
default: |
dma_state <= `DMA_IDLE; |
endcase |
|
initial o_interrupt = 1'b0; |
always @(posedge i_clk) |
o_interrupt <= ((dma_state == `DMA_WRITE_ACK)&&(i_mwb_ack) |
&&(last_write_ack) |
&&(cfg_len == {{(AW-1){1'b0}},1'b1})) |
||((dma_state != `DMA_IDLE)&&(i_mwb_err)); |
|
initial cfg_err = 1'b0; |
always @(posedge i_clk) |
if (dma_state == `DMA_IDLE) |
begin |
if ((i_swb_stb)&&(i_swb_we)&&(i_swb_addr==2'b00)) |
cfg_err <= 1'b0; |
end else if (((i_mwb_err)&&(o_mwb_cyc))||(abort)) |
cfg_err <= 1'b1; |
|
initial last_read_request = 1'b0; |
always @(posedge i_clk) |
if ((dma_state == `DMA_WAIT)||(dma_state == `DMA_READ_REQ)) |
begin |
if ((~i_mwb_stall)&&(dma_state == `DMA_READ_REQ)) |
begin |
last_read_request <= |
(nracks + 1 == { 1'b0, cfg_blocklen_sub_one}) |
||(bus_nracks == cfg_len-2); |
end else |
last_read_request <= |
(nracks== { 1'b0, cfg_blocklen_sub_one}) |
||(bus_nracks == cfg_len-1); |
end else |
last_read_request <= 1'b0; |
|
initial last_read_ack = 1'b0; |
always @(posedge i_clk) |
if ((dma_state == `DMA_READ_REQ)||(dma_state == `DMA_READ_ACK)) |
begin |
if ((i_mwb_ack)&&((~o_mwb_stb)||(i_mwb_stall))) |
last_read_ack <= (nread+2 == nracks); |
else |
last_read_ack <= (nread+1 == nracks); |
end else |
last_read_ack <= 1'b0; |
|
initial last_write_request = 1'b0; |
always @(posedge i_clk) |
if (dma_state == `DMA_PRE_WRITE) |
last_write_request <= (nread <= 1); |
else if (dma_state == `DMA_WRITE_REQ) |
begin |
if (i_mwb_stall) |
last_write_request <= (nwritten >= nread-1); |
else |
last_write_request <= (nwritten >= nread-2); |
end else |
last_write_request <= 1'b0; |
|
initial last_write_ack = 1'b0; |
always @(posedge i_clk) |
if((dma_state == `DMA_WRITE_REQ)||(dma_state == `DMA_WRITE_ACK)) |
begin |
if ((i_mwb_ack)&&((~o_mwb_stb)||(i_mwb_stall))) |
last_write_ack <= (nwacks+2 == nwritten); |
else |
last_write_ack <= (nwacks+1 == nwritten); |
end else |
last_write_ack <= 1'b0; |
|
assign o_mwb_cyc = (dma_state == `DMA_READ_REQ) |
||(dma_state == `DMA_READ_ACK) |
||(dma_state == `DMA_WRITE_REQ) |
||(dma_state == `DMA_WRITE_ACK); |
|
assign o_mwb_stb = (dma_state == `DMA_READ_REQ) |
||(dma_state == `DMA_WRITE_REQ); |
|
assign o_mwb_we = (dma_state == `DMA_PRE_WRITE) |
||(dma_state == `DMA_WRITE_REQ) |
||(dma_state == `DMA_WRITE_ACK); |
|
// |
// This is tricky. In order for Vivado to consider dma_mem to be a |
// proper memory, it must have a simple address fed into it. Hence |
// the read_address (rdaddr) register. The problem is that this |
// register must always be one greater than the address we actually |
// want to read from, unless we are idling. So ... the math is touchy. |
// |
reg [(LGMEMLEN-1):0] rdaddr; |
always @(posedge i_clk) |
if((dma_state == `DMA_IDLE)||(dma_state == `DMA_WAIT) |
||(dma_state == `DMA_WRITE_ACK)) |
rdaddr <= 0; |
else if ((dma_state == `DMA_PRE_WRITE) |
||((dma_state==`DMA_WRITE_REQ)&&(~i_mwb_stall))) |
rdaddr <= rdaddr + {{(LGMEMLEN-1){1'b0}},1'b1}; |
always @(posedge i_clk) |
if ((dma_state != `DMA_WRITE_REQ)||(~i_mwb_stall)) |
o_mwb_data <= dma_mem[rdaddr]; |
always @(posedge i_clk) |
if((dma_state == `DMA_READ_REQ)||(dma_state == `DMA_READ_ACK)) |
dma_mem[nread[(LGMEMLEN-1):0]] <= i_mwb_data; |
|
always @(posedge i_clk) |
casez(i_swb_addr) |
2'b00: o_swb_data <= { (dma_state != `DMA_IDLE), cfg_err, |
~cfg_incs, ~cfg_incd, |
1'b0, nread, |
cfg_on_dev_trigger, cfg_dev_trigger, |
cfg_blocklen_sub_one |
}; |
2'b01: o_swb_data <= { {(DW-AW){1'b0}}, cfg_len }; |
2'b10: o_swb_data <= { {(DW-AW){1'b0}}, cfg_raddr}; |
2'b11: o_swb_data <= { {(DW-AW){1'b0}}, cfg_waddr}; |
endcase |
|
// This causes us to wait a minimum of two clocks before starting: One |
// to go into the wait state, and then one while in the wait state to |
// develop the trigger. |
initial trigger = 1'b0; |
always @(posedge i_clk) |
trigger <= (dma_state == `DMA_WAIT) |
&&((~cfg_on_dev_trigger) |
||(i_dev_ints[cfg_dev_trigger])); |
|
// Ack any access. We'll quietly ignore any access where we are busy, |
// but ack it anyway. In other words, before writing to the device, |
// double check that it isn't busy, and then write. |
always @(posedge i_clk) |
o_swb_ack <= (i_swb_stb); |
|
assign o_swb_stall = 1'b0; |
|
initial abort = 1'b0; |
always @(posedge i_clk) |
abort <= (i_rst)||((i_swb_stb)&&(i_swb_we) |
&&(i_swb_addr == 2'b00) |
&&(i_swb_data == 32'hffed0000)); |
|
initial user_halt = 1'b0; |
always @(posedge i_clk) |
user_halt <= ((user_halt)&&(dma_state != `DMA_IDLE)) |
||((i_swb_stb)&&(i_swb_we)&&(dma_state != `DMA_IDLE) |
&&(i_swb_addr == 2'b00) |
&&(i_swb_data == 32'hafed0000)); |
|
endmodule |
|
/rtl/cpu/zipbones.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: zipbones.v |
// |
11,9 → 11,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015, 2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
25,17 → 25,23
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
`include "cpudefs.v" |
// |
module zipbones(i_clk, i_rst, |
// Wishbone master interface from the CPU |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err, |
// Incoming interrupts |
i_ext_int, |
48,14 → 54,15
, o_zip_debug |
`endif |
); |
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32, |
LGICACHE=6, START_HALTED=0, |
AW=ADDRESS_WIDTH; |
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=30, |
LGICACHE=8, START_HALTED=0; |
localparam AW=ADDRESS_WIDTH; |
input i_clk, i_rst; |
// Wishbone master |
output wire o_wb_cyc, o_wb_stb, o_wb_we; |
output wire [(AW-1):0] o_wb_addr; |
output wire [31:0] o_wb_data; |
output wire [3:0] o_wb_sel; |
input i_wb_ack, i_wb_stall; |
input [31:0] i_wb_data; |
input i_wb_err; |
167,7 → 174,10
wire [31:0] cpu_dbg_data; |
assign cpu_dbg_we = ((i_dbg_cyc)&&(i_dbg_stb) |
&&(i_dbg_we)&&(i_dbg_addr)); |
zipcpu #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE) |
zipcpu #(.RESET_ADDRESS(RESET_ADDRESS), |
.ADDRESS_WIDTH(ADDRESS_WIDTH), |
.LGICACHE(LGICACHE), |
.WITH_LOCAL_BUS(0)) |
thecpu(i_clk, cpu_reset, i_ext_int, |
cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we, |
i_dbg_data, cpu_dbg_stall, cpu_dbg_data, |
174,9 → 184,9
cpu_dbg_cc, cpu_break, |
o_wb_cyc, o_wb_stb, |
cpu_lcl_cyc, cpu_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, |
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
i_wb_ack, i_wb_stall, i_wb_data, |
(i_wb_err)||((cpu_lcl_cyc)&&(cpu_lcl_stb)), |
(i_wb_err)||(cpu_lcl_cyc), |
cpu_op_stall, cpu_pf_stall, cpu_i_count |
`ifdef DEBUG_SCOPE |
, o_zip_debug |
/rtl/cpu/zipcpu.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: zipcpu.v |
// |
7,7 → 7,9
// Purpose: This is the top level module holding the core of the Zip CPU |
// together. The Zip CPU is designed to be as simple as possible. |
// (actual implementation aside ...) The instruction set is about as |
// RISC as you can get, there are only 16 instruction types supported. |
// RISC as you can get, with only 26 instruction types currently supported. |
// (There are still 8-instruction Op-Codes reserved for floating point, |
// and 5 which can be used for transactions not requiring registers.) |
// Please see the accompanying spec.pdf file for a description of these |
// instructions. |
// |
16,7 → 18,7
// |
// The Zip CPU is fully pipelined with the following pipeline stages: |
// |
// 1. Prefetch, returns the instruction from memory. |
// 1. Prefetch, returns the instruction from memory. |
// |
// 2. Instruction Decode |
// |
26,10 → 28,11
// |
// 4. Write-back Results |
// |
// Further information about the inner workings of this CPU may be |
// found in the spec.pdf file. (The documentation within this file |
// had become out of date and out of sync with the spec.pdf, so look |
// to the spec.pdf for accurate and up to date information.) |
// Further information about the inner workings of this CPU, such as |
// what causes pipeline stalls, may be found in the spec.pdf file. (The |
// documentation within this file had become out of date and out of sync |
// with the spec.pdf, so look to the spec.pdf for accurate and up to date |
// information.) |
// |
// |
// In general, the pipelining is controlled by three pieces of logic |
69,9 → 72,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
83,26 → 86,23
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// We can either pipeline our fetches, or issue one fetch at a time. Pipelined |
// fetches are more complicated and therefore use more FPGA resources, while |
// single fetches will cause the CPU to stall for about 5 stalls each |
// instruction cycle, effectively reducing the instruction count per clock to |
// about 0.2. However, the area cost may be worth it. Consider: |
// |
// Slice LUTs ZipSystem ZipCPU |
// Single Fetching 2521 1734 |
// Pipelined fetching 2796 2046 |
// |
// |
// |
`define CPU_CC_REG 4'he |
`define CPU_PC_REG 4'hf |
`define CPU_CLRCACHE_BIT 14 // Set to clear the I-cache, automatically clears |
`define CPU_PHASE_BIT 13 // Set if we are executing the latter half of a CIS |
`define CPU_FPUERR_BIT 12 // Floating point error flag, set on error |
`define CPU_DIVERR_BIT 11 // Divide error flag, set on divide by zero |
`define CPU_BUSERR_BIT 10 // Bus error flag, set on error |
109,7 → 109,7
`define CPU_TRAP_BIT 9 // User TRAP has taken place |
`define CPU_ILL_BIT 8 // Illegal instruction |
`define CPU_BREAK_BIT 7 |
`define CPU_STEP_BIT 6 // Will step one or two (VLIW) instructions |
`define CPU_STEP_BIT 6 // Will step one (or two CIS) instructions |
`define CPU_GIE_BIT 5 |
`define CPU_SLEEP_BIT 4 |
// Compile time defines |
125,7 → 125,7
// CPU interface to the wishbone bus |
o_wb_gbl_cyc, o_wb_gbl_stb, |
o_wb_lcl_cyc, o_wb_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, |
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
i_wb_ack, i_wb_stall, i_wb_data, |
i_wb_err, |
// Accounting/CPU usage interface |
134,8 → 134,9
, o_debug |
`endif |
); |
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24, |
LGICACHE=6; |
parameter [31:0] RESET_ADDRESS=32'h0100000; |
parameter ADDRESS_WIDTH=30, |
LGICACHE=8; |
`ifdef OPT_MULTIPLY |
parameter IMPLEMENT_MPY = `OPT_MULTIPLY; |
`else |
157,7 → 158,9
`else |
parameter EARLY_BRANCHING = 0; |
`endif |
parameter AW=ADDRESS_WIDTH; |
parameter WITH_LOCAL_BUS = 1; |
localparam AW=ADDRESS_WIDTH; |
localparam [(AW-1):0] RESET_BUS_ADDRESS = RESET_ADDRESS[(AW+1):2]; |
input i_clk, i_rst, i_interrupt; |
// Debug interface -- inputs |
input i_halt, i_clear_pf_cache; |
165,7 → 168,7
input i_dbg_we; |
input [31:0] i_dbg_data; |
// Debug interface -- outputs |
output reg o_dbg_stall; |
output wire o_dbg_stall; |
output reg [31:0] o_dbg_reg; |
output reg [3:0] o_dbg_cc; |
output wire o_break; |
174,6 → 177,7
output wire o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we; |
output wire [(AW-1):0] o_wb_addr; |
output wire [31:0] o_wb_data; |
output wire [3:0] o_wb_sel; |
// Wishbone interface -- inputs |
input i_wb_ack, i_wb_stall; |
input [31:0] i_wb_data; |
198,19 → 202,22
// that logic. |
// |
(* ram_style = "distributed" *) |
`ifdef OPT_NO_USERMODE |
reg [31:0] regset [0:15]; |
`else |
reg [31:0] regset [0:31]; |
`endif |
|
// Condition codes |
// (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z |
reg [3:0] flags, iflags; |
wire [13:0] w_uflags, w_iflags; |
reg trap, break_en, step, gie, sleep; |
`ifdef OPT_ILLEGAL_INSTRUCTION |
reg ill_err_u, ill_err_i; |
`else |
wire ill_err_u, ill_err_i; |
`endif |
reg ibus_err_flag, ubus_err_flag; |
wire [14:0] w_uflags, w_iflags; |
reg break_en, step, sleep, r_halted; |
wire break_pending, trap, gie, ubreak; |
wire w_clear_icache, ill_err_u; |
reg ill_err_i; |
reg ibus_err_flag; |
wire ubus_err_flag; |
wire idiv_err_flag, udiv_err_flag; |
wire ifpu_err_flag, ufpu_err_flag; |
wire ihalt_phase, uhalt_phase; |
223,18 → 230,18
// PIPELINE STAGE #1 :: Prefetch |
// Variable declarations |
// |
reg [(AW-1):0] pf_pc; |
reg [(AW+1):0] pf_pc; |
reg new_pc; |
wire clear_pipeline; |
assign clear_pipeline = new_pc || i_clear_pf_cache; |
assign clear_pipeline = new_pc; |
|
wire dcd_stalled; |
wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err; |
wire [(AW-1):0] pf_addr; |
wire [31:0] pf_data; |
wire [31:0] instruction; |
wire [(AW-1):0] instruction_pc; |
wire pf_valid, instruction_gie, pf_illegal; |
wire [31:0] pf_instruction; |
wire [(AW-1):0] pf_instruction_pc; |
wire pf_valid, pf_gie, pf_illegal; |
|
// |
// |
242,29 → 249,33
// Variable declarations |
// |
// |
reg opvalid, opvalid_mem, opvalid_alu; |
reg opvalid_div, opvalid_fpu; |
reg op_valid /* verilator public_flat */, |
op_valid_mem, op_valid_alu; |
reg op_valid_div, op_valid_fpu; |
wire op_stall, dcd_ce, dcd_phase; |
wire [3:0] dcdOp; |
wire [4:0] dcdA, dcdB, dcdR; |
wire dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc; |
wire [3:0] dcdF; |
wire dcdR_wr, dcdA_rd, dcdB_rd, |
dcdALU, dcdM, dcdDV, dcdFP, |
dcdF_wr, dcd_gie, dcd_break, dcd_lock, |
wire [3:0] dcd_opn; |
wire [4:0] dcd_A, dcd_B, dcd_R; |
wire dcd_Acc, dcd_Bcc, dcd_Apc, dcd_Bpc, dcd_Rcc, dcd_Rpc; |
wire [3:0] dcd_F; |
wire dcd_wR, dcd_rA, dcd_rB, |
dcd_ALU, dcd_M, dcd_DIV, dcd_FP, |
dcd_wF, dcd_gie, dcd_break, dcd_lock, |
dcd_pipe, dcd_ljmp; |
reg r_dcdvalid; |
wire dcdvalid; |
wire [(AW-1):0] dcd_pc; |
wire [31:0] dcdI; |
wire dcd_zI; // true if dcdI == 0 |
wire dcdA_stall, dcdB_stall, dcdF_stall; |
reg r_dcd_valid; |
wire dcd_valid; |
wire [AW:0] dcd_pc /* verilator public_flat */; |
wire [31:0] dcd_I; |
wire dcd_zI; // true if dcd_I == 0 |
wire dcd_A_stall, dcd_B_stall, dcd_F_stall; |
|
wire dcd_illegal; |
wire dcd_early_branch; |
wire [(AW-1):0] dcd_branch_pc; |
|
wire dcd_sim; |
wire [22:0] dcd_sim_immv; |
|
|
// |
// |
// PIPELINE STAGE #3 :: Read Operands |
274,29 → 285,33
// |
// Now, let's read our operands |
reg [4:0] alu_reg; |
reg [3:0] opn; |
reg [4:0] opR; |
reg [31:0] r_opA, r_opB; |
wire [3:0] op_opn; |
wire [4:0] op_R; |
reg [31:0] r_op_Av, r_op_Bv; |
reg [(AW-1):0] op_pc; |
wire [31:0] w_opA, w_opB; |
wire [31:0] opA_nowait, opB_nowait, opA, opB; |
reg opR_wr, opR_cc, opF_wr, op_gie; |
wire [13:0] opFl; |
reg [5:0] r_opF; |
wire [7:0] opF; |
wire op_ce, op_phase, op_pipe; |
wire [31:0] w_op_Av, w_op_Bv; |
wire [31:0] op_A_nowait, op_B_nowait, op_Av, op_Bv; |
reg op_wR, op_wF; |
wire op_gie, op_Rcc; |
wire [14:0] op_Fl; |
reg [6:0] r_op_F; |
wire [7:0] op_F; |
wire op_ce, op_phase, op_pipe, op_change_data_ce; |
// Some pipeline control wires |
`ifdef OPT_PIPELINED |
reg opA_alu, opA_mem; |
reg opB_alu, opB_mem; |
reg op_A_alu, op_A_mem; |
reg op_B_alu, op_B_mem; |
`endif |
`ifdef OPT_ILLEGAL_INSTRUCTION |
reg op_illegal; |
`endif |
reg op_break; |
wire op_break; |
wire op_lock; |
|
`ifdef VERILATOR |
reg op_sim /* verilator public_flat */; |
reg [22:0] op_sim_immv /* verilator public_flat */; |
`endif |
|
|
// |
// |
// PIPELINE STAGE #4 :: ALU / Memory |
303,25 → 318,22
// Variable declarations |
// |
// |
reg [(AW-1):0] alu_pc; |
wire [(AW-1):0] alu_pc; |
reg r_alu_pc_valid, mem_pc_valid; |
wire alu_pc_valid; |
wire alu_phase; |
wire alu_ce, alu_stall; |
wire alu_ce /* verilator public_flat */, alu_stall; |
wire [31:0] alu_result; |
wire [3:0] alu_flags; |
wire alu_valid, alu_busy; |
wire set_cond; |
reg alu_wr, alF_wr, alu_gie; |
wire alu_illegal_op; |
wire alu_illegal; |
reg alu_wR, alu_wF; |
wire alu_gie, alu_illegal; |
|
|
|
wire mem_ce, mem_stalled; |
`ifdef OPT_PIPELINED_BUS_ACCESS |
wire mem_pipe_stalled; |
`endif |
wire mem_valid, mem_ack, mem_stall, mem_err, bus_err, |
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we; |
wire [4:0] mem_wreg; |
329,12 → 341,13
wire mem_busy, mem_rdbusy; |
wire [(AW-1):0] mem_addr; |
wire [31:0] mem_data, mem_result; |
wire [3:0] mem_sel; |
|
wire div_ce, div_error, div_busy, div_valid; |
wire [31:0] div_result; |
wire [3:0] div_flags; |
|
assign div_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_div) |
assign div_ce = (master_ce)&&(~clear_pipeline)&&(op_valid_div) |
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy) |
&&(set_cond); |
|
342,10 → 355,11
wire [31:0] fpu_result; |
wire [3:0] fpu_flags; |
|
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu) |
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(op_valid_fpu) |
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy) |
&&(set_cond); |
|
wire adf_ce_unconditional; |
|
// |
// |
352,11 → 366,13
// PIPELINE STAGE #5 :: Write-back |
// Variable declarations |
// |
wire wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc; |
wire wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc, |
wr_write_scc, wr_write_ucc; |
wire [4:0] wr_reg_id; |
wire [31:0] wr_reg_vl; |
wire [31:0] wr_gpreg_vl, wr_spreg_vl; |
wire w_switch_to_interrupt, w_release_from_interrupt; |
reg [(AW-1):0] upc, ipc; |
reg [(AW+1):0] ipc; |
wire [(AW+1):0] upc; |
|
|
|
363,7 → 379,7
// |
// MASTER: clock enable. |
// |
assign master_ce = (~i_halt)&&(~o_break)&&(~sleep); |
assign master_ce = ((~i_halt)||(alu_phase))&&(~o_break)&&(~sleep); |
|
|
// |
376,13 → 392,13
// |
// PIPELINE STAGE #2 :: Instruction Decode |
// Calculate stall conditions |
assign dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline); |
assign dcd_ce = ((~dcd_valid)||(~dcd_stalled))&&(~clear_pipeline); |
|
`ifdef OPT_PIPELINED |
assign dcd_stalled = (dcdvalid)&&(op_stall); |
assign dcd_stalled = (dcd_valid)&&(op_stall); |
`else |
// If not pipelined, there will be no opvalid_ anything, and the |
// op_stall will be false, dcdX_stall will be false, thus we can simply |
// If not pipelined, there will be no op_valid_ anything, and the |
// op_stall will be false, dcd_X_stall will be false, thus we can simply |
// do a ... |
assign dcd_stalled = 1'b0; |
`endif |
389,9 → 405,17
// |
// PIPELINE STAGE #3 :: Read Operands |
// Calculate stall conditions |
wire op_lock_stall; |
wire prelock_stall; |
`ifdef OPT_PIPELINED |
assign op_stall = (opvalid)&&( // Only stall if we're loaded w/validins |
reg cc_invalid_for_dcd; |
always @(posedge i_clk) |
cc_invalid_for_dcd <= (wr_flags_ce) |
||(wr_reg_ce)&&(wr_reg_id[3:0] == `CPU_CC_REG) |
||(op_valid)&&((op_wF)||((op_wR)&&(op_R[3:0] == `CPU_CC_REG))) |
||((alu_wF)||((alu_wR)&&(alu_reg[3:0] == `CPU_CC_REG))) |
||(mem_busy)||(div_busy)||(fpu_busy); |
|
assign op_stall = (op_valid)&&( // Only stall if we're loaded w/validins |
// Stall if we're stopped, and not allowed to execute |
// an instruction |
// (~master_ce) // Already captured in alu_stall |
404,29 → 428,41
// This also includes whether or not the divide or |
// floating point units are busy. |
(alu_stall) |
||(((op_valid_div)||(op_valid_fpu)) |
&&(!adf_ce_unconditional)) |
// |
// Stall if we are going into memory with an operation |
// that cannot be pipelined, and the memory is |
// already busy |
||(mem_stalled) // &&(opvalid_mem) part of mem_stalled |
||(mem_stalled) // &&(op_valid_mem) part of mem_stalled |
||(op_Rcc) |
) |
||(dcdvalid)&&( |
||(dcd_valid)&&( |
// Stall if we need to wait for an operand A |
// to be ready to read |
(dcdA_stall) |
(dcd_A_stall) |
// Likewise for B, also includes logic |
// regarding immediate offset (register must |
// be in register file if we need to add to |
// an immediate) |
||(dcdB_stall) |
||(dcd_B_stall) |
// Or if we need to wait on flags to work on the |
// CC register |
||(dcdF_stall) |
||(dcd_F_stall) |
); |
assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline); |
assign op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(!op_stall); |
|
|
// BUT ... op_ce is too complex for many of the data operations. So |
// let's make their circuit enable code simpler. In particular, if |
// op_ doesn't need to be preserved, we can change it all we want |
// ... right? The clear_pipeline code, for example, really only needs |
// to determine whether op_valid is true. |
assign op_change_data_ce = (~op_stall); |
`else |
assign op_stall = (opvalid)&&(~master_ce); |
assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~clear_pipeline); |
assign op_stall = (op_valid)&&(~master_ce); |
assign op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(~clear_pipeline); |
assign op_change_data_ce = 1'b1; |
`endif |
|
// |
434,7 → 470,7
// Calculate stall conditions |
// |
// 1. Basic stall is if the previous stage is valid and the next is |
// busy. |
// busy. |
// 2. Also stall if the prior stage is valid and the master clock enable |
// is de-selected |
// 3. Stall if someone on the other end is writing the CC register, |
443,20 → 479,16
// through the ALU. Break instructions are not allowed through |
// the ALU. |
`ifdef OPT_PIPELINED |
assign alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2 |
// Old case #3--this isn't an ALU stall though ... |
||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie) |
&&(wr_write_cc)) // Case 3 |
||((opvalid)&&(op_lock)&&(op_lock_stall)) |
||((opvalid)&&(op_break)) |
assign alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(op_valid_alu)) //Case 1&2 |
||(prelock_stall) |
||((op_valid)&&(op_break)) |
||(wr_reg_ce)&&(wr_write_cc) |
||(div_busy)||(fpu_busy); |
assign alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal)) |
&&(~alu_stall) |
assign alu_ce = (master_ce)&&(op_valid_alu)&&(~alu_stall) |
&&(~clear_pipeline); |
`else |
assign alu_stall = ((~master_ce)&&(opvalid_alu)) |
||((opvalid_alu)&&(op_break)); |
assign alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall)&&(~clear_pipeline); |
assign alu_stall = (op_valid_alu)&&((~master_ce)||(op_break)); |
assign alu_ce = (master_ce)&&(op_valid_alu)&&(~alu_stall)&&(~clear_pipeline); |
`endif |
// |
|
465,7 → 497,7
// alu_pc_valid. |
// |
`ifdef OPT_PIPELINED |
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled) |
assign mem_ce = (master_ce)&&(op_valid_mem)&&(~mem_stalled) |
&&(~clear_pipeline); |
`else |
// If we aren't pipelined, then no one will be changing what's in the |
476,12 → 508,13
// something gets in the pipeline and then (due to interrupt or some |
// such) needs to be voided? Thus we avoid simplification and keep |
// what worked here. |
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled) |
assign mem_ce = (master_ce)&&(op_valid_mem)&&(~mem_stalled) |
&&(~clear_pipeline); |
`endif |
`ifdef OPT_PIPELINED_BUS_ACCESS |
assign mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&( |
assign mem_stalled = (~master_ce)||(alu_busy)||((op_valid_mem)&&( |
(mem_pipe_stalled) |
||(prelock_stall) |
||((~op_pipe)&&(mem_busy)) |
||(div_busy) |
||(fpu_busy) |
493,7 → 526,7
&&((wr_write_pc)||(wr_write_cc))))); |
`else |
`ifdef OPT_PIPELINED |
assign mem_stalled = (mem_busy)||((opvalid_mem)&&( |
assign mem_stalled = (mem_busy)||((op_valid_mem)&&( |
(~master_ce) |
// Stall waiting for flags to be valid |
// Or waiting for a write to the PC register |
501,10 → 534,15
// PC as well |
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc))))); |
`else |
assign mem_stalled = (opvalid_mem)&&(~master_ce); |
assign mem_stalled = (op_valid_mem)&&(~master_ce); |
`endif |
`endif |
|
// ALU, DIV, or FPU CE ... equivalent to the OR of all three of these |
assign adf_ce_unconditional = (master_ce)&&(~clear_pipeline)&&(op_valid) |
&&(~op_valid_mem)&&(~mem_rdbusy) |
&&((~op_valid_alu)||(~alu_stall))&&(~op_break) |
&&(~div_busy)&&(~fpu_busy)&&(~clear_pipeline); |
|
// |
// |
514,108 → 552,94
`ifdef OPT_SINGLE_FETCH |
wire pf_ce; |
|
assign pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_busy)&&(~mem_busy)&&(~alu_pc_valid)&&(~mem_pc_valid); |
assign pf_ce = (~pf_valid)&&(~dcd_valid)&&(~op_valid)&&(~alu_busy)&&(~mem_busy)&&(~alu_pc_valid)&&(~mem_pc_valid); |
prefetch #(ADDRESS_WIDTH) |
pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc, gie, |
instruction, instruction_pc, instruction_gie, |
pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc[(AW+1):2], gie, |
pf_instruction, pf_instruction_pc, pf_gie, |
pf_valid, pf_illegal, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, i_wb_data); |
|
initial r_dcdvalid = 1'b0; |
initial r_dcd_valid = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) |
r_dcdvalid <= 1'b0; |
if (clear_pipeline) |
r_dcd_valid <= 1'b0; |
else if (dcd_ce) |
r_dcdvalid <= (pf_valid); |
r_dcd_valid <= (pf_valid)||(pf_illegal); |
else if (op_ce) |
r_dcdvalid <= 1'b0; |
assign dcdvalid = r_dcdvalid; |
r_dcd_valid <= 1'b0; |
assign dcd_valid = r_dcd_valid; |
|
`else // Pipe fetch |
|
wire pf_stalled; |
assign pf_stalled = (dcd_stalled)||(dcd_phase); |
`ifdef OPT_TRADITIONAL_PFCACHE |
wire [(AW-1):0] pf_request_address; |
assign pf_request_address = ((dcd_early_branch)&&(!clear_pipeline)) |
? dcd_branch_pc:pf_pc[(AW+1):2]; |
pfcache #(LGICACHE, ADDRESS_WIDTH) |
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)), |
i_clear_pf_cache, |
w_clear_icache, |
// dcd_pc, |
~dcd_stalled, |
((dcd_early_branch)&&(~clear_pipeline)) |
? dcd_branch_pc:pf_pc, |
instruction, instruction_pc, pf_valid, |
(!pf_stalled), |
pf_request_address, |
pf_instruction, pf_instruction_pc, pf_valid, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, i_wb_data, |
pf_illegal); |
`else |
pipefetch #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH) |
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)), |
i_clear_pf_cache, ~dcd_stalled, |
(new_pc)?pf_pc:dcd_branch_pc, |
instruction, instruction_pc, pf_valid, |
pipefetch #(RESET_BUS_ADDRESS, LGICACHE, ADDRESS_WIDTH) |
pf(i_clk, i_rst, (new_pc)||(dcd_early_branch), |
w_clear_icache, (!pf_stalled), |
(new_pc)?pf_pc[(AW+1):2]:dcd_branch_pc, |
pf_instruction, pf_instruction_pc, pf_valid, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, i_wb_data, |
//`ifdef OPT_PRECLEAR_BUS |
//((dcd_clear_bus)&&(dcdvalid)) |
//||((op_clear_bus)&&(opvalid)) |
//|| |
//`endif |
(mem_cyc_lcl)||(mem_cyc_gbl), |
pf_illegal); |
`endif |
assign instruction_gie = gie; |
`ifdef OPT_NO_USERMODE |
assign pf_gie = 1'b0; |
`else |
assign pf_gie = gie; |
`endif |
|
initial r_dcdvalid = 1'b0; |
initial r_dcd_valid = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) |
r_dcdvalid <= 1'b0; |
if ((clear_pipeline)||(w_clear_icache)) |
r_dcd_valid <= 1'b0; |
else if (dcd_ce) |
r_dcdvalid <= (pf_valid)&&(~dcd_ljmp)&&((~r_dcdvalid)||(~dcd_early_branch)); |
r_dcd_valid <= ((dcd_phase)||(pf_valid)) |
&&(~dcd_ljmp)&&(~dcd_early_branch); |
else if (op_ce) |
r_dcdvalid <= 1'b0; |
assign dcdvalid = r_dcdvalid; |
r_dcd_valid <= 1'b0; |
assign dcd_valid = r_dcd_valid; |
`endif |
|
`ifdef OPT_NEW_INSTRUCTION_SET |
// If not pipelined, there will be no op_valid_ anything, and the |
idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE, |
IMPLEMENT_FPU) |
instruction_decoder(i_clk, (i_rst)||(clear_pipeline), |
dcd_ce, dcd_stalled, instruction, instruction_gie, |
instruction_pc, pf_valid, pf_illegal, dcd_phase, |
dcd_illegal, dcd_pc, dcd_gie, |
{ dcdR_cc, dcdR_pc, dcdR }, |
{ dcdA_cc, dcdA_pc, dcdA }, |
{ dcdB_cc, dcdB_pc, dcdB }, |
dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp, |
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock, |
dcdR_wr,dcdA_rd, dcdB_rd, |
instruction_decoder(i_clk, (clear_pipeline), |
(~dcd_valid)||(~op_stall), dcd_stalled, pf_instruction, pf_gie, |
pf_instruction_pc, pf_valid, pf_illegal, dcd_phase, |
dcd_illegal, dcd_pc, dcd_gie, |
{ dcd_Rcc, dcd_Rpc, dcd_R }, |
{ dcd_Acc, dcd_Apc, dcd_A }, |
{ dcd_Bcc, dcd_Bpc, dcd_B }, |
dcd_I, dcd_zI, dcd_F, dcd_wF, dcd_opn, |
dcd_ALU, dcd_M, dcd_DIV, dcd_FP, dcd_break, dcd_lock, |
dcd_wR,dcd_rA, dcd_rB, |
dcd_early_branch, |
dcd_branch_pc, dcd_ljmp, |
dcd_pipe); |
`else |
idecode_deprecated |
#(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE, |
IMPLEMENT_FPU) |
instruction_decoder(i_clk, (i_rst)||(clear_pipeline), |
dcd_ce, dcd_stalled, instruction, instruction_gie, |
instruction_pc, pf_valid, pf_illegal, dcd_phase, |
dcd_illegal, dcd_pc, dcd_gie, |
{ dcdR_cc, dcdR_pc, dcdR }, |
{ dcdA_cc, dcdA_pc, dcdA }, |
{ dcdB_cc, dcdB_pc, dcdB }, |
dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp, |
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock, |
dcdR_wr,dcdA_rd, dcdB_rd, |
dcd_early_branch, |
dcd_branch_pc, |
dcd_pipe); |
assign dcd_ljmp = 1'b0; |
`endif |
dcd_pipe, |
dcd_sim, dcd_sim_immv); |
|
`ifdef OPT_PIPELINED_BUS_ACCESS |
reg r_op_pipe; |
|
initial r_op_pipe = 1'b0; |
// To be a pipeable operation, there must be |
// To be a pipeable operation, there must be |
// two valid adjacent instructions |
// Both must be memory instructions |
// Both must be writes, or both must be reads |
625,7 → 649,9
// However ... we need to know this before this clock, hence this is |
// calculated in the instruction decoder. |
always @(posedge i_clk) |
if (op_ce) |
if (clear_pipeline) |
r_op_pipe <= 1'b0; |
else if (op_ce) |
r_op_pipe <= dcd_pipe; |
else if (mem_ce) // Clear us any time an op_ is clocked in |
r_op_pipe <= 1'b0; |
639,31 → 665,20
// PIPELINE STAGE #3 :: Read Operands (Registers) |
// |
// |
assign w_opA = regset[dcdA]; |
assign w_opB = regset[dcdB]; |
`ifdef OPT_NO_USERMODE |
assign w_op_Av = regset[dcd_A[3:0]]; |
assign w_op_Bv = regset[dcd_B[3:0]]; |
`else |
assign w_op_Av = regset[dcd_A]; |
assign w_op_Bv = regset[dcd_B]; |
`endif |
|
wire [8:0] w_cpu_info; |
assign w_cpu_info = { |
`ifdef OPT_ILLEGAL_INSTRUCTION |
1'b1, |
`else |
1'b0, |
`endif |
`ifdef OPT_MULTIPLY |
1'b1, |
`else |
1'b0, |
`endif |
`ifdef OPT_DIVIDE |
1'b1, |
`else |
1'b0, |
`endif |
`ifdef OPT_IMPLEMENT_FPU |
1'b1, |
`else |
1'b0, |
`endif |
(IMPLEMENT_MPY >0)? 1'b1:1'b0, |
(IMPLEMENT_DIVIDE >0)? 1'b1:1'b0, |
(IMPLEMENT_FPU >0)? 1'b1:1'b0, |
`ifdef OPT_PIPELINED |
1'b1, |
`else |
684,7 → 699,7
`else |
1'b0, |
`endif |
`ifdef OPT_VLIW |
`ifdef OPT_CIS |
1'b1 |
`else |
1'b0 |
692,70 → 707,85
}; |
|
wire [31:0] w_pcA_v; |
assign w_pcA_v[(AW+1):0] = { (dcd_A[4] == dcd_gie) |
? { dcd_pc[AW:1], 2'b00 } |
: { upc[(AW+1):2], uhalt_phase, 1'b0 } }; |
generate |
if (AW < 32) |
assign w_pcA_v = {{(32-AW){1'b0}}, (dcdA[4] == dcd_gie)?dcd_pc:upc }; |
else |
assign w_pcA_v = (dcdA[4] == dcd_gie)?dcd_pc:upc; |
if (AW < 30) |
assign w_pcA_v[31:(AW+2)] = 0; |
endgenerate |
|
`ifdef OPT_PIPELINED |
reg [4:0] opA_id, opB_id; |
reg opA_rd, opB_rd; |
reg [4:0] op_Aid, op_Bid; |
reg op_rA, op_rB; |
always @(posedge i_clk) |
if (op_ce) |
begin |
opA_id <= dcdA; |
opB_id <= dcdB; |
opA_rd <= dcdA_rd; |
opB_rd <= dcdB_rd; |
op_Aid <= dcd_A; |
op_Bid <= dcd_B; |
op_rA <= dcd_rA; |
op_rB <= dcd_rB; |
end |
`endif |
|
always @(posedge i_clk) |
if (op_ce) // &&(dcdvalid)) |
`ifdef OPT_PIPELINED |
if (op_ce) |
`endif |
begin |
if ((wr_reg_ce)&&(wr_reg_id == dcdA)) |
r_opA <= wr_reg_vl; |
else if (dcdA_pc) |
r_opA <= w_pcA_v; |
else if (dcdA_cc) |
r_opA <= { w_cpu_info, w_opA[22:14], (dcdA[4])?w_uflags:w_iflags }; |
`ifdef OPT_PIPELINED |
if ((wr_reg_ce)&&(wr_reg_id == dcd_A)) |
r_op_Av <= wr_gpreg_vl; |
else |
r_opA <= w_opA; |
`endif |
if (dcd_Apc) |
r_op_Av <= w_pcA_v; |
else if (dcd_Acc) |
r_op_Av <= { w_cpu_info, w_op_Av[22:16], 1'b0, (dcd_A[4])?w_uflags:w_iflags }; |
else |
r_op_Av <= w_op_Av; |
`ifdef OPT_PIPELINED |
end else |
begin // We were going to pick these up when they became valid, |
// but for some reason we're stuck here as they became |
// valid. Pick them up now anyway |
// if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid))) |
// r_opA <= wr_reg_vl; |
if ((wr_reg_ce)&&(wr_reg_id == opA_id)&&(opA_rd)) |
r_opA <= wr_reg_vl; |
// if (((op_A_alu)&&(alu_wR))||((op_A_mem)&&(mem_valid))) |
// r_op_Av <= wr_gpreg_vl; |
if ((wr_reg_ce)&&(wr_reg_id == op_Aid)&&(op_rA)) |
r_op_Av <= wr_gpreg_vl; |
`endif |
end |
|
wire [31:0] w_opBnI, w_pcB_v; |
wire [31:0] w_op_BnI, w_pcB_v; |
assign w_pcB_v[(AW+1):0] = { (dcd_B[4] == dcd_gie) |
? { dcd_pc[AW:1], 2'b00 } |
: { upc[(AW+1):2], uhalt_phase, 1'b0 } }; |
generate |
if (AW < 32) |
assign w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc }; |
else |
assign w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc; |
if (AW < 30) |
assign w_pcB_v[31:(AW+2)] = 0; |
endgenerate |
|
assign w_opBnI = (~dcdB_rd) ? 32'h00 |
: (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl |
: ((dcdB_pc) ? w_pcB_v |
: ((dcdB_cc) ? { w_cpu_info, w_opB[22:14], // w_opB[31:14], |
(dcdB[4])?w_uflags:w_iflags} |
: w_opB))); |
assign w_op_BnI = (!dcd_rB) ? 32'h00 |
`ifdef OPT_PIPELINED |
: ((wr_reg_ce)&&(wr_reg_id == dcd_B)) ? wr_gpreg_vl |
`endif |
: ((dcd_Bcc) ? { w_cpu_info, w_op_Bv[22:16], // w_op_B[31:14], |
1'b0, (dcd_B[4])?w_uflags:w_iflags} |
: w_op_Bv); |
|
always @(posedge i_clk) |
if (op_ce) // &&(dcdvalid)) |
r_opB <= w_opBnI + dcdI; |
`ifdef OPT_PIPELINED |
else if ((wr_reg_ce)&&(opB_id == wr_reg_id)&&(opB_rd)) |
r_opB <= wr_reg_vl; |
if ((op_ce)&&(dcd_Bpc)&&(dcd_rB)) |
r_op_Bv <= w_pcB_v + { dcd_I[29:0], 2'b00 }; |
else if (op_ce) |
r_op_Bv <= w_op_BnI + dcd_I; |
else if ((wr_reg_ce)&&(op_Bid == wr_reg_id)&&(op_rB)) |
r_op_Bv <= wr_gpreg_vl; |
`else |
if ((dcd_Bpc)&&(dcd_rB)) |
r_op_Bv <= w_pcB_v + { dcd_I[29:0], 2'b00 }; |
else |
r_op_Bv <= w_op_BnI + dcd_I; |
`endif |
|
// The logic here has become more complex than it should be, no thanks |
766,48 → 796,42
// conditions checking those bits. Therefore, Vivado complains that |
// these two bits are redundant. Hence the convoluted expression |
// below, arriving at what we finally want in the (now wire net) |
// opF. |
// op_F. |
always @(posedge i_clk) |
if (op_ce) |
`ifdef OPT_PIPELINED |
if (op_ce) // Cannot do op_change_data_ce here since op_F depends |
// upon being either correct for a valid op, or correct |
// for the last valid op |
`endif |
begin // Set the flag condition codes, bit order is [3:0]=VNCZ |
case(dcdF[2:0]) |
3'h0: r_opF <= 6'h00; // Always |
`ifdef OPT_NEW_INSTRUCTION_SET |
// These were remapped as part of the new instruction |
// set in order to make certain that the low order |
// two bits contained the most commonly used |
// conditions: Always, LT, Z, and NZ. |
3'h1: r_opF <= 6'h24; // LT |
3'h2: r_opF <= 6'h11; // Z |
3'h3: r_opF <= 6'h10; // NE |
3'h4: r_opF <= 6'h30; // GT (!N&!Z) |
3'h5: r_opF <= 6'h20; // GE (!N) |
`else |
3'h1: r_opF <= 6'h11; // Z |
3'h2: r_opF <= 6'h10; // NE |
3'h3: r_opF <= 6'h20; // GE (!N) |
3'h4: r_opF <= 6'h30; // GT (!N&!Z) |
3'h5: r_opF <= 6'h24; // LT |
`endif |
3'h6: r_opF <= 6'h02; // C |
3'h7: r_opF <= 6'h08; // V |
case(dcd_F[2:0]) |
3'h0: r_op_F <= 7'h00; // Always |
3'h1: r_op_F <= 7'h11; // Z |
3'h2: r_op_F <= 7'h44; // LT |
3'h3: r_op_F <= 7'h22; // C |
3'h4: r_op_F <= 7'h08; // V |
3'h5: r_op_F <= 7'h10; // NE |
3'h6: r_op_F <= 7'h40; // GE (!N) |
3'h7: r_op_F <= 7'h20; // NC |
endcase |
end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value } |
assign opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] }; |
assign op_F = { r_op_F[3], r_op_F[6:0] }; |
|
wire w_opvalid; |
assign w_opvalid = (~clear_pipeline)&&(dcdvalid)&&(~dcd_ljmp); |
initial opvalid = 1'b0; |
initial opvalid_alu = 1'b0; |
initial opvalid_mem = 1'b0; |
initial opvalid_div = 1'b0; |
initial opvalid_fpu = 1'b0; |
wire w_op_valid; |
assign w_op_valid = (~clear_pipeline)&&(dcd_valid)&&(~dcd_ljmp)&&(!dcd_early_branch); |
initial op_valid = 1'b0; |
initial op_valid_alu = 1'b0; |
initial op_valid_mem = 1'b0; |
initial op_valid_div = 1'b0; |
initial op_valid_fpu = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
if (clear_pipeline) |
begin |
opvalid <= 1'b0; |
opvalid_alu <= 1'b0; |
opvalid_mem <= 1'b0; |
op_valid <= 1'b0; |
op_valid_alu <= 1'b0; |
op_valid_mem <= 1'b0; |
op_valid_div <= 1'b0; |
op_valid_fpu <= 1'b0; |
end else if (op_ce) |
begin |
// Do we have a valid instruction? |
818,25 → 842,19
// Hence, the test on dcd_stalled here. If we must |
// wait until our operands are valid, then we aren't |
// valid yet until then. |
opvalid<= w_opvalid; |
`ifdef OPT_ILLEGAL_INSTRUCTION |
opvalid_alu <= ((dcdALU)||(dcd_illegal))&&(w_opvalid); |
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid); |
opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid); |
opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid); |
`else |
opvalid_alu <= (dcdALU)&&(w_opvalid); |
opvalid_mem <= (dcdM)&&(w_opvalid); |
opvalid_div <= (dcdDV)&&(w_opvalid); |
opvalid_fpu <= (dcdFP)&&(w_opvalid); |
`endif |
end else if ((clear_pipeline)||(alu_ce)||(mem_ce)||(div_ce)||(fpu_ce)) |
op_valid<= (w_op_valid)||(dcd_illegal)&&(dcd_valid)||(dcd_early_branch); |
op_valid_alu <= (w_op_valid)&&((dcd_ALU)||(dcd_illegal) |
||(dcd_early_branch)); |
op_valid_mem <= (dcd_M)&&(~dcd_illegal)&&(w_op_valid); |
op_valid_div <= (dcd_DIV)&&(~dcd_illegal)&&(w_op_valid); |
op_valid_fpu <= (dcd_FP)&&(~dcd_illegal)&&(w_op_valid); |
end else if ((adf_ce_unconditional)||(mem_ce)) |
begin |
opvalid <= 1'b0; |
opvalid_alu <= 1'b0; |
opvalid_mem <= 1'b0; |
opvalid_div <= 1'b0; |
opvalid_fpu <= 1'b0; |
op_valid <= 1'b0; |
op_valid_alu <= 1'b0; |
op_valid_mem <= 1'b0; |
op_valid_div <= 1'b0; |
op_valid_fpu <= 1'b0; |
end |
|
// Here's part of our debug interface. When we recognize a break |
847,45 → 865,41
// condition, replace the break instruction with what it is supposed |
// to be, step through it, and then replace it back. In this fashion, |
// a debugger can step through code. |
// assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001); |
initial op_break = 1'b0; |
// assign w_op_break = (dcd_break)&&(r_dcd_I[15:0] == 16'h0001); |
`ifdef OPT_PIPELINED |
reg r_op_break; |
|
initial r_op_break = 1'b0; |
always @(posedge i_clk) |
if (i_rst) op_break <= 1'b0; |
else if (op_ce) op_break <= (dcd_break); |
else if ((clear_pipeline)||(~opvalid)) |
op_break <= 1'b0; |
if ((i_rst)||(clear_pipeline)) r_op_break <= 1'b0; |
else if (op_ce) |
r_op_break <= (dcd_break); |
else if (!op_valid) |
r_op_break <= 1'b0; |
assign op_break = r_op_break; |
`else |
assign op_break = dcd_break; |
`endif |
|
`ifdef OPT_PIPELINED |
generate |
if (IMPLEMENT_LOCK != 0) |
begin |
reg r_op_lock, r_op_lock_stall; |
reg r_op_lock; |
|
initial r_op_lock_stall = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_op_lock_stall <= 1'b0; |
else |
r_op_lock_stall <= (~opvalid)||(~op_lock) |
||(~dcdvalid)||(~pf_valid); |
|
assign op_lock_stall = r_op_lock_stall; |
|
initial r_op_lock = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
if (clear_pipeline) |
r_op_lock <= 1'b0; |
else if (op_ce) |
r_op_lock <= (dcd_lock)&&(~clear_pipeline); |
r_op_lock <= (dcd_valid)&&(dcd_lock)&&(~clear_pipeline); |
assign op_lock = r_op_lock; |
|
end else begin |
assign op_lock_stall = 1'b0; |
assign op_lock = 1'b0; |
end endgenerate |
|
`else |
assign op_lock_stall = 1'b0; |
assign op_lock = 1'b0; |
`endif |
|
892,52 → 906,106
`ifdef OPT_ILLEGAL_INSTRUCTION |
initial op_illegal = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) |
if (clear_pipeline) |
op_illegal <= 1'b0; |
else if(op_ce) |
`ifdef OPT_PIPELINED |
op_illegal <=(dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0)); |
op_illegal <= (dcd_valid)&&((dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0))); |
`else |
op_illegal <= (dcd_illegal)||(dcd_lock); |
op_illegal <= (dcd_valid)&&((dcd_illegal)||(dcd_lock)); |
`endif |
else if(alu_ce) |
op_illegal <= 1'b0; |
`endif |
|
// No generate on EARLY_BRANCHING here, since if EARLY_BRANCHING is not |
// set, dcd_early_branch will simply be a wire connected to zero and |
// this logic should just optimize. |
`ifdef OPT_PIPELINED |
always @(posedge i_clk) |
if (op_ce) |
begin |
opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr)) |
op_wF <= (dcd_wF)&&((~dcd_Rcc)||(~dcd_wR)) |
&&(~dcd_early_branch)&&(~dcd_illegal); |
opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal); |
op_wR <= (dcd_wR)&&(~dcd_early_branch)&&(~dcd_illegal); |
end |
`else |
always @(posedge i_clk) |
begin |
op_wF <= (dcd_wF)&&((~dcd_Rcc)||(~dcd_wR)) |
&&(~dcd_early_branch)&&(~dcd_illegal); |
op_wR <= (dcd_wR)&&(~dcd_early_branch)&&(~dcd_illegal); |
end |
`endif |
|
`ifdef VERILATOR |
`ifdef OPT_PIPELINED |
always @(posedge i_clk) |
if (op_ce) |
if (op_change_data_ce) |
begin |
opn <= dcdOp; // Which ALU operation? |
// opM <= dcdM; // Is this a memory operation? |
op_sim <= dcd_sim; |
op_sim_immv <= dcd_sim_immv; |
end |
`else |
always @(*) |
begin |
op_sim = dcd_sim; |
op_sim_immv = dcd_sim_immv; |
end |
`endif |
`endif |
|
`ifdef OPT_PIPELINED |
reg [3:0] r_op_opn; |
reg [4:0] r_op_R; |
reg r_op_Rcc; |
reg r_op_gie; |
always @(posedge i_clk) |
if (op_change_data_ce) |
begin |
// Which ALU operation? Early branches are |
// unimplemented moves |
r_op_opn <= (dcd_early_branch) ? 4'hf : dcd_opn; |
// opM <= dcd_M; // Is this a memory operation? |
// What register will these results be written into? |
opR <= dcdR; |
opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie); |
r_op_R <= dcd_R; |
r_op_Rcc <= (dcd_Rcc)&&(dcd_wR)&&(dcd_R[4]==dcd_gie); |
// User level (1), vs supervisor (0)/interrupts disabled |
op_gie <= dcd_gie; |
r_op_gie <= dcd_gie; |
|
|
// |
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc; |
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc[AW:1]; |
end |
assign opFl = (op_gie)?(w_uflags):(w_iflags); |
assign op_opn = r_op_opn; |
assign op_R = r_op_R; |
`ifdef OPT_NO_USERMODE |
assign op_gie = 1'b0; |
`else |
assign op_gie = r_op_gie; |
`endif |
assign op_Rcc = r_op_Rcc; |
`else |
assign op_opn = dcd_opn; |
assign op_R = dcd_R; |
`ifdef OPT_NO_USERMODE |
assign op_gie = 1'b0; |
`else |
assign op_gie = dcd_gie; |
`endif |
// With no pipelining, there is no early branching. We keep it |
always @(posedge i_clk) |
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc[AW:1]; |
`endif |
assign op_Fl = (op_gie)?(w_uflags):(w_iflags); |
|
`ifdef OPT_VLIW |
`ifdef OPT_CIS |
reg r_op_phase; |
initial r_op_phase = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) |
if (clear_pipeline) |
r_op_phase <= 1'b0; |
else if (op_ce) |
r_op_phase <= dcd_phase; |
else if (op_change_data_ce) |
r_op_phase <= (dcd_phase)&&((!dcd_wR)||(!dcd_Rpc)); |
assign op_phase = r_op_phase; |
`else |
assign op_phase = 1'b0; |
956,10 → 1024,10
// define this flag to something other than just plain zero, then |
// the stalls will already be in place. |
`ifdef OPT_PIPELINED |
assign opA = ((wr_reg_ce)&&(wr_reg_id == opA_id)) // &&(opA_rd)) |
? wr_reg_vl : r_opA; |
assign op_Av = ((wr_reg_ce)&&(wr_reg_id == op_Aid)) // &&(op_rA)) |
? wr_gpreg_vl : r_op_Av; |
`else |
assign opA = r_opA; |
assign op_Av = r_op_Av; |
`endif |
|
`ifdef OPT_PIPELINED |
969,20 → 1037,21
// The operation might set flags, and we wish to read the |
// CC register |
// OR ... (No other conditions) |
assign dcdA_stall = (dcdA_rd) // &&(dcdvalid) is checked for elsewhere |
&&((opvalid)||(mem_rdbusy) |
assign dcd_A_stall = (dcd_rA) // &&(dcd_valid) is checked for elsewhere |
&&((op_valid)||(mem_rdbusy) |
||(div_busy)||(fpu_busy)) |
&&((opF_wr)&&(dcdA_cc)); |
&&(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Acc)) |
||((dcd_rA)&&(dcd_Acc)&&(cc_invalid_for_dcd)); |
`else |
// There are no pipeline hazards, if we aren't pipelined |
assign dcdA_stall = 1'b0; |
assign dcd_A_stall = 1'b0; |
`endif |
|
`ifdef OPT_PIPELINED |
assign opB = ((wr_reg_ce)&&(wr_reg_id == opB_id)&&(opB_rd)) |
? wr_reg_vl: r_opB; |
assign op_Bv = ((wr_reg_ce)&&(wr_reg_id == op_Bid)&&(op_rB)) |
? wr_gpreg_vl: r_op_Bv; |
`else |
assign opB = r_opB; |
assign op_Bv = r_op_Bv; |
`endif |
|
`ifdef OPT_PIPELINED |
993,12 → 1062,12
// CC register |
// OR the operation might set register B, and we still need |
// a clock to add the offset to it |
assign dcdB_stall = (dcdB_rd) // &&(dcdvalid) is checked for elsewhere |
assign dcd_B_stall = (dcd_rB) // &&(dcd_valid) is checked for elsewhere |
// If the op stage isn't valid, yet something |
// is running, then it must have been valid. |
// We'll use the last values from that stage |
// (opR_wr, opF_wr, opR) in our logic below. |
&&((opvalid)||(mem_rdbusy) |
// (op_wR, op_wF, op_R) in our logic below. |
&&((op_valid)||(mem_rdbusy) |
||(div_busy)||(fpu_busy)||(alu_busy)) |
&&( |
// Okay, what happens if the result register |
1005,13 → 1074,13
// from instruction 1 becomes the input for |
// instruction two, *and* there's an immediate |
// offset in instruction two? In that case, we |
// need an extra clock between the two |
// instructions to calculate the base plus |
// need an extra clock between the two |
// instructions to calculate the base plus |
// offset. |
// |
// What if instruction 1 (or before) is in a |
// memory pipeline? We may no longer know what |
// the register was! We will then need to |
// the register was! We will then need to |
// blindly wait. We'll temper this only waiting |
// if we're not piping this new instruction. |
// If we were piping, the pipe logic in the |
1019,27 → 1088,28
// is clear, so we're okay then. |
// |
((~dcd_zI)&&( |
((opR == dcdB)&&(opR_wr)) |
((op_R == dcd_B)&&(op_wR)) |
||((mem_rdbusy)&&(~dcd_pipe)) |
)) |
// Stall following any instruction that will |
// set the flags, if we're going to need the |
// flags (CC) register for opB. |
||((opF_wr)&&(dcdB_cc)) |
// flags (CC) register for op_B. |
||(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Bcc)) |
// Stall on any ongoing memory operation that |
// will write to opB -- captured above |
// ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI)) |
); |
assign dcdF_stall = ((~dcdF[3]) |
||((dcdA_rd)&&(dcdA_cc)) |
||((dcdB_rd)&&(dcdB_cc))) |
&&(opvalid)&&(opR_cc); |
// &&(dcdvalid) is checked for elsewhere |
// will write to op_B -- captured above |
// ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcd_B)&&(~dcd_zI)) |
) |
||((dcd_rB)&&(dcd_Bcc)&&(cc_invalid_for_dcd)); |
assign dcd_F_stall = ((~dcd_F[3]) |
||((dcd_rA)&&(dcd_Acc)) |
||((dcd_rB)&&(dcd_Bcc))) |
&&(op_valid)&&(op_Rcc); |
// &&(dcd_valid) is checked for elsewhere |
`else |
// No stalls without pipelining, 'cause how can you have a pipeline |
// hazard without the pipeline? |
assign dcdB_stall = 1'b0; |
assign dcdF_stall = 1'b0; |
assign dcd_B_stall = 1'b0; |
assign dcd_F_stall = 1'b0; |
`endif |
// |
// |
1046,26 → 1116,18
// PIPELINE STAGE #4 :: Apply Instruction |
// |
// |
`ifdef OPT_NEW_INSTRUCTION_SET |
cpuops #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce, |
(opvalid_alu), opn, opA, opB, |
alu_result, alu_flags, alu_valid, alu_illegal_op, |
alu_busy); |
`else |
cpuops_deprecated #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce, |
(opvalid_alu), opn, opA, opB, |
alu_result, alu_flags, alu_valid, alu_illegal_op); |
assign alu_busy = 1'b0; |
`endif |
cpuops #(IMPLEMENT_MPY) doalu(i_clk, (clear_pipeline), |
alu_ce, op_opn, op_Av, op_Bv, |
alu_result, alu_flags, alu_valid, alu_busy); |
|
generate |
if (IMPLEMENT_DIVIDE != 0) |
begin |
div thedivide(i_clk, (i_rst)||(clear_pipeline), div_ce, opn[0], |
opA, opB, div_busy, div_valid, div_error, div_result, |
div thedivide(i_clk, (clear_pipeline), div_ce, op_opn[0], |
op_Av, op_Bv, div_busy, div_valid, div_error, div_result, |
div_flags); |
end else begin |
assign div_error = 1'b1; |
assign div_error = 1'b0; // Can't be high unless div_valid |
assign div_busy = 1'b0; |
assign div_valid = 1'b0; |
assign div_result= 32'h00; |
1077,16 → 1139,16
begin |
// |
// sfpu thefpu(i_clk, i_rst, fpu_ce, |
// opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result, |
// op_Av, op_Bv, fpu_busy, fpu_valid, fpu_err, fpu_result, |
// fpu_flags); |
// |
assign fpu_error = 1'b1; |
assign fpu_error = 1'b0; // Must only be true if fpu_valid |
assign fpu_busy = 1'b0; |
assign fpu_valid = 1'b0; |
assign fpu_result= 32'h00; |
assign fpu_flags = 4'h0; |
end else begin |
assign fpu_error = 1'b1; |
assign fpu_error = 1'b0; |
assign fpu_busy = 1'b0; |
assign fpu_valid = 1'b0; |
assign fpu_result= 32'h00; |
1094,33 → 1156,33
end endgenerate |
|
|
assign set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]); |
initial alF_wr = 1'b0; |
initial alu_wr = 1'b0; |
assign set_cond = ((op_F[7:4]&op_Fl[3:0])==op_F[3:0]); |
initial alu_wF = 1'b0; |
initial alu_wR = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
begin |
alu_wr <= 1'b0; |
alF_wr <= 1'b0; |
alu_wR <= 1'b0; |
alu_wF <= 1'b0; |
end else if (alu_ce) |
begin |
// alu_reg <= opR; |
alu_wr <= (opR_wr)&&(set_cond); |
alF_wr <= (opF_wr)&&(set_cond); |
// alu_reg <= op_R; |
alu_wR <= (op_wR)&&(set_cond); |
alu_wF <= (op_wF)&&(set_cond); |
end else if (~alu_busy) begin |
// These are strobe signals, so clear them if not |
// set for any particular clock |
alu_wr <= (i_halt)&&(i_dbg_we); |
alF_wr <= 1'b0; |
alu_wR <= (i_halt)&&(i_dbg_we); |
alu_wF <= 1'b0; |
end |
|
`ifdef OPT_VLIW |
`ifdef OPT_CIS |
reg r_alu_phase; |
initial r_alu_phase = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_alu_phase <= 1'b0; |
else if ((alu_ce)||(mem_ce)||(div_ce)||(fpu_ce)) |
else if ((adf_ce_unconditional)||(mem_ce)) |
r_alu_phase <= op_phase; |
assign alu_phase = r_alu_phase; |
`else |
1127,11 → 1189,19
assign alu_phase = 1'b0; |
`endif |
|
`ifdef OPT_PIPELINED |
always @(posedge i_clk) |
if ((alu_ce)||(div_ce)||(fpu_ce)) |
alu_reg <= opR; |
if (adf_ce_unconditional) |
alu_reg <= op_R; |
else if ((i_halt)&&(i_dbg_we)) |
alu_reg <= i_dbg_reg; |
`else |
always @(posedge i_clk) |
if ((i_halt)&&(i_dbg_we)) |
alu_reg <= i_dbg_reg; |
else |
alu_reg <= op_R; |
`endif |
|
// |
// DEBUG Register write access starts here |
1139,39 → 1209,58
reg dbgv; |
initial dbgv = 1'b0; |
always @(posedge i_clk) |
dbgv <= (~i_rst)&&(~alu_ce)&&((i_halt)&&(i_dbg_we)); |
dbgv <= (~i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted); |
reg [31:0] dbg_val; |
always @(posedge i_clk) |
dbg_val <= i_dbg_data; |
`ifdef OPT_NO_USERMODE |
assign alu_gie = 1'b0; |
`else |
`ifdef OPT_PIPELINED |
reg r_alu_gie; |
|
always @(posedge i_clk) |
if ((alu_ce)||(mem_ce)) |
alu_gie <= op_gie; |
if ((adf_ce_unconditional)||(mem_ce)) |
r_alu_gie <= op_gie; |
assign alu_gie = r_alu_gie; |
`else |
assign alu_gie = op_gie; |
`endif |
`endif |
|
`ifdef OPT_PIPELINED |
reg [(AW-1):0] r_alu_pc; |
always @(posedge i_clk) |
if ((alu_ce)||((master_ce)&&(opvalid_mem)&&(~clear_pipeline) |
if ((adf_ce_unconditional) |
||((master_ce)&&(op_valid_mem)&&(~clear_pipeline) |
&&(~mem_stalled))) |
alu_pc <= op_pc; |
r_alu_pc <= op_pc; |
assign alu_pc = r_alu_pc; |
`else |
assign alu_pc = op_pc; |
`endif |
|
`ifdef OPT_ILLEGAL_INSTRUCTION |
reg r_alu_illegal; |
initial r_alu_illegal = 0; |
always @(posedge i_clk) |
if (clear_pipeline) |
r_alu_illegal <= 1'b0; |
else if ((alu_ce)||(mem_ce)) |
else if (alu_ce) |
r_alu_illegal <= op_illegal; |
assign alu_illegal = (alu_illegal_op)||(r_alu_illegal); |
`endif |
else |
r_alu_illegal <= 1'b0; |
assign alu_illegal = (r_alu_illegal); |
|
initial r_alu_pc_valid = 1'b0; |
initial mem_pc_valid = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
if (clear_pipeline) |
r_alu_pc_valid <= 1'b0; |
else if (alu_ce) // Includes && (~alu_clear_pipeline) |
else if ((adf_ce_unconditional)&&(!op_phase)) //Includes&&(~alu_clear_pipeline) |
r_alu_pc_valid <= 1'b1; |
else if ((~alu_busy)||(clear_pipeline)) |
else if (((~alu_busy)&&(~div_busy)&&(~fpu_busy))||(clear_pipeline)) |
r_alu_pc_valid <= 1'b0; |
assign alu_pc_valid = (r_alu_pc_valid)&&(~alu_busy); |
assign alu_pc_valid = (r_alu_pc_valid)&&((~alu_busy)&&(~div_busy)&&(~fpu_busy)); |
always @(posedge i_clk) |
if (i_rst) |
mem_pc_valid <= 1'b0; |
1183,17 → 1272,43
generate |
if (IMPLEMENT_LOCK != 0) |
begin |
reg r_prelock_stall; |
|
initial r_prelock_stall = 1'b0; |
always @(posedge i_clk) |
if (clear_pipeline) |
r_prelock_stall <= 1'b0; |
else if ((op_valid)&&(op_lock)&&(op_ce)) |
r_prelock_stall <= 1'b1; |
else if ((op_valid)&&(dcd_valid)&&(pf_valid)) |
r_prelock_stall <= 1'b0; |
|
assign prelock_stall = r_prelock_stall; |
|
reg r_prelock_primed; |
always @(posedge i_clk) |
if (clear_pipeline) |
r_prelock_primed <= 1'b0; |
else if (r_prelock_stall) |
r_prelock_primed <= 1'b1; |
else if ((adf_ce_unconditional)||(mem_ce)) |
r_prelock_primed <= 1'b0; |
|
reg [1:0] r_bus_lock; |
initial r_bus_lock = 2'b00; |
always @(posedge i_clk) |
if (i_rst) |
if (clear_pipeline) |
r_bus_lock <= 2'b00; |
else if ((op_ce)&&(op_lock)) |
r_bus_lock <= 2'b11; |
else if ((|r_bus_lock)&&((~opvalid_mem)||(~op_ce))) |
r_bus_lock <= r_bus_lock + 2'b11; |
else if ((op_valid)&&((adf_ce_unconditional)||(mem_ce))) |
begin |
if (r_prelock_primed) |
r_bus_lock <= 2'b10; |
else if (r_bus_lock != 2'h0) |
r_bus_lock <= r_bus_lock + 2'b11; |
end |
assign bus_lock = |r_bus_lock; |
end else begin |
assign prelock_stall = 1'b0; |
assign bus_lock = 1'b0; |
end endgenerate |
`else |
1202,38 → 1317,49
|
`ifdef OPT_PIPELINED_BUS_ACCESS |
pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock, |
(opn[0]), opB, opA, opR, |
(op_opn[2:0]), op_Bv, op_Av, op_R, |
mem_busy, mem_pipe_stalled, |
mem_valid, bus_err, mem_wreg, mem_result, |
mem_cyc_gbl, mem_cyc_lcl, |
mem_stb_gbl, mem_stb_lcl, |
mem_we, mem_addr, mem_data, |
mem_we, mem_addr, mem_data, mem_sel, |
mem_ack, mem_stall, mem_err, i_wb_data); |
|
|
`else // PIPELINED_BUS_ACCESS |
memops #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock, |
(opn[0]), opB, opA, opR, |
memops #(AW,IMPLEMENT_LOCK,WITH_LOCAL_BUS) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock, |
(op_opn[2:0]), op_Bv, op_Av, op_R, |
mem_busy, |
mem_valid, bus_err, mem_wreg, mem_result, |
mem_cyc_gbl, mem_cyc_lcl, |
mem_stb_gbl, mem_stb_lcl, |
mem_we, mem_addr, mem_data, |
mem_we, mem_addr, mem_data, mem_sel, |
mem_ack, mem_stall, mem_err, i_wb_data); |
assign mem_pipe_stalled = 1'b0; |
`endif // PIPELINED_BUS_ACCESS |
assign mem_rdbusy = ((mem_busy)&&(~mem_we)); |
|
// Either the prefetch or the instruction gets the memory bus, but |
// Either the prefetch or the instruction gets the memory bus, but |
// never both. |
wbdblpriarb #(32,AW) pformem(i_clk, i_rst, |
// Memory access to the arbiter, priority position |
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, |
mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err, |
mem_we, mem_addr, mem_data, mem_sel, |
mem_ack, mem_stall, mem_err, |
// Prefetch access to the arbiter |
pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data, |
// |
// At a first glance, we might want something like: |
// |
// pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data, 4'hf, |
// |
// However, we know that the prefetch will not generate any |
// writes. Therefore, the write specific lines (mem_data and |
// mem_sel) can be shared with the memory in order to ease |
// timing and LUT usage. |
pf_cyc,1'b0,pf_stb, 1'b0, pf_we, pf_addr, mem_data, mem_sel, |
pf_ack, pf_stall, pf_err, |
// Common wires, in and out, of the arbiter |
o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, |
o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
i_wb_ack, i_wb_stall, i_wb_err); |
|
|
1260,45 → 1386,57
// When shall we write back? On one of two conditions |
// Note that the flags needed to be checked before issuing the |
// bus instruction, so they don't need to be checked here. |
// Further, alu_wr includes (set_cond), so we don't need to |
// Further, alu_wR includes (set_cond), so we don't need to |
// check for that here either. |
`ifdef OPT_ILLEGAL_INSTRUCTION |
assign wr_reg_ce = (dbgv)||(~alu_illegal)&& |
(((alu_wr)&&(~clear_pipeline) |
&&((alu_valid)||(div_valid)||(fpu_valid))) |
||(mem_valid)); |
`else |
assign wr_reg_ce = (dbgv)||((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid); |
`endif |
assign wr_reg_ce = (dbgv)||(mem_valid) |
||((~clear_pipeline)&&(~alu_illegal) |
&&(((alu_wR)&&(alu_valid)) |
||(div_valid)||(fpu_valid))); |
// Which register shall be written? |
// COULD SIMPLIFY THIS: by adding three bits to these registers, |
// One or PC, one for CC, and one for GIE match |
// Note that the alu_reg is the register to write on a divide or |
// FPU operation. |
assign wr_reg_id = (alu_wr)?alu_reg:mem_wreg; |
`ifdef OPT_NO_USERMODE |
assign wr_reg_id[3:0] = (alu_wR|div_valid|fpu_valid) |
? alu_reg[3:0]:mem_wreg[3:0]; |
assign wr_reg_id[4] = 1'b0; |
`else |
assign wr_reg_id = (alu_wR|div_valid|fpu_valid)?alu_reg:mem_wreg; |
`endif |
|
// Are we writing to the CC register? |
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG); |
assign wr_write_scc = (wr_reg_id[4:0] == {1'b0, `CPU_CC_REG}); |
assign wr_write_ucc = (wr_reg_id[4:0] == {1'b1, `CPU_CC_REG}); |
// Are we writing to the PC? |
assign wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG); |
|
// What value to write? |
assign wr_reg_vl = ((mem_valid) ? mem_result |
assign wr_gpreg_vl = ((mem_valid) ? mem_result |
:((div_valid|fpu_valid)) |
? ((div_valid) ? div_result:fpu_result) |
:((dbgv) ? dbg_val : alu_result)); |
assign wr_spreg_vl = ((mem_valid) ? mem_result |
:((dbgv) ? dbg_val : alu_result)); |
always @(posedge i_clk) |
if (wr_reg_ce) |
regset[wr_reg_id] <= wr_reg_vl; |
`ifdef OPT_NO_USERMODE |
regset[wr_reg_id[3:0]] <= wr_gpreg_vl; |
`else |
regset[wr_reg_id] <= wr_gpreg_vl; |
`endif |
|
// |
// Write back to the condition codes/flags register ... |
// When shall we write to our flags register? alF_wr already |
// When shall we write to our flags register? alu_wF already |
// includes the set condition ... |
assign wr_flags_ce = ((alF_wr)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal); |
assign w_uflags = { uhalt_phase, ufpu_err_flag, |
assign wr_flags_ce = ((alu_wF)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal); |
assign w_uflags = { 1'b0, uhalt_phase, ufpu_err_flag, |
udiv_err_flag, ubus_err_flag, trap, ill_err_u, |
1'b0, step, 1'b1, sleep, |
ubreak, step, 1'b1, sleep, |
((wr_flags_ce)&&(alu_gie))?alu_flags:flags }; |
assign w_iflags = { ihalt_phase, ifpu_err_flag, |
assign w_iflags = { 1'b0, ihalt_phase, ifpu_err_flag, |
idiv_err_flag, ibus_err_flag, trap, ill_err_i, |
break_en, 1'b0, 1'b0, sleep, |
((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags }; |
1307,8 → 1445,8
// What value to write? |
always @(posedge i_clk) |
// If explicitly writing the register itself |
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc)) |
flags <= wr_reg_vl[3:0]; |
if ((wr_reg_ce)&&(wr_write_ucc)) |
flags <= wr_gpreg_vl[3:0]; |
// Otherwise if we're setting the flags from an ALU operation |
else if ((wr_flags_ce)&&(alu_gie)) |
flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags |
1315,8 → 1453,8
: alu_flags); |
|
always @(posedge i_clk) |
if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc)) |
iflags <= wr_reg_vl[3:0]; |
if ((wr_reg_ce)&&(wr_write_scc)) |
iflags <= wr_gpreg_vl[3:0]; |
else if ((wr_flags_ce)&&(~alu_gie)) |
iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags |
: alu_flags); |
1327,12 → 1465,12
// |
// The goal, upon encountering a break is that the CPU should stop and |
// not execute the break instruction, choosing instead to enter into |
// either interrupt mode or halt first. |
// either interrupt mode or halt first. |
// if ((break_en) AND (break_instruction)) // user mode or not |
// HALT CPU |
// else if (break_instruction) // only in user mode |
// set an interrupt flag, go to supervisor mode |
// allow supervisor to step the CPU. |
// set an interrupt flag, set the user break bit, |
// go to supervisor mode, allow supervisor to step the CPU. |
// Upon a CPU halt, any break condition will be reset. The |
// external debugger will then need to deal with whatever |
// condition has taken place. |
1340,34 → 1478,62
always @(posedge i_clk) |
if ((i_rst)||(i_halt)) |
break_en <= 1'b0; |
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc)) |
break_en <= wr_reg_vl[`CPU_BREAK_BIT]; |
`ifdef OPT_ILLEGAL_INSTRUCTION |
assign o_break = ((break_en)||(~op_gie))&&(op_break) |
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy) |
&&(~div_busy)&&(~fpu_busy) |
&&(~clear_pipeline) |
||((~alu_gie)&&(bus_err)) |
||((~alu_gie)&&(div_valid)&&(div_error)) |
||((~alu_gie)&&(fpu_valid)&&(fpu_error)) |
||((~alu_gie)&&(alu_pc_valid)&&(alu_illegal)); |
else if ((wr_reg_ce)&&(wr_write_scc)) |
break_en <= wr_spreg_vl[`CPU_BREAK_BIT]; |
|
`ifdef OPT_PIPELINED |
reg r_break_pending; |
|
initial r_break_pending = 1'b0; |
always @(posedge i_clk) |
if ((clear_pipeline)||(~op_valid)) |
r_break_pending <= 1'b0; |
else if (op_break) |
r_break_pending <= (~alu_busy)&&(~div_busy)&&(~fpu_busy)&&(~mem_busy)&&(!wr_reg_ce); |
else |
r_break_pending <= 1'b0; |
assign break_pending = r_break_pending; |
`else |
assign o_break = (((break_en)||(~op_gie))&&(op_break) |
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy) |
&&(~clear_pipeline)) |
||((~alu_gie)&&(bus_err)) |
||((~alu_gie)&&(div_valid)&&(div_error)) |
||((~alu_gie)&&(fpu_valid)&&(fpu_error)); |
assign break_pending = op_break; |
`endif |
|
|
assign o_break = ((break_en)||(~op_gie))&&(break_pending) |
&&(~clear_pipeline) |
||((~alu_gie)&&(bus_err)) |
||((~alu_gie)&&(div_error)) |
||((~alu_gie)&&(fpu_error)) |
||((~alu_gie)&&(alu_illegal)&&(!clear_pipeline)); |
|
// The sleep register. Setting the sleep register causes the CPU to |
// sleep until the next interrupt. Setting the sleep register within |
// interrupt mode causes the processor to halt until a reset. This is |
// a panic/fault halt. The trick is that you cannot be allowed to |
// set the sleep bit and switch to supervisor mode in the same |
// set the sleep bit and switch to supervisor mode in the same |
// instruction: users are not allowed to halt the CPU. |
initial sleep = 1'b0; |
`ifdef OPT_NO_USERMODE |
reg r_sleep_is_halt; |
initial r_sleep_is_halt = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_sleep_is_halt <= 1'b0; |
else if ((wr_reg_ce)&&(wr_write_cc) |
&&(wr_spreg_vl[`CPU_SLEEP_BIT]) |
&&(~wr_spreg_vl[`CPU_GIE_BIT])) |
r_sleep_is_halt <= 1'b1; |
|
// Trying to switch to user mode, either via a WAIT or an RTU |
// instruction will cause the CPU to sleep until an interrupt, in |
// the NO-USERMODE build. |
always @(posedge i_clk) |
if ((i_rst)||((i_interrupt)&&(!r_sleep_is_halt))) |
sleep <= 1'b0; |
else if ((wr_reg_ce)&&(wr_write_cc) |
&&(wr_spreg_vl[`CPU_GIE_BIT])) |
sleep <= 1'b1; |
`else |
always @(posedge i_clk) |
if ((i_rst)||(w_switch_to_interrupt)) |
sleep <= 1'b0; |
else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie)) |
1376,27 → 1542,30
// Well ... not quite. Switching to user mode and |
// sleep mode shouold only be possible if the interrupt |
// flag isn't set. |
// Thus: if (i_interrupt)&&(wr_reg_vl[GIE]) |
// Thus: if (i_interrupt)&&(wr_spreg_vl[GIE]) |
// don't set the sleep bit |
// otherwise however it would o.w. be set |
sleep <= (wr_reg_vl[`CPU_SLEEP_BIT]) |
&&((~i_interrupt)||(~wr_reg_vl[`CPU_GIE_BIT])); |
else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT])) |
sleep <= (wr_spreg_vl[`CPU_SLEEP_BIT]) |
&&((~i_interrupt)||(~wr_spreg_vl[`CPU_GIE_BIT])); |
else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_spreg_vl[`CPU_GIE_BIT])) |
// In user mode, however, you can only set the sleep |
// mode while remaining in user mode. You can't switch |
// to sleep mode *and* supervisor mode at the same |
// time, lest you halt the CPU. |
sleep <= wr_reg_vl[`CPU_SLEEP_BIT]; |
sleep <= wr_spreg_vl[`CPU_SLEEP_BIT]; |
`endif |
|
always @(posedge i_clk) |
if ((i_rst)||(w_switch_to_interrupt)) |
if (i_rst) |
step <= 1'b0; |
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc)) |
step <= wr_reg_vl[`CPU_STEP_BIT]; |
else if (((alu_pc_valid)||(mem_pc_valid))&&(step)&&(gie)) |
step <= 1'b0; |
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_write_ucc)) |
step <= wr_spreg_vl[`CPU_STEP_BIT]; |
|
// The GIE register. Only interrupts can disable the interrupt register |
`ifdef OPT_NO_USERMODE |
assign w_switch_to_interrupt = 1'b0; |
assign w_release_from_interrupt = 1'b0; |
`else |
assign w_switch_to_interrupt = (gie)&&( |
// On interrupt (obviously) |
((i_interrupt)&&(~alu_phase)&&(~bus_lock)) |
1404,49 → 1573,78
||(((alu_pc_valid)||(mem_pc_valid))&&(step)&&(~alu_phase)&&(~bus_lock)) |
// If we encounter a break instruction, if the break |
// enable isn't set. |
||((master_ce)&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy) |
&&(op_break)&&(~break_en)) |
`ifdef OPT_ILLEGAL_INSTRUCTION |
||((master_ce)&&(break_pending)&&(~break_en)) |
// On an illegal instruction |
||((alu_pc_valid)&&(alu_illegal)) |
`endif |
||((alu_illegal)&&(!clear_pipeline)) |
// On division by zero. If the divide isn't |
// implemented, div_valid and div_error will be short |
// circuited and that logic will be bypassed |
||((div_valid)&&(div_error)) |
// Same thing on a floating point error. |
||((fpu_valid)&&(fpu_error)) |
// |
||(div_error) |
// Same thing on a floating point error. Note that |
// fpu_error must *never* be set unless fpu_valid is |
// also set as well, else this will fail. |
||(fpu_error) |
// |
||(bus_err) |
// If we write to the CC register |
||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT]) |
||((wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT]) |
&&(wr_reg_id[4])&&(wr_write_cc)) |
); |
assign w_release_from_interrupt = (~gie)&&(~i_interrupt) |
// Then if we write the CC register |
&&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT]) |
&&(~wr_reg_id[4])&&(wr_write_cc)) |
// Then if we write the sCC register |
&&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT]) |
&&(wr_write_scc)) |
); |
`endif |
|
`ifdef OPT_NO_USERMODE |
assign gie = 1'b0; |
`else |
reg r_gie; |
|
initial r_gie = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
gie <= 1'b0; |
r_gie <= 1'b0; |
else if (w_switch_to_interrupt) |
gie <= 1'b0; |
r_gie <= 1'b0; |
else if (w_release_from_interrupt) |
gie <= 1'b1; |
r_gie <= 1'b1; |
assign gie = r_gie; |
`endif |
|
initial trap = 1'b0; |
`ifdef OPT_NO_USERMODE |
assign trap = 1'b0; |
assign ubreak = 1'b0; |
`else |
reg r_trap; |
|
initial r_trap = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
trap <= 1'b0; |
else if (w_release_from_interrupt) |
trap <= 1'b0; |
else if ((alu_gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT]) |
&&(wr_write_cc)) // &&(wr_reg_id[4]) implied |
trap <= 1'b1; |
else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_id[4])) |
trap <= wr_reg_vl[`CPU_TRAP_BIT]; |
if ((i_rst)||(w_release_from_interrupt)) |
r_trap <= 1'b0; |
else if ((alu_gie)&&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT]) |
&&(wr_write_ucc)) // &&(wr_reg_id[4]) implied |
r_trap <= 1'b1; |
else if ((wr_reg_ce)&&(wr_write_ucc)&&(~alu_gie)) |
r_trap <= (r_trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]); |
|
reg r_ubreak; |
|
initial r_ubreak = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(w_release_from_interrupt)) |
r_ubreak <= 1'b0; |
else if ((op_gie)&&(break_pending)&&(w_switch_to_interrupt)) |
r_ubreak <= 1'b1; |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc)) |
r_ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]); |
|
assign trap = r_trap; |
assign ubreak = r_ubreak; |
`endif |
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION |
initial ill_err_i = 1'b0; |
always @(posedge i_clk) |
1453,26 → 1651,31
if (i_rst) |
ill_err_i <= 1'b0; |
// Only the debug interface can clear this bit |
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG}) |
&&(~wr_reg_vl[`CPU_ILL_BIT])) |
ill_err_i <= 1'b0; |
else if ((alu_pc_valid)&&(alu_illegal)&&(~alu_gie)) |
else if ((dbgv)&&(wr_write_scc)) |
ill_err_i <= (ill_err_i)&&(wr_spreg_vl[`CPU_ILL_BIT]); |
else if ((alu_illegal)&&(~alu_gie)&&(!clear_pipeline)) |
ill_err_i <= 1'b1; |
initial ill_err_u = 1'b0; |
|
`ifdef OPT_NO_USERMODE |
assign ill_err_u = 1'b0; |
`else |
reg r_ill_err_u; |
|
initial r_ill_err_u = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
ill_err_u <= 1'b0; |
// The bit is automatically cleared on release from interrupt |
else if (w_release_from_interrupt) |
ill_err_u <= 1'b0; |
// If the supervisor writes to this register, clearing the |
// bit, then clear it |
else if (((~alu_gie)||(dbgv)) |
&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_ILL_BIT]) |
&&(wr_reg_id[4])&&(wr_write_cc)) |
ill_err_u <= 1'b0; |
else if ((alu_pc_valid)&&(alu_illegal)&&(alu_gie)) |
ill_err_u <= 1'b1; |
// or reset |
if ((i_rst)||(w_release_from_interrupt)) |
r_ill_err_u <= 1'b0; |
// If the supervisor (or debugger) writes to this register, |
// clearing the bit, then clear it |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc)) |
r_ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT])); |
else if ((alu_illegal)&&(alu_gie)&&(!clear_pipeline)) |
r_ill_err_u <= 1'b1; |
|
assign ill_err_u = r_ill_err_u; |
`endif |
`else |
assign ill_err_u = 1'b0; |
assign ill_err_i = 1'b0; |
1483,26 → 1686,29
always @(posedge i_clk) |
if (i_rst) |
ibus_err_flag <= 1'b0; |
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG}) |
&&(~wr_reg_vl[`CPU_BUSERR_BIT])) |
ibus_err_flag <= 1'b0; |
else if ((dbgv)&&(wr_write_scc)) |
ibus_err_flag <= (ibus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]); |
else if ((bus_err)&&(~alu_gie)) |
ibus_err_flag <= 1'b1; |
// User bus error flag -- if ever set, it will cause an interrupt to |
// supervisor mode. |
initial ubus_err_flag = 1'b0; |
// supervisor mode. |
`ifdef OPT_NO_USERMODE |
assign ubus_err_flag = 1'b0; |
`else |
reg r_ubus_err_flag; |
|
initial r_ubus_err_flag = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
ubus_err_flag <= 1'b0; |
else if (w_release_from_interrupt) |
ubus_err_flag <= 1'b0; |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce) |
&&(~wr_reg_vl[`CPU_BUSERR_BIT]) |
&&(wr_reg_id[4])&&(wr_write_cc)) |
ubus_err_flag <= 1'b0; |
if ((i_rst)||(w_release_from_interrupt)) |
r_ubus_err_flag <= 1'b0; |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc)) |
r_ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]); |
else if ((bus_err)&&(alu_gie)) |
ubus_err_flag <= 1'b1; |
r_ubus_err_flag <= 1'b1; |
|
assign ubus_err_flag = r_ubus_err_flag; |
`endif |
|
generate |
if (IMPLEMENT_DIVIDE != 0) |
begin |
1515,28 → 1721,29
always @(posedge i_clk) |
if (i_rst) |
r_idiv_err_flag <= 1'b0; |
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG}) |
&&(~wr_reg_vl[`CPU_DIVERR_BIT])) |
r_idiv_err_flag <= 1'b0; |
else if ((div_error)&&(div_valid)&&(~alu_gie)) |
else if ((dbgv)&&(wr_write_scc)) |
r_idiv_err_flag <= (r_idiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]); |
else if ((div_error)&&(~alu_gie)) |
r_idiv_err_flag <= 1'b1; |
|
assign idiv_err_flag = r_idiv_err_flag; |
`ifdef OPT_NO_USERMODE |
assign udiv_err_flag = 1'b0; |
`else |
// User divide (by zero) error flag -- if ever set, it will |
// cause a sudden switch interrupt to supervisor mode. |
// cause a sudden switch interrupt to supervisor mode. |
initial r_udiv_err_flag = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
if ((i_rst)||(w_release_from_interrupt)) |
r_udiv_err_flag <= 1'b0; |
else if (w_release_from_interrupt) |
r_udiv_err_flag <= 1'b0; |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce) |
&&(~wr_reg_vl[`CPU_DIVERR_BIT]) |
&&(wr_reg_id[4])&&(wr_write_cc)) |
r_udiv_err_flag <= 1'b0; |
else if ((div_error)&&(alu_gie)&&(div_valid)) |
&&(wr_write_ucc)) |
r_udiv_err_flag <= (r_udiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]); |
else if ((div_error)&&(alu_gie)) |
r_udiv_err_flag <= 1'b1; |
|
assign idiv_err_flag = r_idiv_err_flag; |
assign udiv_err_flag = r_udiv_err_flag; |
`endif |
end else begin |
assign idiv_err_flag = 1'b0; |
assign udiv_err_flag = 1'b0; |
1552,23 → 1759,19
always @(posedge i_clk) |
if (i_rst) |
r_ifpu_err_flag <= 1'b0; |
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG}) |
&&(~wr_reg_vl[`CPU_FPUERR_BIT])) |
r_ifpu_err_flag <= 1'b0; |
else if ((dbgv)&&(wr_write_scc)) |
r_ifpu_err_flag <= (r_ifpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]); |
else if ((fpu_error)&&(fpu_valid)&&(~alu_gie)) |
r_ifpu_err_flag <= 1'b1; |
// User floating point error flag -- if ever set, it will cause |
// a sudden switch interrupt to supervisor mode. |
// a sudden switch interrupt to supervisor mode. |
initial r_ufpu_err_flag = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
if ((i_rst)&&(w_release_from_interrupt)) |
r_ufpu_err_flag <= 1'b0; |
else if (w_release_from_interrupt) |
r_ufpu_err_flag <= 1'b0; |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce) |
&&(~wr_reg_vl[`CPU_FPUERR_BIT]) |
&&(wr_reg_id[4])&&(wr_write_cc)) |
r_ufpu_err_flag <= 1'b0; |
&&(wr_write_ucc)) |
r_ufpu_err_flag <= (r_ufpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]); |
else if ((fpu_error)&&(alu_gie)&&(fpu_valid)) |
r_ufpu_err_flag <= 1'b1; |
|
1579,22 → 1782,34
assign ufpu_err_flag = 1'b0; |
end endgenerate |
|
`ifdef OPT_VLIW |
reg r_ihalt_phase, r_uhalt_phase; |
`ifdef OPT_CIS |
reg r_ihalt_phase; |
|
initial r_ihalt_phase = 0; |
initial r_uhalt_phase = 0; |
always @(posedge i_clk) |
if (~alu_gie) |
if (i_rst) |
r_ihalt_phase <= 1'b0; |
else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline)) |
r_ihalt_phase <= alu_phase; |
|
assign ihalt_phase = r_ihalt_phase; |
|
`ifdef OPT_NO_USERMODE |
assign uhalt_phase = 1'b0; |
`else |
reg r_uhalt_phase; |
|
initial r_uhalt_phase = 0; |
always @(posedge i_clk) |
if (alu_gie) |
if ((i_rst)||(w_release_from_interrupt)) |
r_uhalt_phase <= 1'b0; |
else if ((alu_gie)&&(alu_pc_valid)) |
r_uhalt_phase <= alu_phase; |
else if (w_release_from_interrupt) |
r_uhalt_phase <= 1'b0; |
else if ((~alu_gie)&&(wr_reg_ce)&&(wr_write_ucc)) |
r_uhalt_phase <= wr_spreg_vl[`CPU_PHASE_BIT]; |
|
assign ihalt_phase = r_ihalt_phase; |
assign uhalt_phase = r_uhalt_phase; |
`endif |
`else |
assign ihalt_phase = 1'b0; |
assign uhalt_phase = 1'b0; |
1610,48 → 1825,70
// What happens when the pipeline has gie and ~gie instructions within |
// it? Do we clear both? What if a gie instruction tries to clear |
// a non-gie instruction? |
`ifdef OPT_NO_USERMODE |
assign upc = {(AW+2){1'b0}}; |
`else |
reg [(AW+1):0] r_upc; |
|
always @(posedge i_clk) |
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc)) |
upc <= wr_reg_vl[(AW-1):0]; |
r_upc <= { wr_spreg_vl[(AW+1):2], 2'b00 }; |
else if ((alu_gie)&& |
(((alu_pc_valid)&&(~clear_pipeline)) |
(((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal)) |
||(mem_pc_valid))) |
upc <= alu_pc; |
r_upc <= { alu_pc, 2'b00 }; |
assign upc = r_upc; |
`endif |
|
always @(posedge i_clk) |
if (i_rst) |
ipc <= RESET_ADDRESS; |
ipc <= { RESET_BUS_ADDRESS, 2'b00 }; |
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc)) |
ipc <= wr_reg_vl[(AW-1):0]; |
else if ((~alu_gie)&& |
(((alu_pc_valid)&&(~clear_pipeline)) |
ipc <= { wr_spreg_vl[(AW+1):2], 2'b00 }; |
else if ((!alu_gie)&&(!alu_phase)&& |
(((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal)) |
||(mem_pc_valid))) |
ipc <= alu_pc; |
ipc <= { alu_pc, 2'b00 }; |
|
always @(posedge i_clk) |
if (i_rst) |
pf_pc <= RESET_ADDRESS; |
else if (w_switch_to_interrupt) |
pf_pc <= ipc; |
else if (w_release_from_interrupt) |
pf_pc <= upc; |
pf_pc <= { RESET_BUS_ADDRESS, 2'b00 }; |
else if ((w_switch_to_interrupt)||((~gie)&&(w_clear_icache))) |
pf_pc <= { ipc[(AW+1):2], 2'b00 }; |
else if ((w_release_from_interrupt)||((gie)&&(w_clear_icache))) |
pf_pc <= { upc[(AW+1):2], 2'b00 }; |
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc)) |
pf_pc <= wr_reg_vl[(AW-1):0]; |
pf_pc <= { wr_spreg_vl[(AW+1):2], 2'b00 }; |
`ifdef OPT_PIPELINED |
else if ((dcd_early_branch)&&(~clear_pipeline)) |
pf_pc <= dcd_branch_pc + 1; |
else if ((new_pc)||((~dcd_stalled)&&(pf_valid))) |
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1}; |
pf_pc <= { dcd_branch_pc + 1'b1, 2'b00 }; |
else if ((new_pc)||((!pf_stalled)&&(pf_valid))) |
pf_pc <= { pf_pc[(AW+1):2] + {{(AW-1){1'b0}},1'b1}, 2'b00 }; |
`else |
else if ((alu_gie==gie)&&( |
((alu_pc_valid)&&(~clear_pipeline)) |
||(mem_pc_valid))) |
pf_pc <= alu_pc; |
pf_pc <= { alu_pc[(AW-1):0], 2'b00 }; |
`endif |
|
`ifdef OPT_PIPELINED |
reg r_clear_icache; |
initial r_clear_icache = 1'b1; |
always @(posedge i_clk) |
if ((i_rst)||(i_clear_pf_cache)) |
r_clear_icache <= 1'b1; |
else if ((wr_reg_ce)&&(wr_write_scc)) |
r_clear_icache <= wr_spreg_vl[`CPU_CLRCACHE_BIT]; |
else |
r_clear_icache <= 1'b0; |
assign w_clear_icache = r_clear_icache; |
`else |
assign w_clear_icache = i_clear_pf_cache; |
`endif |
|
initial new_pc = 1'b1; |
always @(posedge i_clk) |
if ((i_rst)||(i_clear_pf_cache)) |
if ((i_rst)||(w_clear_icache)) |
new_pc <= 1'b1; |
else if (w_switch_to_interrupt) |
new_pc <= 1'b1; |
1664,42 → 1901,65
|
// |
// The debug interface |
wire [31:0] w_debug_pc; |
`ifdef OPT_NO_USERMODE |
assign w_debug_pc[(AW+1):0] = { ipc, 2'b00 }; |
`else |
assign w_debug_pc[(AW+1):0] = { (i_dbg_reg[4]) |
? { upc[(AW+1):2], uhalt_phase, 1'b0 } |
: { ipc[(AW+1):2], ihalt_phase, 1'b0 } }; |
`endif |
generate |
if (AW<32) |
if (AW<30) |
assign w_debug_pc[31:(AW+2)] = 0; |
endgenerate |
|
always @(posedge i_clk) |
begin |
always @(posedge i_clk) |
`ifdef OPT_NO_USERMODE |
o_dbg_reg <= regset[i_dbg_reg[3:0]]; |
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= w_debug_pc; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
begin |
o_dbg_reg <= regset[i_dbg_reg]; |
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc}; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
begin |
o_dbg_reg[13:0] <= (i_dbg_reg[4])?w_uflags:w_iflags; |
o_dbg_reg[`CPU_GIE_BIT] <= gie; |
end |
o_dbg_reg[14:0] <= w_iflags; |
o_dbg_reg[15] <= 1'b0; |
o_dbg_reg[31:23] <= w_cpu_info; |
o_dbg_reg[`CPU_GIE_BIT] <= gie; |
end |
end else begin |
always @(posedge i_clk) |
`else |
o_dbg_reg <= regset[i_dbg_reg]; |
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= w_debug_pc; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
begin |
o_dbg_reg <= regset[i_dbg_reg]; |
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= (i_dbg_reg[4])?upc:ipc; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
begin |
o_dbg_reg[13:0] <= (i_dbg_reg[4])?w_uflags:w_iflags; |
o_dbg_reg[`CPU_GIE_BIT] <= gie; |
end |
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags; |
o_dbg_reg[15] <= 1'b0; |
o_dbg_reg[31:23] <= w_cpu_info; |
o_dbg_reg[`CPU_GIE_BIT] <= gie; |
end |
end endgenerate |
`endif |
end |
|
always @(posedge i_clk) |
o_dbg_cc <= { o_break, bus_err, gie, sleep }; |
|
`ifdef OPT_PIPELINED |
always @(posedge i_clk) |
o_dbg_stall <= (i_halt)&&( |
(pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy) |
||((~opvalid)&&(~i_rst)&&(~dcd_illegal)) |
||((~dcdvalid)&&(~i_rst)&&(~pf_illegal))); |
r_halted <= (i_halt)&&( |
// To be halted, any long lasting instruction must |
// be completed. |
(~pf_cyc)&&(~mem_busy)&&(~alu_busy) |
&&(~div_busy)&&(~fpu_busy) |
// Operations must either be valid, or illegal |
&&((op_valid)||(i_rst)||(dcd_illegal)) |
// Decode stage must be either valid, in reset, or ill |
&&((dcd_valid)||(i_rst)||(pf_illegal))); |
`else |
always @(posedge i_clk) |
r_halted <= (i_halt)&&((op_valid)||(i_rst)); |
`endif |
assign o_dbg_stall = ~r_halted; |
|
// |
// |
1714,73 → 1974,50
`ifdef DEBUG_SCOPE |
always @(posedge i_clk) |
o_debug <= { |
/* |
/* |
o_break, i_wb_err, pf_pc[1:0], |
// |
flags, |
// |
pf_valid, dcdvalid, opvalid, alu_valid, |
// |
mem_valid, |
pf_valid, dcd_valid, op_valid, alu_valid, mem_valid, |
op_ce, alu_ce, mem_ce, |
// |
master_ce, |
opvalid_alu, opvalid_mem, alu_stall, |
master_ce, op_valid_alu, op_valid_mem, |
// |
mem_busy, op_pipe, |
`ifdef OPT_PIPELINED_BUS_ACCESS |
mem_pipe_stalled, |
`else |
1'b0, |
`endif |
alu_stall, mem_busy, op_pipe, mem_pipe_stalled, |
mem_we, |
// |
// ((opvalid_alu)&&(alu_stall)) |
// ||((opvalid_mem)&&(~op_pipe)&&(mem_busy)) |
// ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled))); |
// opA[23:20], opA[3:0], |
gie, sleep, wr_reg_ce, wr_reg_vl[4:0] |
*/ |
|
o_break, i_wb_err, o_wb_gbl_cyc, o_wb_gbl_stb, |
pf_valid, dcdvalid, opvalid, alu_valid, |
mem_valid, dcd_ce, op_ce, alu_ce, |
mem_ce, |
pf_ce, gie, sleep, |
{ ((o_wb_gbl_cyc)&&(o_wb_gbl_stb)&&(o_wb_we)) |
? o_wb_data[15:0] |
: ((o_wb_gbl_cyc)&&(~o_wb_we)&&(i_wb_ack)) |
? i_wb_data[15:0] |
: o_wb_addr[15:0] |
} |
// ((op_valid_alu)&&(alu_stall)) |
// ||((op_valid_mem)&&(~op_pipe)&&(mem_busy)) |
// ||((op_valid_mem)&&( op_pipe)&&(mem_pipe_stalled))); |
// op_Av[23:20], op_Av[3:0], |
gie, sleep, wr_reg_ce, wr_gpreg_vl[4:0] |
*/ |
/* |
i_rst, master_ce, (new_pc), |
((dcd_early_branch)&&(dcdvalid)), |
((dcd_early_branch)&&(dcd_valid)), |
pf_valid, pf_illegal, |
op_ce, dcd_ce, dcdvalid, dcd_stalled, |
op_ce, dcd_ce, dcd_valid, dcd_stalled, |
pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err, |
pf_pc[7:0], pf_addr[7:0] |
*/ |
/* |
|
i_wb_err, gie, alu_illegal, |
(new_pc)||((dcd_early_branch)&&(~clear_pipeline)), |
mem_busy, |
(mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we, |
o_wb_addr[8:0] } |
: { instruction[31:21] }, |
: { pf_instruction[31:21] }, |
pf_valid, (pf_valid) ? alu_pc[14:0] |
:{ pf_cyc, pf_stb, pf_pc[12:0] } |
*/ |
:{ pf_cyc, pf_stb, pf_pc[14:2] } |
|
/* |
i_wb_err, gie, new_pc, dcd_early_branch, // 4 |
pf_valid, pf_cyc, pf_stb, instruction_pc[0], // 4 |
instruction[30:27], // 4 |
pf_valid, pf_cyc, pf_stb, pf_instruction_pc[0], // 4 |
pf_instruction[30:27], // 4 |
dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb, // 4 |
dcdvalid, |
dcd_valid, |
((dcd_early_branch)&&(~clear_pipeline)) // 15 |
? dcd_branch_pc[14:0]:pf_pc[14:0] |
*/ |
}; |
`endif |
|
|
endmodule |
/rtl/cpu/ziptimer.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: ziptimer.v |
// |
43,9 → 43,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
57,12 → 57,18
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module ziptimer(i_clk, i_rst, i_ce, |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
84,7 → 90,7
wire wb_write; |
assign wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)); |
|
wire auto_reload, need_reload; |
wire auto_reload; |
wire [(VW-1):0] reload_value; |
|
initial r_running = 1'b0; |
99,10 → 105,11
generate |
if (RELOADABLE != 0) |
begin |
reg r_auto_reload, r_need_reload; |
reg r_auto_reload; |
reg [(VW-1):0] r_reload_value; |
|
initial r_auto_reload = 1'b0; |
|
always @(posedge i_clk) |
if (wb_write) |
r_auto_reload <= (i_wb_data[(BW-1)]); |
115,20 → 122,9
if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0])) |
r_reload_value <= i_wb_data[(VW-1):0]; |
assign reload_value = r_reload_value; |
|
initial r_need_reload = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_need_reload <= 1'b0; |
else if ((i_ce)&&(auto_reload)) |
r_need_reload <= (i_ce) |
&&(r_value == { {(VW-1){1'b0}}, 1'b1 }); |
|
assign need_reload = r_need_reload; |
end else begin |
assign auto_reload = 1'b0; |
assign reload_value = 0; |
assign need_reload = 1'b0; |
end endgenerate |
|
|
/rtl/deppbyte.v
14,7 → 14,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
27,7 → 27,7
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
77,9 → 77,9
|
reg [7:0] addr; |
wire astb, dstb, w_write; |
assign astb = (~r_astb_n)&&(l_astb_n); |
assign dstb = (~r_dstb_n)&&(l_dstb_n); |
assign w_write= (~r_write_n); |
assign astb = (!r_astb_n)&&(l_astb_n); |
assign dstb = (!r_dstb_n)&&(l_dstb_n); |
assign w_write= (!r_write_n); |
|
|
initial addr = 8'h00; |
102,7 → 102,7
// (less than one clock) of when the strobe lines are brought low, and |
// raised high again within 10 ms of when the strobe lines are raised |
// again. |
assign o_wait = ((~i_dstb_n)||(~i_astb_n)); |
assign o_wait = ((!i_dstb_n)||(!i_astb_n)); |
|
// For one clock, following any read from address zero, we allow the |
// port to write one new byte into our interface. This works because |
/rtl/llqspi.v
189,6 → 189,7
initial o_valid = 1'b0; |
initial o_busy = 1'b0; |
initial r_input = 31'h000; |
initial o_mod = `QSPI_MOD_SPI; |
always @(posedge i_clk) |
if ((state == `QSPI_IDLE)&&(o_sck)) |
begin |
196,16 → 197,16
o_valid <= 1'b0; |
o_busy <= 1'b0; |
o_mod <= `QSPI_MOD_SPI; |
r_word <= i_word; |
r_spd <= i_spd; |
r_dir <= i_dir; |
if (i_wr) |
begin |
r_word <= i_word; |
state <= `QSPI_START; |
r_spd <= i_spd; |
r_dir <= i_dir; |
spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8; |
o_cs_n <= 1'b0; |
// o_sck <= 1'b1; |
o_busy <= 1'b1; |
o_sck <= 1'b1; |
end |
end else if (state == `QSPI_START) |
begin // We come in here with sck high, stay here 'til sck is low |
224,13 → 225,9
o_busy <= 1'b1; |
o_valid <= 1'b0; |
if (r_spd) |
begin |
o_dat <= r_word[31:28]; |
// r_word <= { r_word[27:0], 4'h0 }; |
end else begin |
else |
o_dat <= { 3'b110, r_word[31] }; |
// r_word <= { r_word[30:0], 1'b0 }; |
end |
end else if (~o_sck) |
begin |
o_sck <= 1'b1; |
272,6 → 269,16
// this state. Here we chose to either STOP or |
// continue and transmit more. |
o_sck <= (i_hold); // No clocks while holding |
r_spd <= i_spd; |
r_dir <= i_dir; |
if (i_spd) |
begin |
r_word <= { i_word[27:0], 4'h0 }; |
spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8 - 6'h4; |
end else begin |
r_word <= { i_word[30:0], 1'b0 }; |
spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8 - 6'h1; |
end |
if((~o_busy)&&(i_wr))// Acknowledge a new request |
begin |
state <= `QSPI_BITS; |
279,51 → 286,29
o_sck <= 1'b0; |
|
// Read the new request off the bus |
r_spd <= i_spd; |
r_dir <= i_dir; |
// Set up the first bits on the bus |
o_mod <= (i_spd) ? { 1'b1, i_dir } : `QSPI_MOD_SPI; |
if (i_spd) |
begin |
o_dat <= i_word[31:28]; |
r_word <= { i_word[27:0], 4'h0 }; |
// spi_len <= spi_len - 4; |
spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8 |
- 6'h4; |
end else begin |
else |
o_dat <= { 3'b110, i_word[31] }; |
r_word <= { i_word[30:0], 1'b0 }; |
spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8 |
- 6'h1; |
end |
|
// Read a bit upon any transition |
o_valid <= 1'b1; |
if (~o_mod[1]) |
begin |
r_input <= { r_input[29:0], i_miso }; |
o_word <= { r_input[30:0], i_miso }; |
end else if (o_mod[1]) |
begin |
r_input <= { r_input[26:0], i_dat }; |
o_word <= { r_input[27:0], i_dat }; |
end |
end else begin |
o_sck <= 1'b1; |
state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP; |
o_busy <= (~i_hold); |
end |
|
// Read a bit upon any transition |
o_valid <= 1'b1; |
if (~o_mod[1]) |
begin |
r_input <= { r_input[29:0], i_miso }; |
o_word <= { r_input[30:0], i_miso }; |
end else if (o_mod[1]) |
begin |
r_input <= { r_input[26:0], i_dat }; |
o_word <= { r_input[27:0], i_dat }; |
end |
// Read a bit upon any transition |
o_valid <= 1'b1; |
if (~o_mod[1]) |
begin |
r_input <= { r_input[29:0], i_miso }; |
o_word <= { r_input[30:0], i_miso }; |
end else if (o_mod[1]) |
begin |
r_input <= { r_input[26:0], i_dat }; |
o_word <= { r_input[27:0], i_dat }; |
end |
end else if (state == `QSPI_HOLDING) |
begin |
338,6 → 323,16
o_valid <= 1'b0; |
o_cs_n <= 1'b0; |
o_busy <= 1'b0; |
r_spd <= i_spd; |
r_dir <= i_dir; |
if (i_spd) |
begin |
r_word <= { i_word[27:0], 4'h0 }; |
spi_len<= { 1'b0, i_len, 3'b100 }; |
end else begin |
r_word <= { i_word[30:0], 1'b0 }; |
spi_len<= { 1'b0, i_len, 3'b111 }; |
end |
if((~o_busy)&&(i_wr))// Acknowledge a new request |
begin |
state <= `QSPI_BITS; |
345,20 → 340,12
o_sck <= 1'b0; |
|
// Read the new request off the bus |
r_spd <= i_spd; |
r_dir <= i_dir; |
// Set up the first bits on the bus |
o_mod<=(i_spd)?{ 1'b1, i_dir } : `QSPI_MOD_SPI; |
if (i_spd) |
begin |
o_dat <= i_word[31:28]; |
r_word <= { i_word[27:0], 4'h0 }; |
spi_len<= { 1'b0, i_len, 3'b100 }; |
end else begin |
else |
o_dat <= { 3'b110, i_word[31] }; |
r_word <= { i_word[30:0], 1'b0 }; |
spi_len<= { 1'b0, i_len, 3'b111 }; |
end |
end else begin |
o_sck <= 1'b1; |
state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP; |
/rtl/memdev.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: memdev.v |
// |
14,9 → 14,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
28,31 → 28,88
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module memdev(i_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
module memdev(i_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel, |
o_wb_ack, o_wb_stall, o_wb_data); |
parameter AW=15, DW=32; |
parameter LGMEMSZ=15, DW=32, EXTRACLOCK= 0; |
localparam AW = LGMEMSZ - 2; |
input i_clk, i_wb_cyc, i_wb_stb, i_wb_we; |
input [(AW-1):0] i_wb_addr; |
input [(DW-1):0] i_wb_data; |
input [(DW/8-1):0] i_wb_sel; |
output reg o_wb_ack; |
output wire o_wb_stall; |
output reg [(DW-1):0] o_wb_data; |
|
wire w_wstb, w_stb; |
wire [(DW-1):0] w_data; |
wire [(AW-1):0] w_addr; |
wire [(DW/8-1):0] w_sel; |
|
generate |
if (EXTRACLOCK == 0) |
begin |
|
assign w_wstb = (i_wb_stb)&&(i_wb_we); |
assign w_stb = i_wb_stb; |
assign w_addr = i_wb_addr; |
assign w_data = i_wb_data; |
assign w_sel = i_wb_sel; |
|
end else begin |
|
reg last_wstb, last_stb; |
always @(posedge i_clk) |
last_wstb <= (i_wb_stb)&&(i_wb_we); |
always @(posedge i_clk) |
last_stb <= (i_wb_stb); |
|
reg [(AW-1):0] last_addr; |
reg [(DW-1):0] last_data; |
reg [(DW/8-1):0] last_sel; |
always @(posedge i_clk) |
last_data <= i_wb_data; |
always @(posedge i_clk) |
last_addr <= i_wb_addr; |
always @(posedge i_clk) |
last_sel <= i_wb_sel; |
|
assign w_wstb = last_wstb; |
assign w_stb = last_stb; |
assign w_addr = last_addr; |
assign w_data = last_data; |
assign w_sel = last_sel; |
end endgenerate |
|
reg [(DW-1):0] mem [0:((1<<AW)-1)]; |
|
always @(posedge i_clk) |
o_wb_data <= mem[i_wb_addr]; |
o_wb_data <= mem[w_addr]; |
always @(posedge i_clk) |
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)) |
mem[i_wb_addr] <= i_wb_data; |
begin |
if ((w_wstb)&&(w_sel[3])) |
mem[w_addr][31:24] <= w_data[31:24]; |
if ((w_wstb)&&(w_sel[2])) |
mem[w_addr][23:16] <= w_data[23:16]; |
if ((w_wstb)&&(w_sel[1])) |
mem[w_addr][15: 8] <= w_data[15:8]; |
if ((w_wstb)&&(w_sel[0])) |
mem[w_addr][ 7: 0] <= w_data[7:0]; |
end |
|
always @(posedge i_clk) |
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb); |
o_wb_ack <= (w_stb); |
assign o_wb_stall = 1'b0; |
|
endmodule |
/rtl/rxuart.v
2,7 → 2,7
// |
// Filename: rxuart.v |
// |
// Project: CMod S6 System on a Chip, ZipCPU demonstration project |
// Project: wbuart32, a full featured UART with simulator |
// |
// Purpose: Receive and decode inputs from a single UART line. |
// |
19,9 → 19,13
// Now for the setup register. The register is 32 bits, so that this |
// UART may be set up over a 32-bit bus. |
// |
// i_setup[30] True if we are not using hardware flow control. This bit |
// is ignored within this module, as any receive hardware flow |
// control will need to be implemented elsewhere. |
// |
// i_setup[29:28] Indicates the number of data bits per word. This will |
// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10 |
// for a six bit word, or 2'b11 for a five bit word. |
// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10 |
// for a six bit word, or 2'b11 for a five bit word. |
// |
// i_setup[27] Indicates whether or not to use one or two stop bits. |
// Set this to one to expect two stop bits, zero for one. |
74,7 → 78,7
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
90,7 → 94,7
// ..7 Bits arrive |
// 8 Stop bit (x1) |
// 9 Stop bit (x2) |
/// c break condition |
// c break condition |
// d Waiting for the channel to go high |
// e Waiting for the reset to complete |
// f Idle state |
111,15 → 115,13
`define RXU_RESET_IDLE 4'he |
`define RXU_IDLE 4'hf |
|
module rxuart(i_clk, i_reset, i_setup, i_uart, o_wr, o_data, o_break, |
module rxuart(i_clk, i_reset, i_setup, i_uart_rx, o_wr, o_data, o_break, |
o_parity_err, o_frame_err, o_ck_uart); |
// parameter // CLOCKS_PER_BAUD = 25'd004340, |
// BREAK_CONDITION = CLOCKS_PER_BAUD * 12, |
// CLOCKS_PER_HALF_BAUD = CLOCKS_PER_BAUD/2; |
parameter [30:0] INITIAL_SETUP = 31'd868; |
// 8 data bits, no parity, (at least 1) stop bit |
input i_clk, i_reset; |
input [29:0] i_setup; |
input i_uart; |
input [30:0] i_setup; |
input i_uart_rx; |
output reg o_wr; |
output reg [7:0] o_data; |
output reg o_break; |
131,7 → 133,10
wire [1:0] data_bits; |
wire use_parity, parity_even, dblstop, fixd_parity; |
reg [29:0] r_setup; |
reg [3:0] state; |
|
assign clocks_per_baud = { 4'h0, r_setup[23:0] }; |
// assign hw_flow_control = !r_setup[30]; |
assign data_bits = r_setup[29:28]; |
assign dblstop = r_setup[27]; |
assign use_parity = r_setup[26]; |
138,8 → 143,15
assign fixd_parity = r_setup[25]; |
assign parity_even = r_setup[24]; |
assign break_condition = { r_setup[23:0], 4'h0 }; |
assign half_baud = { 5'h00, r_setup[23:1] }; |
assign half_baud = { 5'h00, r_setup[23:1] }-28'h1; |
reg [27:0] baud_counter; |
reg zero_baud_counter; |
|
|
// Since this is an asynchronous receiver, we need to register our |
// input a couple of clocks over to avoid any problems with |
// metastability. We do that here, and then ignore all but the |
// ck_uart wire. |
reg q_uart, qq_uart, ck_uart; |
initial q_uart = 1'b0; |
initial qq_uart = 1'b0; |
146,12 → 158,19
initial ck_uart = 1'b0; |
always @(posedge i_clk) |
begin |
q_uart <= i_uart; |
q_uart <= i_uart_rx; |
qq_uart <= q_uart; |
ck_uart <= qq_uart; |
end |
|
// In case anyone else wants this clocked, stabilized value, we |
// offer it on our output. |
assign o_ck_uart = ck_uart; |
|
// Keep track of the number of clocks since the last change. |
// |
// This is used to determine if we are in either a break or an idle |
// condition, as discussed further below. |
reg [27:0] chg_counter; |
initial chg_counter = 28'h00; |
always @(posedge i_clk) |
162,71 → 181,100
else if (chg_counter < break_condition) |
chg_counter <= chg_counter + 1; |
|
// Are we in a break condition? |
// |
// A break condition exists if the line is held low for longer than |
// a data word. Hence, we keep track of when the last change occurred. |
// If it was more than break_condition clocks ago, and the current input |
// value is a 0, then we're in a break--and nothing can be read until |
// the line idles again. |
initial o_break = 1'b0; |
always @(posedge i_clk) |
o_break <=((chg_counter >= break_condition)&&(~ck_uart))? 1'b1:1'b0; |
o_break <= ((chg_counter >= break_condition)&&(~ck_uart))? 1'b1:1'b0; |
|
reg [3:0] state; |
reg [27:0] baud_counter; |
reg [7:0] data_reg; |
reg calc_parity; |
initial o_wr = 1'b0; |
// Are we between characters? |
// |
// The opposite of a break condition is where the line is held high |
// for more clocks than would be in a character. When this happens, |
// we know we have synchronization--otherwise, we might be sampling |
// from within a data word. |
// |
// This logic is used later to hold the RXUART in a reset condition |
// until we know we are between data words. At that point, we should |
// be able to hold on to our synchronization. |
reg line_synch; |
initial line_synch = 1'b0; |
always @(posedge i_clk) |
line_synch <= ((chg_counter >= break_condition)&&(ck_uart)); |
|
// Are we in the middle of a baud iterval? Specifically, are we |
// in the middle of a start bit? Set this to high if so. We'll use |
// this within our state machine to transition out of the IDLE |
// state. |
reg half_baud_time; |
initial half_baud_time = 0; |
always @(posedge i_clk) |
half_baud_time <= (~ck_uart)&&(chg_counter >= half_baud); |
|
|
// Allow our controlling processor to change our setup at any time |
// outside of receiving/processing a character. |
initial r_setup = INITIAL_SETUP[29:0]; |
always @(posedge i_clk) |
if (state >= `RXU_RESET_IDLE) |
r_setup <= i_setup[29:0]; |
|
|
// Our monster state machine. YIKES! |
// |
// Yeah, this may be more complicated than it needs to be. The basic |
// progression is: |
// RESET -> RESET_IDLE -> (when line is idle) -> IDLE |
// IDLE -> bit 0 -> bit 1 -> bit_{ndatabits} -> |
// (optional) PARITY -> STOP -> (optional) SECOND_STOP |
// -> IDLE |
// ANY -> (on break) BREAK -> IDLE |
// |
// There are 16 states, although all are not used. These are listed |
// at the top of this file. |
// |
// Logic inputs (12): (I've tried to minimize this number) |
// state (4) |
// i_reset |
// line_synch |
// o_break |
// ckuart |
// half_baud_time |
// zero_baud_counter |
// use_parity |
// dblstop |
// Logic outputs (4): |
// state |
// |
initial state = `RXU_RESET_IDLE; |
initial o_parity_err = 1'b0; |
initial o_frame_err = 1'b0; |
// initial baud_counter = clocks_per_baud; |
always @(posedge i_clk) |
begin |
if (i_reset) |
begin |
o_wr <= 1'b0; |
o_data <= 8'h00; |
state <= `RXU_RESET_IDLE; |
baud_counter <= clocks_per_baud; // Set, not reset |
data_reg <= 8'h00; |
calc_parity <= 1'b0; |
o_parity_err <= 1'b0; |
o_frame_err <= 1'b0; |
end else if (state == `RXU_RESET_IDLE) |
else if (state == `RXU_RESET_IDLE) |
begin |
r_setup <= i_setup; |
data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0; |
baud_counter <= clocks_per_baud-28'h01;// Set, not reset |
if ((ck_uart)&&(chg_counter >= break_condition)) |
if (line_synch) |
// Goto idle state from a reset |
state <= `RXU_IDLE; |
else // Otherwise, stay in this condition 'til reset |
state <= `RXU_RESET_IDLE; |
calc_parity <= 1'b0; |
o_parity_err <= 1'b0; |
o_frame_err <= 1'b0; |
end else if ((~ck_uart)&&(chg_counter >= break_condition)) |
end else if (o_break) |
begin // We are in a break condition |
state <= `RXU_BREAK; |
o_wr <= 1'b0; |
o_data <= 8'h00; |
baud_counter <= clocks_per_baud-28'h01;// Set, not reset |
data_reg <= 8'h00; |
calc_parity <= 1'b0; |
o_parity_err <= 1'b0; |
o_frame_err <= 1'b0; |
r_setup <= i_setup; |
end else if (state == `RXU_BREAK) |
begin // Goto idle state following return ck_uart going high |
data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0; |
baud_counter <= clocks_per_baud - 28'h01; |
if (ck_uart) |
state <= `RXU_IDLE; |
else |
state <= `RXU_BREAK; |
calc_parity <= 1'b0; |
o_parity_err <= 1'b0; |
o_frame_err <= 1'b0; |
r_setup <= i_setup; |
end else if (state == `RXU_IDLE) |
begin // Idle state, independent of baud counter |
data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0; |
baud_counter <= clocks_per_baud - 28'h01; |
if ((ck_uart == 1'b0)&&(chg_counter > half_baud)) |
if ((~ck_uart)&&(half_baud_time)) |
begin |
// We are in the center of a valid start bit |
case (data_bits) |
237,79 → 285,179
endcase |
end else // Otherwise, just stay here in idle |
state <= `RXU_IDLE; |
calc_parity <= 1'b0; |
o_parity_err <= 1'b0; |
o_frame_err <= 1'b0; |
end else if (baud_counter == 0) |
end else if (zero_baud_counter) |
begin |
baud_counter <= clocks_per_baud-28'h1; |
if (state < `RXU_BIT_SEVEN) |
begin |
// Data arrives least significant bit first. |
// By the time this is clocked in, it's what |
// you'll have. |
data_reg <= { ck_uart, data_reg[7:1] }; |
calc_parity <= calc_parity ^ ck_uart; |
o_data <= 8'h00; |
o_wr <= 1'b0; |
state <= state + 1; |
o_parity_err <= 1'b0; |
o_frame_err <= 1'b0; |
end else if (state == `RXU_BIT_SEVEN) |
begin |
data_reg <= { ck_uart, data_reg[7:1] }; |
calc_parity <= calc_parity ^ ck_uart; |
o_data <= 8'h00; |
o_wr <= 1'b0; |
else if (state == `RXU_BIT_SEVEN) |
state <= (use_parity) ? `RXU_PARITY:`RXU_STOP; |
o_parity_err <= 1'b0; |
o_frame_err <= 1'b0; |
end else if (state == `RXU_PARITY) |
begin |
if (fixd_parity) |
o_parity_err <= (ck_uart ^ parity_even); |
else |
o_parity_err <= ((parity_even && (calc_parity != ck_uart)) |
||((~parity_even)&&(calc_parity==ck_uart))); |
else if (state == `RXU_PARITY) |
state <= `RXU_STOP; |
o_frame_err <= 1'b0; |
end else if (state == `RXU_STOP) |
else if (state == `RXU_STOP) |
begin // Stop (or parity) bit(s) |
case (data_bits) |
2'b00: o_data <= data_reg; |
2'b01: o_data <= { 1'b0, data_reg[7:1] }; |
2'b10: o_data <= { 2'b0, data_reg[7:2] }; |
2'b11: o_data <= { 3'b0, data_reg[7:3] }; |
endcase |
o_wr <= 1'b1; // Pulse the write |
o_frame_err <= (~ck_uart); |
if (~ck_uart) |
if (~ck_uart) // On frame error, wait 4 ch idle |
state <= `RXU_RESET_IDLE; |
else if (dblstop) |
state <= `RXU_SECOND_STOP; |
else |
state <= `RXU_IDLE; |
// o_parity_err <= 1'b0; |
end else // state must equal RX_SECOND_STOP |
begin |
if (~ck_uart) |
begin |
o_frame_err <= 1'b1; |
if (~ck_uart) // On frame error, wait 4 ch idle |
state <= `RXU_RESET_IDLE; |
end else begin |
else |
state <= `RXU_IDLE; |
o_frame_err <= 1'b0; |
end |
o_parity_err <= 1'b0; |
end |
end else begin |
o_wr <= 1'b0; // data_reg = data_reg |
baud_counter <= baud_counter - 28'd1; |
o_parity_err <= 1'b0; |
o_frame_err <= 1'b0; |
end |
end |
|
// Data bit capture logic. |
// |
// This is drastically simplified from the state machine above, based |
// upon: 1) it doesn't matter what it is until the end of a captured |
// byte, and 2) the data register will flush itself of any invalid |
// data in all other cases. Hence, let's keep it real simple. |
// The only trick, though, is that if we have parity, then the data |
// register needs to be held through that state without getting |
// updated. |
reg [7:0] data_reg; |
always @(posedge i_clk) |
if ((zero_baud_counter)&&(state != `RXU_PARITY)) |
data_reg <= { ck_uart, data_reg[7:1] }; |
|
// Parity calculation logic |
// |
// As with the data capture logic, all that must be known about this |
// bit is that it is the exclusive-OR of all bits prior. The first |
// of those will follow idle, so we set ourselves to zero on idle. |
// Then, as we walk through the states of a bit, all will adjust this |
// value up until the parity bit, where the value will be read. Setting |
// it then or after will be irrelevant, so ... this should be good |
// and simplified. Note--we don't need to adjust this on reset either, |
// since the reset state will lead to the idle state where we'll be |
// reset before any transmission takes place. |
reg calc_parity; |
always @(posedge i_clk) |
if (state == `RXU_IDLE) |
calc_parity <= 0; |
else if (zero_baud_counter) |
calc_parity <= calc_parity ^ ck_uart; |
|
// Parity error logic |
// |
// Set during the parity bit interval, read during the last stop bit |
// interval, cleared on BREAK, RESET_IDLE, or IDLE states. |
initial o_parity_err = 1'b0; |
always @(posedge i_clk) |
if ((zero_baud_counter)&&(state == `RXU_PARITY)) |
begin |
if (fixd_parity) |
// Fixed parity bit--independent of any dat |
// value. |
o_parity_err <= (ck_uart ^ parity_even); |
else if (parity_even) |
// Parity even: The XOR of all bits including |
// the parity bit must be zero. |
o_parity_err <= (calc_parity != ck_uart); |
else |
// Parity odd: the parity bit must equal the |
// XOR of all the data bits. |
o_parity_err <= (calc_parity == ck_uart); |
end else if (state >= `RXU_BREAK) |
o_parity_err <= 1'b0; |
|
// Frame error determination |
// |
// For the purpose of this controller, a frame error is defined as a |
// stop bit (or second stop bit, if so enabled) not being high midway |
// through the stop baud interval. The frame error value is |
// immediately read, so we can clear it under all other circumstances. |
// Specifically, we want it clear in RXU_BREAK, RXU_RESET_IDLE, and |
// most importantly in RXU_IDLE. |
initial o_frame_err = 1'b0; |
always @(posedge i_clk) |
if ((zero_baud_counter)&&((state == `RXU_STOP) |
||(state == `RXU_SECOND_STOP))) |
o_frame_err <= (o_frame_err)||(~ck_uart); |
else if ((zero_baud_counter)||(state >= `RXU_BREAK)) |
o_frame_err <= 1'b0; |
|
// Our data bit logic doesn't need nearly the complexity of all that |
// work above. Indeed, we only need to know if we are at the end of |
// a stop bit, in which case we copy the data_reg into our output |
// data register, o_data. |
// |
// We would also set o_wr to be true when this is the case, but ... we |
// won't know if there is a frame error on the second stop bit for |
// another baud interval yet. So, instead, we set up the logic so that |
// we know on the next zero baud counter that we can write out. That's |
// the purpose of pre_wr. |
initial o_data = 8'h00; |
reg pre_wr; |
initial pre_wr = 1'b0; |
always @(posedge i_clk) |
if (i_reset) |
begin |
pre_wr <= 1'b0; |
o_data <= 8'h00; |
end else if ((zero_baud_counter)&&(state == `RXU_STOP)) |
begin |
pre_wr <= 1'b1; |
case (data_bits) |
2'b00: o_data <= data_reg; |
2'b01: o_data <= { 1'b0, data_reg[7:1] }; |
2'b10: o_data <= { 2'b0, data_reg[7:2] }; |
2'b11: o_data <= { 3'b0, data_reg[7:3] }; |
endcase |
end else if ((zero_baud_counter)||(state == `RXU_IDLE)) |
pre_wr <= 1'b0; |
|
// Create an output strobe, true for one clock only, once we know |
// all we need to know. o_data will be set on the last baud interval, |
// o_parity_err on the last parity baud interval (if it existed, |
// cleared otherwise, so ... we should be good to go here.) |
initial o_wr = 1'b0; |
always @(posedge i_clk) |
if ((zero_baud_counter)||(state == `RXU_IDLE)) |
o_wr <= (pre_wr)&&(!i_reset); |
else |
o_wr <= 1'b0; |
|
// The baud counter |
// |
// This is used as a "clock divider" if you will, but the clock needs |
// to be reset before any byte can be decoded. In all other respects, |
// we set ourselves up for clocks_per_baud counts between baud |
// intervals. |
always @(posedge i_clk) |
if (i_reset) |
baud_counter <= clocks_per_baud-28'h01; |
else if (zero_baud_counter) |
baud_counter <= clocks_per_baud-28'h01; |
else case(state) |
`RXU_RESET_IDLE:baud_counter <= clocks_per_baud-28'h01; |
`RXU_BREAK: baud_counter <= clocks_per_baud-28'h01; |
`RXU_IDLE: baud_counter <= clocks_per_baud-28'h01; |
default: baud_counter <= baud_counter-28'h01; |
endcase |
|
// zero_baud_counter |
// |
// Rather than testing whether or not (baud_counter == 0) within our |
// (already too complicated) state transition tables, we use |
// zero_baud_counter to pre-charge that test on the clock |
// before--cleaning up some otherwise difficult timing dependencies. |
initial zero_baud_counter = 1'b0; |
always @(posedge i_clk) |
if (state == `RXU_IDLE) |
zero_baud_counter <= 1'b0; |
else |
zero_baud_counter <= (baud_counter == 28'h01); |
|
|
endmodule |
|
|
/rtl/spio.v
57,7 → 57,7
initial o_kp_col = 4'h0; |
initial o_led = 4'h0; |
always @(posedge i_clk) |
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)) |
if ((i_wb_stb)&&(i_wb_we)) |
begin |
o_kp_col <= ((o_kp_col)&(~i_wb_data[11:8])) |
|((i_wb_data[15:12])&(i_wb_data[11:8])); |
/rtl/toplevel.v
53,7 → 53,7
module toplevel(i_clk_8mhz, |
o_qspi_cs_n, o_qspi_sck, io_qspi_dat, |
i_btn, o_led, o_pwm, o_pwm_shutdown_n, o_pwm_gain, |
i_uart, o_uart, o_uart_cts, i_uart_rts, |
i_uart, o_uart, o_uart_rts_n, i_uart_cts_n, |
i_kp_row, o_kp_col, |
i_gpio, o_gpio, |
io_scl, io_sda); |
73,8 → 73,8
input i_uart; |
output wire o_uart; |
// and it's associated control wires |
output wire o_uart_cts; |
input i_uart_rts; |
output wire o_uart_rts_n; |
input i_uart_cts_n; |
// Our keypad |
input [3:0] i_kp_row; |
output wire [3:0] o_kp_col; |
114,31 → 114,12
.PSEN(1'b0), |
.RST(1'b0)); |
|
// |
// The UART serial interface |
// |
// Perhaps this should be part of our simulation model as well. |
// For historical reasons, internal to Gisselquist Technology, |
// this has remained separate from the simulation, allowing the |
// simulation to bypass whether or not these two functions work. |
// |
wire rx_stb, tx_stb; |
wire [7:0] rx_data, tx_data; |
wire tx_busy; |
wire [29:0] uart_setup; |
// Baud rate is set by clock rate / baud rate desired. Thus, |
// 80 MHz / 9600 Baud = 8333, or about 0x208d. We choose a slow |
// speed such as 9600 Baud to help the CPU keep up with the serial |
// port rate. |
localparam [30:0] UART_SETUP = 31'h4000208d; |
|
wire reset_s; |
assign reset_s = 1'b0; |
|
wire rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, tx_break; |
assign tx_break = 1'b0; |
rxuart rcvuart(clk_s, 1'b0, uart_setup, |
i_uart, rx_stb, rx_data, |
rx_break, rx_parity_err, rx_frame_err, rx_ck_uart); |
txuart tcvuart(clk_s, reset_s, uart_setup, tx_break, tx_stb, tx_data, |
o_uart, tx_busy); |
|
|
// |
// BUSMASTER |
// |
152,9 → 133,11
wire [1:0] qspi_bmod; |
wire [15:0] w_gpio; |
|
busmaster masterbus(clk_s, 1'b0, |
// External ... bus control (if enabled) |
rx_stb, rx_data, tx_stb, tx_data, tx_busy, w_uart_cts, |
wire w_uart_rts_n; |
busmaster #(.UART_SETUP(UART_SETUP)) |
masterbus(clk_s, 1'b0, |
// Serial port wires |
i_uart, o_uart_rts_n, o_uart, i_uart_cts_n, |
// SPI/SD-card flash |
o_qspi_cs_n, o_qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod, |
// Board lights and switches |
161,12 → 144,9
i_btn, o_led, o_pwm, { o_pwm_shutdown_n, o_pwm_gain }, |
// Keypad connections |
i_kp_row, o_kp_col, |
// UART control |
uart_setup, |
// GPIO lines |
{ i_gpio, io_scl, io_sda }, w_gpio |
); |
assign o_uart_cts = (w_uart_cts)&&(i_uart_rts); |
|
// |
// Quad SPI support |
186,7 → 166,7
// Supporting I2C requires a couple quick adjustments to our |
// GPIO lines. Specifically, we'll allow that when the output |
// (i.e. w_gpio) pins are high, then the I2C lines float. They |
// will be (need to be) pulled up by a resistor in order to |
// will be (need to be) pulled up by a resistor in order to |
// match the I2C protocol, but this change makes them look/act |
// more like GPIO pins. |
// |
/rtl/txuart.v
2,7 → 2,7
// |
// Filename: txuart.v |
// |
// Project: CMod S6 System on a Chip, ZipCPU demonstration project |
// Project: wbuart32, a full featured UART with simulator |
// |
// Purpose: Transmit outputs over a single UART line. |
// |
21,9 → 21,16
// Now for the setup register. The register is 32 bits, so that this |
// UART may be set up over a 32-bit bus. |
// |
// i_setup[30] Set this to zero to use hardware flow control, and to |
// one to ignore hardware flow control. Only works if the hardware |
// flow control has been properly wired. |
// |
// If you don't want hardware flow control, fix the i_rts bit to |
// 1'b1, and let the synthesys tools optimize out the logic. |
// |
// i_setup[29:28] Indicates the number of data bits per word. This will |
// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10 |
// for a six bit word, or 2'b11 for a five bit word. |
// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10 |
// for a six bit word, or 2'b11 for a five bit word. |
// |
// i_setup[27] Indicates whether or not to use one or two stop bits. |
// Set this to one to expect two stop bits, zero for one. |
56,12 → 63,13
// 32'h0006c8 // For 115,200 baud, 8 bit, no parity |
// 32'h005161 // For 9600 baud, 8 bit, no parity |
// |
// Creator: Dan Gisselquist |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
74,7 → 82,7
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
85,7 → 93,6
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// |
`define TXU_BIT_ZERO 4'h0 |
`define TXU_BIT_ONE 4'h1 |
`define TXU_BIT_TWO 4'h2 |
104,77 → 111,95
`define TXU_IDLE 4'hf |
// |
// |
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data, o_uart, o_busy); |
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data, |
i_cts_n, o_uart_tx, o_busy); |
parameter [30:0] INITIAL_SETUP = 31'd868; |
input i_clk, i_reset; |
input [29:0] i_setup; |
input [30:0] i_setup; |
input i_break; |
input i_wr; |
input [7:0] i_data; |
output reg o_uart; |
// Hardware flow control Ready-To-Send bit. Set this to one to use |
// the core without flow control. (A more appropriate name would be |
// the Ready-To-Receive bit ...) |
input i_cts_n; |
// And the UART input line itself |
output reg o_uart_tx; |
// A line to tell others when we are ready to accept data. If |
// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte |
// for transmission. |
output wire o_busy; |
|
wire [27:0] clocks_per_baud, break_condition; |
wire [1:0] data_bits; |
wire use_parity, parity_even, dblstop, fixd_parity; |
reg [29:0] r_setup; |
wire use_parity, parity_even, dblstop, fixd_parity, |
fixdp_value, hw_flow_control; |
reg [30:0] r_setup; |
assign clocks_per_baud = { 4'h0, r_setup[23:0] }; |
assign break_condition = { r_setup[23:0], 4'h0 }; |
assign data_bits = r_setup[29:28]; |
assign dblstop = r_setup[27]; |
assign use_parity = r_setup[26]; |
assign fixd_parity = r_setup[25]; |
assign parity_even = r_setup[24]; |
assign hw_flow_control = !r_setup[30]; |
assign data_bits = r_setup[29:28]; |
assign dblstop = r_setup[27]; |
assign use_parity = r_setup[26]; |
assign fixd_parity = r_setup[25]; |
assign parity_even = r_setup[24]; |
assign fixdp_value = r_setup[24]; |
|
reg [27:0] baud_counter; |
reg [3:0] state; |
reg [7:0] lcl_data; |
reg calc_parity; |
reg r_busy; |
reg calc_parity, r_busy, zero_baud_counter; |
|
initial o_uart = 1'b1; |
|
// First step ... handle any hardware flow control, if so enabled. |
// |
// Clock in the flow control data, two clocks to avoid metastability |
// Default to using hardware flow control (uart_setup[30]==0 to use it). |
// Set this high order bit off if you do not wish to use it. |
reg q_cts_n, qq_cts_n, ck_cts; |
// While we might wish to give initial values to q_rts and ck_cts, |
// 1) it's not required since the transmitter starts in a long wait |
// state, and 2) doing so will prevent the synthesizer from optimizing |
// this pin in the case it is hard set to 1'b1 external to this |
// peripheral. |
// |
// initial q_cts_n = 1'b1; |
// initial qq_cts_n = 1'b1; |
// initial ck_cts = 1'b0; |
always @(posedge i_clk) |
q_cts_n <= i_cts_n; |
always @(posedge i_clk) |
qq_cts_n <= q_cts_n; |
always @(posedge i_clk) |
ck_cts <= (!qq_cts_n)||(!hw_flow_control); |
|
initial o_uart_tx = 1'b1; |
initial r_busy = 1'b1; |
initial state = `TXU_IDLE; |
initial lcl_data= 8'h0; |
initial calc_parity = 1'b0; |
initial baud_counter = clocks_per_baud; |
// initial baud_counter = clocks_per_baud; |
// initial baud_counter = clocks_per_baud;//ILLEGAL--not constant |
always @(posedge i_clk) |
begin |
if (i_reset) |
begin |
baud_counter <= clocks_per_baud; |
o_uart <= 1'b1; |
r_busy <= 1'b1; |
state <= `TXU_IDLE; |
lcl_data <= 8'h0; |
calc_parity <= 1'b0; |
end else if (i_break) |
begin |
baud_counter <= break_condition; |
o_uart <= 1'b0; |
state <= `TXU_BREAK; |
calc_parity <= 1'b0; |
r_busy <= 1'b1; |
end else if (baud_counter != 0) |
end else if (!zero_baud_counter) |
begin // r_busy needs to be set coming into here |
baud_counter <= baud_counter - 28'h01; |
r_busy <= 1'b1; |
end else if (state == `TXU_BREAK) |
begin |
state <= `TXU_IDLE; |
r_busy <= 1'b1; |
o_uart <= 1'b1; |
calc_parity <= 1'b0; |
// Give us two stop bits before becoming available |
baud_counter <= clocks_per_baud<<2; |
end else if (state == `TXU_IDLE) // STATE_IDLE |
begin |
// baud_counter <= 0; |
r_setup <= i_setup; |
calc_parity <= 1'b0; |
if ((i_wr)&&(~r_busy)) |
if ((i_wr)&&(!r_busy)) |
begin // Immediately start us off with a start bit |
o_uart <= 1'b0; |
r_busy <= 1'b1; |
case(data_bits) |
2'b00: state <= `TXU_BIT_ZERO; |
182,46 → 207,31
2'b10: state <= `TXU_BIT_TWO; |
2'b11: state <= `TXU_BIT_THREE; |
endcase |
lcl_data <= i_data; |
baud_counter <= clocks_per_baud-28'h01; |
end else begin // Stay in idle |
o_uart <= 1'b1; |
r_busy <= 0; |
// lcl_data is irrelevant |
// state <= state; |
r_busy <= !ck_cts; |
end |
end else begin |
// One clock tick in each of these states ... |
baud_counter <= clocks_per_baud - 28'h01; |
// baud_counter <= clocks_per_baud - 28'h01; |
r_busy <= 1'b1; |
if (state[3] == 0) // First 8 bits |
begin |
o_uart <= lcl_data[0]; |
calc_parity <= calc_parity ^ lcl_data[0]; |
if (state == `TXU_BIT_SEVEN) |
state <= (use_parity)?`TXU_PARITY:`TXU_STOP; |
else |
state <= state + 1; |
lcl_data <= { 1'b0, lcl_data[7:1] }; |
end else if (state == `TXU_PARITY) |
begin |
state <= `TXU_STOP; |
if (fixd_parity) |
o_uart <= parity_even; |
else |
o_uart <= calc_parity^((parity_even)? 1'b1:1'b0); |
end else if (state == `TXU_STOP) |
begin // two stop bit(s) |
o_uart <= 1'b1; |
if (dblstop) |
state <= `TXU_SECOND_STOP; |
else |
state <= `TXU_IDLE; |
calc_parity <= 1'b0; |
end else // `TXU_SECOND_STOP and default: |
begin |
state <= `TXU_IDLE; // Go back to idle |
o_uart <= 1'b1; |
// Still r_busy, since we need to wait |
// for the baud clock to finish counting |
// out this last bit. |
229,6 → 239,156
end |
end |
|
// o_busy |
// |
// This is a wire, designed to be true is we are ever busy above. |
// originally, this was going to be true if we were ever not in the |
// idle state. The logic has since become more complex, hence we have |
// a register dedicated to this and just copy out that registers value. |
assign o_busy = (r_busy); |
|
|
// r_setup |
// |
// Our setup register. Accept changes between any pair of transmitted |
// words. The register itself has many fields to it. These are |
// broken out up top, and indicate what 1) our baud rate is, 2) our |
// number of stop bits, 3) what type of parity we are using, and 4) |
// the size of our data word. |
initial r_setup = INITIAL_SETUP; |
always @(posedge i_clk) |
if (state == `TXU_IDLE) |
r_setup <= i_setup; |
|
// lcl_data |
// |
// This is our working copy of the i_data register which we use |
// when transmitting. It is only of interest during transmit, and is |
// allowed to be whatever at any other time. Hence, if r_busy isn't |
// true, we can always set it. On the one clock where r_busy isn't |
// true and i_wr is, we set it and r_busy is true thereafter. |
// Then, on any zero_baud_counter (i.e. change between baud intervals) |
// we simple logically shift the register right to grab the next bit. |
always @(posedge i_clk) |
if (!r_busy) |
lcl_data <= i_data; |
else if (zero_baud_counter) |
lcl_data <= { 1'b0, lcl_data[7:1] }; |
|
// o_uart_tx |
// |
// This is the final result/output desired of this core. It's all |
// centered about o_uart_tx. This is what finally needs to follow |
// the UART protocol. |
// |
// Ok, that said, our rules are: |
// 1'b0 on any break condition |
// 1'b0 on a start bit (IDLE, write, and not busy) |
// lcl_data[0] during any data transfer, but only at the baud |
// change |
// PARITY -- During the parity bit. This depends upon whether or |
// not the parity bit is fixed, then what it's fixed to, |
// or changing, and hence what it's calculated value is. |
// 1'b1 at all other times (stop bits, idle, etc) |
always @(posedge i_clk) |
if (i_reset) |
o_uart_tx <= 1'b1; |
else if ((i_break)||((i_wr)&&(!r_busy))) |
o_uart_tx <= 1'b0; |
else if (zero_baud_counter) |
casez(state) |
4'b0???: o_uart_tx <= lcl_data[0]; |
`TXU_PARITY: o_uart_tx <= calc_parity; |
default: o_uart_tx <= 1'b1; |
endcase |
|
|
// calc_parity |
// |
// Calculate the parity to be placed into the parity bit. If the |
// parity is fixed, then the parity bit is given by the fixed parity |
// value (r_setup[24]). Otherwise the parity is given by the GF2 |
// sum of all the data bits (plus one for even parity). |
always @(posedge i_clk) |
if (fixd_parity) |
calc_parity <= fixdp_value; |
else if (zero_baud_counter) |
begin |
if (state[3] == 0) // First 8 bits of msg |
calc_parity <= calc_parity ^ lcl_data[0]; |
else |
calc_parity <= parity_even; |
end else if (!r_busy) |
calc_parity <= parity_even; |
|
|
// All of the above logic is driven by the baud counter. Bits must last |
// clocks_per_baud in length, and this baud counter is what we use to |
// make certain of that. |
// |
// The basic logic is this: at the beginning of a bit interval, start |
// the baud counter and set it to count clocks_per_baud. When it gets |
// to zero, restart it. |
// |
// However, comparing a 28'bit number to zero can be rather complex-- |
// especially if we wish to do anything else on that same clock. For |
// that reason, we create "zero_baud_counter". zero_baud_counter is |
// nothing more than a flag that is true anytime baud_counter is zero. |
// It's true when the logic (above) needs to step to the next bit. |
// Simple enough? |
// |
// I wish we could stop there, but there are some other (ugly) |
// conditions to deal with that offer exceptions to this basic logic. |
// |
// 1. When the user has commanded a BREAK across the line, we need to |
// wait several baud intervals following the break before we start |
// transmitting, to give any receiver a chance to recognize that we are |
// out of the break condition, and to know that the next bit will be |
// a stop bit. |
// |
// 2. A reset is similar to a break condition--on both we wait several |
// baud intervals before allowing a start bit. |
// |
// 3. In the idle state, we stop our counter--so that upon a request |
// to transmit when idle we can start transmitting immediately, rather |
// than waiting for the end of the next (fictitious and arbitrary) baud |
// interval. |
// |
// When (i_wr)&&(!r_busy)&&(state == `TXU_IDLE) then we're not only in |
// the idle state, but we also just accepted a command to start writing |
// the next word. At this point, the baud counter needs to be reset |
// to the number of clocks per baud, and zero_baud_counter set to zero. |
// |
// The logic is a bit twisted here, in that it will only check for the |
// above condition when zero_baud_counter is false--so as to make |
// certain the STOP bit is complete. |
initial zero_baud_counter = 1'b0; |
initial baud_counter = 28'h05; |
always @(posedge i_clk) |
begin |
zero_baud_counter <= (baud_counter == 28'h01); |
if ((i_reset)||(i_break)) |
begin |
// Give ourselves 16 bauds before being ready |
baud_counter <= break_condition; |
zero_baud_counter <= 1'b0; |
end else if (!zero_baud_counter) |
baud_counter <= baud_counter - 28'h01; |
else if (state == `TXU_BREAK) |
// Give us four idle baud intervals before becoming |
// available |
baud_counter <= clocks_per_baud<<2; |
else if (state == `TXU_IDLE) |
begin |
baud_counter <= 28'h0; |
zero_baud_counter <= 1'b1; |
if ((i_wr)&&(!r_busy)) |
begin |
baud_counter <= clocks_per_baud - 28'h01; |
zero_baud_counter <= 1'b0; |
end |
end else |
baud_counter <= clocks_per_baud - 28'h01; |
end |
endmodule |
|
/rtl/wbgpio.v
63,7 → 63,7
|
// 9LUT's, 16 FF's |
always @(posedge i_clk) |
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)) |
if ((i_wb_stb)&&(i_wb_we)) |
o_gpio <= ((o_gpio)&(~i_wb_data[(NOUT+16-1):16])) |
|((i_wb_data[(NOUT-1):0])&(i_wb_data[(NOUT+16-1):16])); |
|
/rtl/wbpwmaudio.v
82,11 → 82,12
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
o_pwm, o_aux, o_int); |
parameter DEFAULT_RELOAD = 17'd1814, // about 44.1 kHz @ 80MHz |
//DEFAULT_RELOAD = 32'd2268,//about 44.1 kHz @ 100MHz |
parameter DEFAULT_RELOAD = 16'd1814, // about 44.1 kHz @ 80MHz |
//DEFAULT_RELOAD = 16'd2268,//about 44.1 kHz @ 100MHz |
NAUX=2, // Dev control values |
VARIABLE_RATE=0, |
TIMING_BITS=17; |
VARIABLE_RATE=0, |
TIMING_BITS=16; |
localparam [0:0] BITREVERSE=1; |
input i_clk; |
input i_wb_cyc, i_wb_stb, i_wb_we; |
input i_wb_addr; |
109,7 → 110,7
reg [(TIMING_BITS-1):0] r_reload_value; |
initial r_reload_value = DEFAULT_RELOAD; |
always @(posedge i_clk) // Data write |
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr)&&(i_wb_we)) |
if ((i_wb_stb)&&(i_wb_addr)&&(i_wb_we)) |
r_reload_value <= i_wb_data[(TIMING_BITS-1):0]; |
assign w_reload_value = r_reload_value; |
end else begin |
116,10 → 117,14
assign w_reload_value = DEFAULT_RELOAD; |
end endgenerate |
|
reg ztimer; |
reg [(TIMING_BITS-1):0] timer; |
initial timer = DEFAULT_RELOAD; |
initial ztimer= 1'b0; |
always @(posedge i_clk) |
if (timer == 0) |
ztimer <= (timer == { {(TIMING_BITS-1){1'b0}}, 1'b1 }); |
always @(posedge i_clk) |
if (ztimer) |
timer <= w_reload_value; |
else |
timer <= timer - {{(TIMING_BITS-1){1'b0}},1'b1}; |
126,7 → 131,7
|
reg [15:0] sample_out; |
always @(posedge i_clk) |
if (timer == 0) |
if (ztimer) |
sample_out <= next_sample; |
|
|
135,7 → 140,7
initial next_valid = 1'b1; |
initial next_sample = 16'h8000; |
always @(posedge i_clk) // Data write |
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we) |
if ((i_wb_stb)&&(i_wb_we) |
&&((~i_wb_addr)||(VARIABLE_RATE==0))) |
begin |
// Write with two's complement data, convert it |
144,7 → 149,7
next_valid <= 1'b1; |
if (i_wb_data[16]) |
o_aux <= i_wb_data[(NAUX+20-1):20]; |
end else if (timer == 0) |
end else if (ztimer) |
next_valid <= 1'b0; |
|
initial o_int = 1'b0; |
160,7 → 165,7
genvar k; |
generate for(k=0; k<16; k=k+1) |
begin : bit_reversal_loop |
assign br_counter[k] = pwm_counter[15-k]; |
assign br_counter[k] = (BITREVERSE)?pwm_counter[15-k]:pwm_counter[k]; |
end endgenerate |
|
always @(posedge i_clk) |
184,7 → 189,7
|
initial o_wb_ack = 1'b0; |
always @(posedge i_clk) |
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb); |
o_wb_ack <= (i_wb_stb); |
assign o_wb_stall = 1'b0; |
|
endmodule |
/rtl/wbqspiflash.v
1,8 → 1,8
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbspiflash.v |
// |
// Project: Wishbone Controlled Quad SPI Flash Controller |
// Project: CMod S6 System on a Chip, ZipCPU demonstration project |
// |
// Purpose: Access a Quad SPI flash via a WISHBONE interface. This |
// includes both read and write (and erase) commands to the SPI |
24,12 → 24,12
// (19 bits): Data (R/w, but expect writes to take a while) |
// |
// |
// Creator: Dan Gisselquist |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
42,7 → 42,7
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
50,8 → 50,9
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
`include "flashconfig.v" |
// |
`define WBQSPI_RESET 0 |
65,10 → 66,10
`define WBQSPI_READ_CMD 8 |
`define WBQSPI_READ_DATA 9 |
`define WBQSPI_WAIT_TIL_RDIDLE 10 |
`define WBQSPI_READ_ID_CMD 11 // |
`define WBQSPI_READ_ID 12 // |
`define WBQSPI_READ_STATUS 13 // |
`define WBQSPI_READ_CONFIG 14 // |
`define WBQSPI_READ_ID_CMD 11 |
`define WBQSPI_READ_ID 12 |
`define WBQSPI_READ_STATUS 13 |
`define WBQSPI_READ_CONFIG 14 |
`define WBQSPI_WAIT_TIL_IDLE 15 |
// |
// |
102,10 → 103,11
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat, |
o_interrupt); |
parameter ADDRESS_WIDTH=22; |
localparam AW = ADDRESS_WIDTH-2; |
input i_clk_100mhz; |
// Wishbone, inputs first |
input i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we; |
input [(ADDRESS_WIDTH-3):0] i_wb_addr; |
input [(AW-1):0] i_wb_addr; |
input [31:0] i_wb_data; |
// then outputs |
output reg o_wb_ack; |
150,13 → 152,13
reg [9:0] reset_counter; |
reg quad_mode_enabled; |
reg spif_cmd, spif_override; |
reg [(ADDRESS_WIDTH-3):0] spif_addr; |
reg [(AW-1):0] spif_addr; |
reg [31:0] spif_data; |
reg [5:0] state; |
reg spif_ctrl, spif_req; |
reg alt_cmd, alt_ctrl; |
wire [(ADDRESS_WIDTH-17):0] spif_sector; |
assign spif_sector = spif_addr[(ADDRESS_WIDTH-3):14]; |
assign spif_sector = spif_addr[(AW-1):14]; |
|
// assign o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg }; |
|
168,6 → 170,7
initial quad_mode_enabled = 1'b0; |
initial o_interrupt = 1'b0; |
initial spif_override = 1'b1; |
initial spif_ctrl = 1'b0; |
always @(posedge i_clk_100mhz) |
begin |
spif_override <= 1'b0; |
237,7 → 240,7
spi_spd <= 1'b0; |
spi_dir <= 1'b0; // Write (for now, 'cause of cmd) |
// Data register access |
if ((i_wb_data_stb)&&(i_wb_cyc)) |
if (i_wb_data_stb) |
begin |
|
if (i_wb_we) // Request to write a page |
280,13 → 283,13
begin |
spi_in <= { 8'heb, |
{(24-ADDRESS_WIDTH){1'b0}}, |
i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00 }; |
i_wb_addr[(AW-1):0], 2'b00 }; |
state <= `WBQSPI_QRD_ADDRESS; |
spi_len <= 2'b00; // single byte, cmd only |
end else begin |
spi_in <= { 8'h0b, |
{(24-ADDRESS_WIDTH){1'b0}}, |
i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00 }; |
i_wb_addr[(AW-1):0], 2'b00 }; |
state <= `WBQSPI_RD_DUMMY; |
spi_len <= 2'b11; // cmd+addr,32bits |
end |
299,7 → 302,7
o_wb_stall <= 1'b1; |
`endif |
end |
end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)&&(i_wb_we)) |
end else if ((i_wb_ctrl_stb)&&(i_wb_we)) |
begin |
`ifdef READ_ONLY |
o_wb_ack <= 1'b1; |
365,7 → 368,7
end |
endcase |
`endif |
end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)) // &&(~i_wb_we)) |
end else if (i_wb_ctrl_stb) // &&(~i_wb_we)) |
begin |
case(i_wb_addr[1:0]) |
2'b00: begin // Read local register |
441,15 → 444,15
spi_hold <= 1'b0; |
spi_spd<= 1'b1; |
spi_dir <= 1'b0; // Write (for now) |
if ((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we)) |
if ((i_wb_data_stb)&&(~i_wb_we)) |
begin // Continue our read ... send the new address / mode |
o_wb_stall <= 1'b1; |
spi_wr <= 1'b1; |
spi_len <= 2'b10; // Write address, but not mode byte |
spi_in <= { {(24-ADDRESS_WIDTH){1'b0}}, |
i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00, 8'ha0 }; |
i_wb_addr[(AW-1):0], 2'b00, 8'ha0 }; |
state <= `WBQSPI_QRD_DUMMY; |
end else if((i_wb_cyc)&&(i_wb_ctrl_stb)&&(~i_wb_we)&&(i_wb_addr[1:0] == 2'b00)) |
end else if((i_wb_ctrl_stb)&&(~i_wb_we)&&(i_wb_addr[1:0] == 2'b00)) |
begin |
// A local read that doesn't touch the device, so leave |
// the device in its current state |
461,7 → 464,7
quad_mode_enabled, |
{(29-ADDRESS_WIDTH){1'b0}}, |
erased_sector, 14'h000 }; |
end else if((i_wb_cyc)&&((i_wb_ctrl_stb)||(i_wb_data_stb))) |
end else if(((i_wb_ctrl_stb)||(i_wb_data_stb))) |
begin // Need to release the device from quad mode for all else |
o_wb_ack <= 1'b0; |
o_wb_stall <= 1'b1; |
659,7 → 662,7
|
spi_wr <= 1'b1; // Non-stop |
spi_in <= { {(24-ADDRESS_WIDTH){1'b0}}, |
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00, 8'ha0 }; |
spif_addr[(AW-1):0], 2'b00, 8'ha0 }; |
spi_len <= 2'b10; // Write address, not mode byte |
spi_spd <= 1'b1; |
spi_dir <= 1'b0; // Still writing |
701,7 → 704,7
end else if (state == `WBQSPI_READ_DATA) |
begin |
// Pipelined read support |
spi_wr <=((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1))); |
spi_wr <=((i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1))); |
spi_in <= 32'h00; |
spi_len <= 2'b11; |
// Don't adjust the speed here, it was set in the setup |
725,8 → 728,7
o_wb_ack <= spif_req; |
o_wb_stall <= (~spi_wr); |
// adjust endian-ness to match the PC |
o_wb_data <= { spi_out[7:0], spi_out[15:8], |
spi_out[23:16], spi_out[31:24] }; |
o_wb_data <= spi_out; |
state <= (spi_wr)?`WBQSPI_READ_DATA |
: ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE); |
spif_req <= spi_wr; |
915,13 → 917,13
begin |
spi_in <= { 8'heb, |
{(24-ADDRESS_WIDTH){1'b0}}, |
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 }; |
spif_addr[(AW-1):0], 2'b00 }; |
state <= `WBQSPI_QRD_ADDRESS; |
// spi_len <= 2'b00; // single byte, cmd only |
end else begin |
spi_in <= { 8'h0b, |
{(24-ADDRESS_WIDTH){1'b0}}, |
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 }; |
spif_addr[(AW-1):0], 2'b00 }; |
state <= `WBQSPI_RD_DUMMY; |
spi_len <= 2'b11; // Send cmd and addr |
end end |
971,7 → 973,7
spi_wr <= 1'b1; |
spi_in <= { 8'h02, |
{(24-ADDRESS_WIDTH){1'b0}}, |
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 }; |
spif_addr[(AW-1):0], 2'b00 }; |
spi_len <= 2'b11; |
spi_hold <= 1'b1; |
spi_spd <= 1'b0; |
989,7 → 991,7
spi_wr <= 1'b1; |
spi_in <= { 8'h32, |
{(24-ADDRESS_WIDTH){1'b0}}, |
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 }; |
spif_addr[(AW-1):0], 2'b00 }; |
spi_len <= 2'b11; |
spi_hold <= 1'b1; |
spi_spd <= 1'b0; |
1012,11 → 1014,7
o_wb_stall <= 1'b1; |
o_wb_ack <= 1'b0; |
spi_wr <= 1'b1; // write without waiting |
spi_in <= { |
spif_data[ 7: 0], |
spif_data[15: 8], |
spif_data[23:16], |
spif_data[31:24] }; |
spi_in <= spif_data; |
spi_len <= 2'b11; // Write 4 bytes |
spi_hold <= 1'b1; |
if (~spi_busy) |
1042,7 → 1040,7
// Do nothing here. |
end else if ((i_wb_data_stb)&&(i_wb_we) |
&&(i_wb_addr == (spif_addr+1)) |
&&(i_wb_addr[(ADDRESS_WIDTH-3):6]==spif_addr[(ADDRESS_WIDTH-3):6])) |
&&(i_wb_addr[(AW-1):6]==spif_addr[(AW-1):6])) |
begin |
spif_cmd <= 1'b1; |
spif_data <= i_wb_data; |
1115,7 → 1113,7
// together with setting our copy of the WIP bit |
write_in_progress <= 1'b1; |
// keeping track of which sector we just erased |
erased_sector <= spif_data[(ADDRESS_WIDTH-3):14]; |
erased_sector <= spif_data[(AW-1):14]; |
// and marking this erase sector as no longer dirty |
dirty_sector <= 1'b0; |
|
1133,11 → 1131,10
o_wb_ack <= 1'b0; |
spif_req <= (spif_req) && (i_wb_cyc); |
// When the port clears, we can head back to idle |
// No ack necessary, we ackd before getting |
// here. |
if ((~spi_busy)&&(~spi_wr)) |
begin |
o_wb_ack <= spif_req; |
state <= `WBQSPI_IDLE; |
end |
end else if (state == `WBQSPI_CLEAR_STATUS) |
begin // Issue a clear status command |
spi_wr <= 1'b1; |
/rtl/wbqspiflashp.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbspiflashp.v |
// |
11,9 → 11,9
// Creator: Dan Gisselquist |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
26,7 → 26,7
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
34,8 → 34,9
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
`define WBQSPI_RESET 0 |
`define WBQSPI_RESET_QUADMODE 1 |
`define WBQSPI_IDLE 2 |
84,10 → 85,11
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat, |
o_interrupt); |
parameter ADDRESS_WIDTH=22; |
localparam AW = ADDRESS_WIDTH-2; |
input i_clk_100mhz; |
// Wishbone, inputs first |
input i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we; |
input [(ADDRESS_WIDTH-3):0] i_wb_addr; |
input [(AW-1):0] i_wb_addr; |
input [31:0] i_wb_data; |
// then outputs |
output reg o_wb_ack; |
129,14 → 131,16
end |
|
reg [7:0] last_status; |
reg [9:0] reset_counter; |
reg quad_mode_enabled; |
reg spif_cmd, spif_override; |
reg [(ADDRESS_WIDTH-3):0] spif_addr; |
reg [(AW-1):0] spif_addr; |
reg [31:0] spif_data; |
reg [5:0] state; |
reg spif_ctrl, spif_req; |
reg alt_cmd, alt_ctrl; |
wire [(ADDRESS_WIDTH-17):0] spif_sector; |
assign spif_sector = spif_addr[(ADDRESS_WIDTH-3):14]; |
assign spif_sector = spif_addr[(AW-1):14]; |
|
// assign o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg }; |
|
147,9 → 151,13
initial spi_len = 2'b00; |
initial quad_mode_enabled = 1'b0; |
initial o_interrupt = 1'b0; |
initial spif_override = 1'b1; |
initial spif_ctrl = 1'b0; |
always @(posedge i_clk_100mhz) |
begin |
spif_override <= 1'b0; |
alt_cmd <= (reset_counter[9:8]==2'b10)?reset_counter[3]:1'b1; // Toggle CS_n |
alt_ctrl <= (reset_counter[9:8]==2'b10)?reset_counter[0]:1'b1; // Toggle clock too |
if (state == `WBQSPI_RESET) |
begin |
// From a reset, we should |
167,7 → 175,8
state <= `WBQSPI_RESET_QUADMODE; |
spif_req <= 1'b0; |
spif_override <= 1'b1; |
last_status <= 8'hfc; // |
last_status <= 8'h00; // |
reset_counter <= 10'h3fc; // |
// This guarantees that we aren't starting in quad |
// I/O mode, where the FPGA configuration scripts may |
// have left us. |
175,21 → 184,28
begin |
// Okay, so here's the problem: we don't know whether or not |
// the Xilinx loader started us up in Quad Read I/O idle mode. |
// So, thus we need to |
// So, thus we need to toggle the clock and CS_n, with fewer |
// clocks than are necessary to transmit a word. |
// |
// Not ready to handle the bus yet, so stall any requests |
o_wb_ack <= 1'b0; |
o_wb_stall <= 1'b1; |
|
// Do something ... |
if (last_status == 8'h00) |
if (reset_counter == 10'h00) |
begin |
spif_override <= 1'b0; |
state <= `WBQSPI_IDLE; |
|
// Find out if we can use Quad I/O mode ... |
state <= `WBQSPI_READ_CONFIG; |
spi_wr <= 1'b1; |
spi_len <= 2'b01; |
spi_in <= { 8'h35, 24'h00}; |
|
end else begin |
last_status <= last_status - 8'h1; |
reset_counter <= reset_counter - 10'h1; |
spif_override <= 1'b1; |
spif_cmd <= last_status[3]; // Toggle CS_n |
spif_ctrl <= last_status[0]; // Toggle clock too |
end |
end else if (state == `WBQSPI_IDLE) |
begin |
206,7 → 222,7
spi_spd <= 1'b0; |
spi_dir <= 1'b0; // Write (for now, 'cause of cmd) |
// Data register access |
if ((i_wb_data_stb)&&(i_wb_cyc)) |
if (i_wb_data_stb) |
begin |
|
if (i_wb_we) // Request to write a page |
249,13 → 265,13
begin |
spi_in <= { 8'heb, |
{(24-ADDRESS_WIDTH){1'b0}}, |
i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00 }; |
i_wb_addr[(AW-1):0], 2'b00 }; |
state <= `WBQSPI_QRD_ADDRESS; |
spi_len <= 2'b00; // single byte, cmd only |
end else begin |
spi_in <= { 8'h0b, |
{(24-ADDRESS_WIDTH){1'b0}}, |
i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00 }; |
i_wb_addr[(AW-1):0], 2'b00 }; |
state <= `WBQSPI_RD_DUMMY; |
spi_len <= 2'b11; // cmd+addr,32bits |
end |
268,7 → 284,7
o_wb_stall <= 1'b1; |
`endif |
end |
end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)&&(i_wb_we)) |
end else if ((i_wb_ctrl_stb)&&(i_wb_we)) |
begin |
`ifdef READ_ONLY |
o_wb_ack <= 1'b1; |
334,7 → 350,7
end |
endcase |
`endif |
end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)) // &&(~i_wb_we)) |
end else if (i_wb_ctrl_stb) // &&(~i_wb_we)) |
begin |
case(i_wb_addr[1:0]) |
2'b00: begin // Read local register |
410,15 → 426,15
spi_hold <= 1'b0; |
spi_spd<= 1'b1; |
spi_dir <= 1'b0; // Write (for now) |
if ((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we)) |
if ((i_wb_data_stb)&&(~i_wb_we)) |
begin // Continue our read ... send the new address / mode |
o_wb_stall <= 1'b1; |
spi_wr <= 1'b1; |
spi_len <= 2'b10; // Write address, but not mode byte |
spi_in <= { {(24-ADDRESS_WIDTH){1'b0}}, |
i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00, 8'ha0 }; |
i_wb_addr[(AW-1):0], 2'b00, 8'ha0 }; |
state <= `WBQSPI_QRD_DUMMY; |
end else if((i_wb_cyc)&&(i_wb_ctrl_stb)&&(~i_wb_we)&&(i_wb_addr[1:0] == 2'b00)) |
end else if((i_wb_ctrl_stb)&&(~i_wb_we)&&(i_wb_addr[1:0] == 2'b00)) |
begin |
// A local read that doesn't touch the device, so leave |
// the device in its current state |
430,7 → 446,7
quad_mode_enabled, |
{(29-ADDRESS_WIDTH){1'b0}}, |
erased_sector, 14'h000 }; |
end else if((i_wb_cyc)&&((i_wb_ctrl_stb)||(i_wb_data_stb))) |
end else if(((i_wb_ctrl_stb)||(i_wb_data_stb))) |
begin // Need to release the device from quad mode for all else |
o_wb_ack <= 1'b0; |
o_wb_stall <= 1'b1; |
628,7 → 644,7
|
spi_wr <= 1'b1; // Non-stop |
spi_in <= { {(24-ADDRESS_WIDTH){1'b0}}, |
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00, 8'ha0 }; |
spif_addr[(AW-1):0], 2'b00, 8'ha0 }; |
spi_len <= 2'b10; // Write address, not mode byte |
spi_spd <= 1'b1; |
spi_dir <= 1'b0; // Still writing |
670,7 → 686,7
end else if (state == `WBQSPI_READ_DATA) |
begin |
// Pipelined read support |
spi_wr <=((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1))); |
spi_wr <=((i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1))); |
spi_in <= 32'h00; |
spi_len <= 2'b11; |
// Don't adjust the speed here, it was set in the setup |
694,8 → 710,7
o_wb_ack <= spif_req; |
o_wb_stall <= (~spi_wr); |
// adjust endian-ness to match the PC |
o_wb_data <= { spi_out[7:0], spi_out[15:8], |
spi_out[23:16], spi_out[31:24] }; |
o_wb_data <= spi_out; |
state <= (spi_wr)?`WBQSPI_READ_DATA |
: ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE); |
spif_req <= spi_wr; |
884,13 → 899,13
begin |
spi_in <= { 8'heb, |
{(24-ADDRESS_WIDTH){1'b0}}, |
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 }; |
spif_addr[(AW-1):0], 2'b00 }; |
state <= `WBQSPI_QRD_ADDRESS; |
// spi_len <= 2'b00; // single byte, cmd only |
end else begin |
spi_in <= { 8'h0b, |
{(24-ADDRESS_WIDTH){1'b0}}, |
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 }; |
spif_addr[(AW-1):0], 2'b00 }; |
state <= `WBQSPI_RD_DUMMY; |
spi_len <= 2'b11; // Send cmd and addr |
end end |
940,7 → 955,7
spi_wr <= 1'b1; |
spi_in <= { 8'h02, |
{(24-ADDRESS_WIDTH){1'b0}}, |
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 }; |
spif_addr[(AW-1):0], 2'b00 }; |
spi_len <= 2'b11; |
spi_hold <= 1'b1; |
spi_spd <= 1'b0; |
958,7 → 973,7
spi_wr <= 1'b1; |
spi_in <= { 8'h32, |
{(24-ADDRESS_WIDTH){1'b0}}, |
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 }; |
spif_addr[(AW-1):0], 2'b00 }; |
spi_len <= 2'b11; |
spi_hold <= 1'b1; |
spi_spd <= 1'b0; |
981,11 → 996,7
o_wb_stall <= 1'b1; |
o_wb_ack <= 1'b0; |
spi_wr <= 1'b1; // write without waiting |
spi_in <= { |
spif_data[ 7: 0], |
spif_data[15: 8], |
spif_data[23:16], |
spif_data[31:24] }; |
spi_in <= spif_data; |
spi_len <= 2'b11; // Write 4 bytes |
spi_hold <= 1'b1; |
if (~spi_busy) |
1011,7 → 1022,7
// Do nothing here. |
end else if ((i_wb_data_stb)&&(i_wb_we) |
&&(i_wb_addr == (spif_addr+1)) |
&&(i_wb_addr[(ADDRESS_WIDTH-3):6]==spif_addr[(ADDRESS_WIDTH-3):6])) |
&&(i_wb_addr[(AW-1):6]==spif_addr[(AW-1):6])) |
begin |
spif_cmd <= 1'b1; |
spif_data <= i_wb_data; |
1084,7 → 1095,7
// together with setting our copy of the WIP bit |
write_in_progress <= 1'b1; |
// keeping track of which sector we just erased |
erased_sector <= spif_data[(ADDRESS_WIDTH-3):14]; |
erased_sector <= spif_data[(AW-1):14]; |
// and marking this erase sector as no longer dirty |
dirty_sector <= 1'b0; |
|
1102,11 → 1113,10
o_wb_ack <= 1'b0; |
spif_req <= (spif_req) && (i_wb_cyc); |
// When the port clears, we can head back to idle |
// No ack necessary, we ackd before getting |
// here. |
if ((~spi_busy)&&(~spi_wr)) |
begin |
o_wb_ack <= spif_req; |
state <= `WBQSPI_IDLE; |
end |
end else if (state == `WBQSPI_CLEAR_STATUS) |
begin // Issue a clear status command |
spi_wr <= 1'b1; |
1166,8 → 1176,8
end |
|
// Command and control during the reset sequence |
assign o_qspi_cs_n = (spif_override)?spif_cmd :w_qspi_cs_n; |
assign o_qspi_sck = (spif_override)?spif_ctrl:w_qspi_sck; |
assign o_qspi_mod = (spif_override)? 2'b01 :w_qspi_mod; |
assign o_qspi_dat = (spif_override)? 4'b00 :w_qspi_dat; |
assign o_qspi_cs_n = (spif_override)?alt_cmd :w_qspi_cs_n; |
assign o_qspi_sck = (spif_override)?alt_ctrl:w_qspi_sck; |
assign o_qspi_mod = (spif_override)? 2'b01 :w_qspi_mod; |
assign o_qspi_dat = (spif_override)? 4'b00 :w_qspi_dat; |
endmodule |
/rtl/wbscopc.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbscopc.v |
// |
61,9 → 61,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
76,7 → 76,7
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
84,7 → 84,7
// http://www.gnu.org/licenses/gpl.html |
// |
// |
///////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module wbscopc(i_clk, i_ce, i_trigger, i_data, |
113,7 → 113,7
// When is the full scope reset? Capture that reset bit from any |
// write. |
wire lcl_reset; |
assign lcl_reset = (i_wb_cyc)&&(i_wb_stb)&&(~i_wb_addr)&&(i_wb_we) |
assign lcl_reset = (i_wb_stb)&&(~i_wb_addr)&&(i_wb_we) |
&&(~i_wb_data[31]); |
|
// A big part of this scope is the 'address' of any particular |
/rtl/wbscope.v
1,22 → 1,21
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbscope.v |
// |
// Project: FPGA Library of Routines |
// Project: WBScope, a wishbone hosted scope |
// |
// Purpose: This is a generic/library routine for providing a bus accessed |
// 'scope' or (perhaps more appropriately) a bus accessed logic |
// analyzer. The general operation is such that this 'scope' can |
// record and report on any 32 bit value transiting through the |
// FPGA. Once started and reset, the scope records a copy of the |
// input data every time the clock ticks with the circuit enabled. |
// That is, it records these values up until the trigger. Once |
// the trigger goes high, the scope will record for bw_holdoff |
// more counts before stopping. Values may then be read from the |
// buffer, oldest to most recent. After reading, the scope may |
// then be reset for another run. |
// 'scope' or (perhaps more appropriately) a bus accessed logic analyzer. |
// The general operation is such that this 'scope' can record and report |
// on any 32 bit value transiting through the FPGA. Once started and |
// reset, the scope records a copy of the input data every time the clock |
// ticks with the circuit enabled. That is, it records these values up |
// until the trigger. Once the trigger goes high, the scope will record |
// for bw_holdoff more counts before stopping. Values may then be read |
// from the buffer, oldest to most recent. After reading, the scope may |
// then be reset for another run. |
// |
// In general, therefore, operation happens in this fashion: |
// In general, therefore, operation happens in this fashion: |
// 1. A reset is issued. |
// 2. Recording starts, in a circular buffer, and continues until |
// 3. The trigger line is asserted. |
58,9 → 57,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
73,7 → 72,7
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
81,12 → 80,16
// http://www.gnu.org/licenses/gpl.html |
// |
// |
///////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module wbscope(i_clk, i_ce, i_trigger, i_data, |
i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
o_interrupt); |
parameter LGMEM = 5'd10, BUSW = 32, SYNCHRONOUS=1; |
parameter LGMEM = 5'd10, BUSW = 32, SYNCHRONOUS=1, |
DEFAULT_HOLDOFF = ((1<<(LGMEM-1))-4), |
HOLDOFFBITS = 20; |
// The input signals that we wish to record |
input i_clk, i_ce, i_trigger; |
input [(BUSW-1):0] i_data; |
108,10 → 111,10
wire bw_reset_request, bw_manual_trigger, |
bw_disable_trigger, bw_reset_complete; |
reg [22:0] br_config; |
wire [19:0] bw_holdoff; |
initial br_config = ((1<<(LGMEM-1))-4); |
wire [(HOLDOFFBITS-1):0] bw_holdoff; |
initial br_config = DEFAULT_HOLDOFF; |
always @(posedge i_wb_clk) |
if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_addr)) |
if ((i_wb_stb)&&(~i_wb_addr)) |
begin |
if (i_wb_we) |
br_config <= { i_wb_data[31], |
123,7 → 126,7
assign bw_reset_request = (~br_config[22]); |
assign bw_manual_trigger = (br_config[21]); |
assign bw_disable_trigger = (br_config[20]); |
assign bw_holdoff = br_config[19:0]; |
assign bw_holdoff = br_config[(HOLDOFFBITS-1):0]; |
|
wire dw_reset, dw_manual_trigger, dw_disable_trigger; |
generate |
135,7 → 138,8
assign bw_reset_complete = bw_reset_request; |
end else begin |
reg r_reset_complete; |
reg [2:0] r_iflags, q_iflags; |
(* ASYNC_REG = "TRUE" *) reg [2:0] q_iflags; |
reg [2:0] r_iflags; |
|
// Resets are synchronous to the bus clock, not the data clock |
// so do a clock transfer here |
152,7 → 156,8
assign dw_manual_trigger = r_iflags[1]; |
assign dw_disable_trigger = r_iflags[0]; |
|
reg q_reset_complete, qq_reset_complete; |
(* ASYNC_REG = "TRUE" *) reg q_reset_complete; |
reg qq_reset_complete; |
// Pass an acknowledgement back from the data clock to the bus |
// clock that the reset has been accomplished |
initial q_reset_complete = 1'b0; |
189,24 → 194,34
// Determine when memory is full and capture is complete |
// |
// Writes take place on the data clock |
// The counter is unsigned |
(* ASYNC_REG="TRUE" *) reg [(HOLDOFFBITS-1):0] counter; |
reg less_than_holdoff; |
always @(posedge i_clk) |
if (dw_reset) |
less_than_holdoff <= 1'b1; |
else if (i_ce) |
less_than_holdoff <= (counter < bw_holdoff); |
|
reg dr_stopped; |
reg [19:0] counter; // This is unsigned |
initial dr_stopped = 1'b0; |
initial counter = 20'h0000; |
initial counter = 0; |
always @(posedge i_clk) |
if (dw_reset) |
begin |
counter <= 0; |
dr_stopped <= 1'b0; |
end else if ((i_ce)&&(dr_triggered)) |
else if ((i_ce)&&(dr_triggered)&&(~dr_stopped)) |
begin // MUST BE a < and not <=, so that we can keep this w/in |
// 20 bits. Else we'd need to add a bit to comparison |
// here. |
if (counter < bw_holdoff) |
counter <= counter + 20'h01; |
else |
dr_stopped <= 1'b1; |
counter <= counter + 1'b1; |
end |
always @(posedge i_clk) |
if ((~dr_triggered)||(dw_reset)) |
dr_stopped <= 1'b0; |
else if (i_ce) |
dr_stopped <= (counter+1'b1 >= bw_holdoff); |
else |
dr_stopped <= (counter >= bw_holdoff); |
|
// |
// Actually do our writes to memory. Record, via 'primed' when |
226,7 → 241,7
begin |
waddr <= 0; // upon reset. |
dr_primed <= 1'b0; |
end else if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff))) |
end else if ((i_ce)&&(!dr_stopped)) |
begin |
// mem[waddr] <= i_data; |
waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1}; |
233,7 → 248,7
dr_primed <= (dr_primed)||(&waddr); |
end |
always @(posedge i_clk) |
if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff))) |
if ((i_ce)&&(!dr_stopped)) |
mem[waddr] <= i_data; |
|
// |
252,7 → 267,8
// for many clocks. Swapping is thus easy--two flip flops to |
// protect against meta-stability and we're done. |
// |
reg [2:0] q_oflags, r_oflags; |
(* ASYNC_REG = "TRUE" *) reg [2:0] q_oflags; |
reg [2:0] r_oflags; |
initial q_oflags = 3'h0; |
initial r_oflags = 3'h0; |
always @(posedge i_wb_clk) |
274,7 → 290,7
reg br_wb_ack; |
initial br_wb_ack = 1'b0; |
wire bw_cyc_stb; |
assign bw_cyc_stb = ((i_wb_cyc)&&(i_wb_stb)); |
assign bw_cyc_stb = (i_wb_stb); |
always @(posedge i_wb_clk) |
begin |
if ((bw_reset_request) |
281,7 → 297,7
||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we))) |
raddr <= 0; |
else if ((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)&&(bw_stopped)) |
raddr <= raddr + {{(LGMEM-1){1'b0}},1'b1}; // Data read, when stopped |
raddr <= raddr + 1'b1; // Data read, when stopped |
|
if ((bw_cyc_stb)&&(~i_wb_we)) |
begin // Read from the bus |
299,6 → 315,12
(((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)) ? |
{{(LGMEM-1){1'b0}},1'b1} : { (LGMEM){1'b0}} )]; |
|
wire [19:0] full_holdoff; |
assign full_holdoff[(HOLDOFFBITS-1):0] = bw_holdoff; |
generate if (HOLDOFFBITS < 20) |
assign full_holdoff[19:(HOLDOFFBITS)] = 0; |
endgenerate |
|
wire [4:0] bw_lgmem; |
assign bw_lgmem = LGMEM; |
always @(posedge i_wb_clk) |
311,7 → 333,7
bw_disable_trigger, |
(raddr == {(LGMEM){1'b0}}), |
bw_lgmem, |
bw_holdoff }; |
full_holdoff }; |
else if (~bw_stopped) // read, prior to stopping |
o_wb_data <= i_data; |
else // if (i_wb_addr) // Read from FIFO memory |
/rtl/wbubus.v
13,7 → 13,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
26,7 → 26,7
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
39,237 → 39,240
// |
module wbubus(i_clk,i_rx_stb,i_rx_data,o_wb_cyc,o_wb_stb,o_wb_we,o_wb_addr, |
o_wb_data,i_wb_ack,i_wb_stall,i_wb_err,i_wb_data,i_interrupt,o_tx_stb,o_tx_data |
,i_tx_busy);parameter LGWATCHDOG=19;input i_clk;input i_rx_stb;input[7:0] |
i_rx_data;output wire o_wb_cyc,o_wb_stb,o_wb_we;output wire[31:0]o_wb_addr, |
,i_tx_busy,o_dbg);parameter LGWATCHDOG=12;input i_clk;input i_rx_stb;input[7:0 |
]i_rx_data;output wire o_wb_cyc,o_wb_stb,o_wb_we;output wire[31:0]o_wb_addr, |
o_wb_data;input i_wb_ack,i_wb_stall,i_wb_err;input[31:0]i_wb_data;input |
i_interrupt;output wire o_tx_stb;output wire[7:0]o_tx_data;input i_tx_busy;reg |
PhcDs;wire QhcDs;wire[35:0]RhcDs;ShcDs ThcDs(i_clk,i_rx_stb,i_rx_data,QhcDs, |
RhcDs);wire UhcDs,VhcDs,WhcDs,XhcDs;wire[35:0]YhcDs,ZhcDs; |
`ifdef aicDs |
assign VhcDs=QhcDs;assign YhcDs=RhcDs;assign XhcDs=1'd0; |
`else |
wire bicDs,cicDs;assign VhcDs=(~UhcDs)&&(bicDs);assign XhcDs=PhcDs;dicDs#(36,6 |
)eicDs(i_clk,XhcDs,QhcDs,RhcDs,VhcDs,YhcDs,bicDs,cicDs); |
`endif |
ficDs gicDs(i_clk,PhcDs,VhcDs,YhcDs,UhcDs,o_wb_cyc,o_wb_stb,o_wb_we,o_wb_addr |
,o_wb_data,i_wb_ack,i_wb_stall,i_wb_err,i_wb_data,WhcDs,ZhcDs);wire hicDs;iicDs |
jicDs(i_clk,XhcDs,WhcDs,ZhcDs,o_wb_cyc,i_interrupt,WhcDs,o_tx_stb,o_tx_data, |
i_tx_busy,hicDs);reg[(LGWATCHDOG-1):0]kicDs;initial PhcDs=1'd0;initial kicDs=0 |
;always@(posedge i_clk)if((~o_wb_cyc)||(i_wb_ack))begin kicDs<=0;PhcDs<=1'd0; |
end else if(&kicDs)begin PhcDs<=1'd1;kicDs<=0;end else begin kicDs<=kicDs+{{( |
LGWATCHDOG-1){1'd0}},1'd1};PhcDs<=1'd0;end endmodule |
|
module licDs(i_clk,micDs,nicDs,oicDs,picDs,qicDs,i_tx_busy,ricDs);input i_clk, |
micDs;input[6:0]nicDs;output reg oicDs;output reg[6:0]picDs;input qicDs;input |
i_tx_busy;output wire ricDs;reg sicDs,ticDs;initial sicDs=1'd1;initial ticDs= |
1'd1;always@(posedge i_clk)if((~i_tx_busy)&&(oicDs))sicDs<=(picDs[6]);always@( |
posedge i_clk)if((micDs)&&(~ricDs))ticDs<=(nicDs[6]);reg[6:0]uicDs;initial |
uicDs=7'd0;always@(posedge i_clk)if((~i_tx_busy)&&(oicDs))begin if(picDs[6]) |
uicDs<=0;else uicDs<=uicDs+7'd1;end reg vicDs;initial vicDs=1'd0;always@( |
posedge i_clk)vicDs<=(uicDs>7'd72);initial oicDs=1'd0;always@(posedge i_clk)if |
((micDs)&&(~ricDs))begin oicDs<=(vicDs)||(~nicDs[6]);picDs<=nicDs;end else if( |
~ricDs)begin oicDs<=(~i_tx_busy)&&(~qicDs)&&(~sicDs)&&(ticDs);picDs<=7'd64;end |
else if(~i_tx_busy)oicDs<=1'd0;reg wicDs;initial wicDs=1'd0;always@(posedge |
i_clk)wicDs<=(oicDs);assign ricDs=(wicDs)||(oicDs);endmodule |
|
module xicDs(i_clk,micDs,yicDs,oicDs,zicDs,AicDs);parameter BicDs=32,CicDs=36, |
DicDs=10;input i_clk,micDs;input[(CicDs-1):0]yicDs;output wire oicDs;output |
wire[(CicDs-1):0]zicDs;input AicDs;reg EicDs;reg[35:0]FicDs;wire[31:0]GicDs; |
assign GicDs=yicDs[31:0];always@(posedge i_clk)if((micDs)&&(~EicDs))begin if( |
yicDs[35:32]!=4'd2)begin FicDs<=yicDs;end else if(GicDs[31:6]==26'd0)FicDs<={ |
6'd12,GicDs[5:0],24'd0};else if(GicDs[31:12]==20'd0)FicDs<={6'd13,GicDs[11:0], |
18'd0};else if(GicDs[31:18]==14'd0)FicDs<={6'd14,GicDs[17:0],12'd0};else if( |
GicDs[31:24]==8'd0)FicDs<={6'd15,GicDs[23:0],6'd0};else begin FicDs<=yicDs;end |
end initial EicDs=1'd0;always@(posedge i_clk)if((micDs)&&(~EicDs))EicDs<=micDs |
;else if(~AicDs)EicDs<=1'd0;wire HicDs;assign HicDs=(EicDs)&&(~AicDs);reg IicDs |
;always@(posedge i_clk)IicDs<=EicDs;wire[35:0]JicDs;assign JicDs=FicDs;reg[( |
DicDs-1):0]KicDs;reg LicDs,MicDs;always@(posedge i_clk)if(HicDs)begin if(zicDs |
[35:33]==3'd1)KicDs<=0;else if(zicDs[35:33]==3'd7)KicDs<=KicDs+{{(DicDs-1){1'd0 |
}},1'd1};end always@(posedge i_clk)if((HicDs)&&(zicDs[35:33]==3'd1))MicDs<=1'd0 |
;else if(KicDs==10'd1023)MicDs<=1'd1;reg[31:0]NicDs[0:((1<<DicDs)-1)];always@( |
posedge i_clk)NicDs[KicDs]<={JicDs[32:31],JicDs[29:0]};reg[(DicDs-1):0]OicDs; |
wire[(DicDs-1):0]PicDs;assign PicDs=OicDs-{{(DicDs-1){1'd0}},1'd1};initial |
OicDs=0;always@(posedge i_clk)if((HicDs)||(~EicDs))OicDs<=KicDs+{(DicDs){1'd1} |
};else if((PicDs!=KicDs)&&(~QicDs)&&((~PicDs[DicDs-1])||(MicDs)))OicDs<=PicDs; |
reg[(BicDs-1):0]RicDs;reg[(DicDs-1):0]SicDs;always@(posedge i_clk)begin RicDs |
<=NicDs[OicDs];SicDs<=OicDs;end reg QicDs;reg[9:0]TicDs;always@(posedge i_clk) |
if((HicDs)||(~EicDs)||(~IicDs))QicDs<=1'd0;else if(~QicDs)begin QicDs<=(({1'd0 |
,SicDs}<{MicDs,KicDs}))&&(JicDs[35:33]==3'd7)&&(RicDs=={JicDs[32:31],JicDs[29:0 |
]});TicDs<=KicDs-SicDs;end wire[(DicDs-1):0]UicDs;wire[9:0]VicDs;wire[2:0]WicDs |
;assign UicDs=TicDs;assign WicDs=TicDs[2:0]-3'd2;assign VicDs=TicDs-10'd10; |
initial LicDs=1'd0;reg[(CicDs-1):0]XicDs;always@(posedge i_clk)begin if((~EicDs |
)||(~IicDs)||(HicDs))LicDs<=1'd0;else if(LicDs);else if((QicDs)&&(TicDs<10'd521 |
))begin if(TicDs==10'd1)XicDs[35:30]<={5'd3,JicDs[30]};else if(UicDs<10'd10) |
XicDs[35:30]<={2'd2,WicDs,JicDs[30]};else XicDs[35:24]<={2'd1,VicDs[8:6],JicDs |
[30],VicDs[5:0]};LicDs<=1'd1;end else XicDs<=JicDs;end assign oicDs=EicDs; |
assign zicDs=(LicDs)?(XicDs):(FicDs);endmodule |
|
module YicDs(i_clk,micDs,ZicDs,oicDs,ajcDs);input i_clk,micDs;input[35:0]ZicDs |
;output reg oicDs;output reg[35:0]ajcDs;wire bjcDs=(ZicDs[35:33]==3'd3);reg[7:0 |
]cjcDs;initial cjcDs=8'd0;always@(posedge i_clk)if((micDs)&&(bjcDs))cjcDs<= |
cjcDs+8'd1;reg[31:0]NicDs[0:255];always@(posedge i_clk)if(micDs)NicDs[cjcDs]<= |
{ZicDs[32:31],ZicDs[29:0]};reg[35:0]JicDs;always@(posedge i_clk)if(micDs)JicDs |
<=ZicDs;reg[7:0]djcDs;always@(posedge i_clk)djcDs=cjcDs-{JicDs[32:31],JicDs[29 |
:24]};reg[24:0]ejcDs;always@(posedge i_clk)case(JicDs[32:30])3'd0:ejcDs<={19'd0 |
,JicDs[29:24]};3'd2:ejcDs<={13'd0,JicDs[29:18]};3'd4:ejcDs<={7'd0,JicDs[29:12] |
};3'd6:ejcDs<={1'd0,JicDs[29:6]};3'd1:ejcDs<={{(19){JicDs[29]}},JicDs[29:24]}; |
3'd3:ejcDs<={{(13){JicDs[29]}},JicDs[29:18]};3'd5:ejcDs<={{(7){JicDs[29]}}, |
JicDs[29:12]};3'd7:ejcDs<={{(1){JicDs[29]}},JicDs[29:6]};endcase wire[31:0] |
GicDs;assign GicDs={{(7){ejcDs[24]}},ejcDs};reg[9:0]fjcDs;always@(posedge i_clk |
)if(~JicDs[34])fjcDs<=10'd1+{6'd0,JicDs[33:31]};else fjcDs<=10'd8+{1'd0,JicDs[ |
33:31],JicDs[29:24]};reg[31:0]RicDs;always@(posedge i_clk)RicDs<=NicDs[djcDs]; |
reg[2:0]IicDs;initial IicDs=0;always@(posedge i_clk)IicDs<={IicDs[1:0],micDs}; |
always@(posedge i_clk)oicDs<=IicDs[2];always@(posedge i_clk)if(JicDs[35:30]== |
6'd46)ajcDs<=JicDs;else casez(JicDs[35:30])6'b001??0:ajcDs<={4'd0,GicDs[31:0]} |
;6'b001??1:ajcDs<={3'd1,GicDs[31:30],1'd1,GicDs[29:0]};6'b010???:ajcDs<={3'd3, |
RicDs[31:30],JicDs[30],RicDs[29:0]};6'b10????:ajcDs<={5'd24,JicDs[30],20'd0, |
fjcDs};6'b11????:ajcDs<={5'd24,JicDs[30],20'd0,fjcDs};default:ajcDs<=JicDs; |
endcase endmodule |
|
module gjcDs(i_clk,micDs,ZicDs,i_tx_busy,oicDs,picDs,ricDs);input i_clk,micDs; |
input[35:0]ZicDs;input i_tx_busy;output reg oicDs;output reg[6:0]picDs;output |
reg ricDs;wire[2:0]hjcDs;assign hjcDs=(ZicDs[35:33]==3'd0)?3'd1:(ZicDs[35:32] |
==4'd2)?3'd6:(ZicDs[35:32]==4'd3)?(3'd2+{1'd0,ZicDs[31:30]}):(ZicDs[35:34]== |
2'd1)?3'd2:(ZicDs[35:34]==2'd2)?3'd1:3'd6;reg ijcDs;reg[2:0]jjcDs;reg[29:0] |
JicDs;initial oicDs=1'd0;initial ricDs=1'd0;initial ijcDs=1'd0;always@(posedge |
i_clk)if((micDs)&&(~ricDs))begin jjcDs<=hjcDs-3'd1;JicDs<=ZicDs[29:0];oicDs<= |
1'd1;picDs<={1'd0,ZicDs[35:30]};ricDs<=1'd1;ijcDs<=1'd1;end else if((oicDs)&&( |
i_tx_busy))begin ricDs<=1'd1;ijcDs<=1'd1;end else if(oicDs)oicDs<=1'd0;else if |
(jjcDs>0)begin oicDs<=1'd1;picDs<={1'd0,JicDs[29:24]};JicDs[29:6]<=JicDs[23:0] |
;jjcDs<=jjcDs-3'd1;ricDs<=1'd1;ijcDs<=1'd1;end else if(~picDs[6])begin oicDs<= |
1'd1;picDs<=7'd64;ricDs<=1'd1;ijcDs<=1'd1;end else begin ijcDs<=1'd0;ricDs<=( |
ijcDs);end endmodule |
|
module ficDs(i_clk,kjcDs,micDs,yicDs,ricDs,o_wb_cyc,o_wb_stb,o_wb_we,o_wb_addr |
,o_wb_data,i_wb_ack,i_wb_stall,i_wb_err,i_wb_data,oicDs,ljcDs);input i_clk, |
kjcDs;input micDs;input[35:0]yicDs;output reg ricDs;output reg o_wb_cyc, |
o_wb_stb,o_wb_we;output reg[31:0]o_wb_addr,o_wb_data;input i_wb_ack,i_wb_stall |
,i_wb_err;input[31:0]i_wb_data;output reg oicDs;output reg[35:0]ljcDs;wire |
mjcDs,njcDs,ojcDs,pjcDs;assign mjcDs=(micDs)&&(~ricDs);assign ojcDs=(mjcDs)&&( |
yicDs[35:34]==2'd1);assign njcDs=(mjcDs)&&(yicDs[35:30]==6'd46);wire[31:0]qjcDs |
;assign qjcDs={yicDs[32:31],yicDs[29:0]};assign pjcDs=((mjcDs)&&((yicDs[35:33] |
!=3'd3)||(~o_wb_we))&&(yicDs[35:30]!=6'd46));reg[9:0]rjcDs,jjcDs;reg sjcDs, |
tjcDs,ujcDs,vjcDs;initial tjcDs=1'd0;initial ujcDs=1'd1;always@(posedge i_clk) |
if(kjcDs)begin oicDs<=1'd1;ljcDs<={6'd3,30'd0};tjcDs<=1'd0;o_wb_cyc<=1'd0;end |
else if(o_wb_cyc)begin oicDs<=1'd0;if(tjcDs)begin if(njcDs)o_wb_cyc<=1'd0; |
o_wb_stb<=1'd0;end else if((i_wb_err)||(pjcDs))begin o_wb_cyc<=(~ricDs); |
o_wb_stb<=1'd0;tjcDs<=1'd1;oicDs<=1'd1;ljcDs<={6'd5,30'd0};end else if(( |
o_wb_stb)&&(~i_wb_stall))begin if(jjcDs!=0)jjcDs<=jjcDs-10'd1;else o_wb_stb<= |
1'd0;if(o_wb_we)begin oicDs<=1'd1;ljcDs<={6'd2,30'd0};end if(sjcDs)o_wb_addr<= |
o_wb_addr+32'd1;end else if(ojcDs)begin sjcDs<=yicDs[30];o_wb_data<=qjcDs; |
o_wb_stb<=1'd1;end if(njcDs)vjcDs<=1'd1;if((tjcDs)||(i_wb_err)||(pjcDs))ricDs |
<=1'd0;else if((njcDs)||(ojcDs)||(vjcDs))ricDs<=1'd1;else if((o_wb_we)&&( |
o_wb_stb)&&(~i_wb_stall)&&(jjcDs==0))ricDs<=1'd0;else if((o_wb_we)&&(~o_wb_stb |
))ricDs<=1'd0;if((tjcDs)||(i_wb_err))begin end else if(rjcDs!=10'd0)begin if(( |
i_wb_ack)&&(~o_wb_we))begin oicDs<=1'd1;ljcDs<={3'd7,i_wb_data[31:30],sjcDs, |
i_wb_data[29:0]};end if((i_wb_ack)&&(~ojcDs))rjcDs<=rjcDs-10'd1;else if((~ |
i_wb_ack)&&(ojcDs))rjcDs<=rjcDs+10'd1;end else if(rjcDs==10'd0)begin if((~ |
o_wb_we)||(vjcDs)||(njcDs))o_wb_cyc<=1'd0;else if(ojcDs)begin rjcDs<=rjcDs+ |
10'd1;o_wb_data<=qjcDs;end end end else if(micDs)begin oicDs<=1'd0;sjcDs<=yicDs |
[30];o_wb_we<=(~yicDs[35]);tjcDs<=1'd0;ricDs<=1'd0;vjcDs<=1'd0;if(yicDs[35:32] |
==4'd0)begin ujcDs<=1'd1;o_wb_addr<=yicDs[31:0];end else if(yicDs[35:33]==3'd1 |
)begin o_wb_addr<=o_wb_addr+{yicDs[32:31],yicDs[29:0]};ujcDs<=1'd1;end else if |
(yicDs[35:34]==2'd3)begin jjcDs<=yicDs[9:0]-10'd1;o_wb_cyc<=1'd1;o_wb_stb<=1'd1 |
;rjcDs<=yicDs[9:0];ricDs<=1'd1;if(ujcDs)begin oicDs<=1'd1;ljcDs<={4'd2, |
o_wb_addr};ujcDs<=1'd0;end end else if(~yicDs[35])begin o_wb_cyc<=1'd1;o_wb_stb |
<=1'd1;o_wb_data<=qjcDs;ricDs<=1'd1;jjcDs<=10'd0;ujcDs<=1'd1;rjcDs<=10'd1;end |
end else begin tjcDs<=1'd0;ricDs<=1'd0;oicDs<=1'd0;end endmodule |
|
module dicDs(i_clk,kjcDs,wjcDs,xjcDs,yjcDs,zjcDs,AjcDs,BjcDs);parameter CjcDs= |
66,DjcDs=10,EjcDs=(1<<DjcDs);input i_clk,kjcDs;input wjcDs;input[(CjcDs-1):0] |
xjcDs;input yjcDs;output reg[(CjcDs-1):0]zjcDs;output reg AjcDs;output wire |
BjcDs;reg[(CjcDs-1):0]FjcDs[0:(EjcDs-1)];reg[(DjcDs-1):0]GjcDs,HjcDs;initial |
GjcDs=0;always@(posedge i_clk)if(kjcDs)GjcDs<={(DjcDs){1'd0}};else if(wjcDs) |
begin if(GjcDs+1!=HjcDs)GjcDs<=GjcDs+{{(DjcDs-1){1'd0}},1'd1};end always@( |
posedge i_clk)if(wjcDs)FjcDs[GjcDs]<=xjcDs;initial HjcDs=0;always@(posedge |
i_clk)if(kjcDs)HjcDs<={(DjcDs){1'd0}};else if(yjcDs)begin if(GjcDs!=HjcDs)HjcDs |
<=HjcDs+{{(DjcDs-1){1'd0}},1'd1};end always@(posedge i_clk)zjcDs<=FjcDs[(yjcDs |
)?(HjcDs+{{(DjcDs-1){1'd0}},1'd1}):(HjcDs)];wire[(DjcDs-1):0]IjcDs;assign IjcDs |
=GjcDs+{{(DjcDs-1){1'd0}},1'd1};assign BjcDs=((wjcDs)&&(IjcDs==HjcDs))||((yjcDs |
)&&(GjcDs==HjcDs));wire[(DjcDs-1):0]JjcDs;assign JjcDs=HjcDs+{{(DjcDs-1){1'd0} |
},1'd1};always@(posedge i_clk)if(kjcDs)AjcDs<=1'd0;else AjcDs<=(~yjcDs)&&(GjcDs |
!=HjcDs)||(yjcDs)&&(GjcDs!=JjcDs);endmodule |
|
module KjcDs(i_clk,micDs,yicDs,LjcDs,AicDs,MjcDs,oicDs,ljcDs,ricDs,i_tx_busy); |
input i_clk;input micDs;input[35:0]yicDs;input LjcDs,AicDs,MjcDs;output reg |
oicDs;output reg[35:0]ljcDs;output reg ricDs;input i_tx_busy;reg NjcDs,OjcDs; |
initial NjcDs=1'd0;always@(posedge i_clk)if((oicDs)&&(~i_tx_busy)&&(ljcDs[35:30 |
]==6'd4))NjcDs<=MjcDs;else NjcDs<=(NjcDs)||(MjcDs);wire PjcDs;reg QjcDs;reg[35 |
:0]RjcDs;initial RjcDs=36'd0;always@(posedge i_clk)if((micDs)||(oicDs))RjcDs<= |
36'd0;else if(~RjcDs[35])RjcDs<=RjcDs+36'd43;initial QjcDs=1'd0;always@(posedge |
i_clk)if((oicDs)&&(~i_tx_busy)&&(ljcDs[35:31]==5'd0))QjcDs<=1'd1;else if(~RjcDs |
[35])QjcDs<=1'd0;assign PjcDs=(~QjcDs)&&(RjcDs[35]);initial oicDs=1'd0;initial |
ricDs=1'd0;always@(posedge i_clk)if((oicDs)&&(i_tx_busy))begin ricDs<=1'd1;end |
else if(oicDs)begin oicDs<=1'd0;ricDs<=1'd1;end else if(ricDs)ricDs<=1'd0;else |
if(micDs)begin ljcDs<=yicDs;oicDs<=1'd1;ricDs<=1'd1;end else if((NjcDs)&&(~ |
OjcDs))begin oicDs<=1'd1;ljcDs<={6'd4,30'd0};ricDs<=1'd1;end else if(PjcDs) |
begin oicDs<=1'd1;ricDs<=1'd1;if(LjcDs)ljcDs<={6'd1,30'd0};else ljcDs<={6'd0, |
30'd0};end initial OjcDs=1'd0;always@(posedge i_clk)if((NjcDs)&&((~oicDs)&&(~ |
ricDs)&&(~micDs)))OjcDs<=1'd1;else if(~MjcDs)OjcDs<=1'd0;endmodule |
|
module ShcDs(i_clk,micDs,SjcDs,oicDs,ljcDs);input i_clk,micDs;input[7:0]SjcDs; |
output wire oicDs;output wire[35:0]ljcDs;wire TjcDs,UjcDs;wire[5:0]VjcDs;WjcDs |
XjcDs(i_clk,micDs,SjcDs,TjcDs,UjcDs,VjcDs);wire YjcDs;wire[35:0]ZjcDs;akcDs |
bkcDs(i_clk,TjcDs,UjcDs,VjcDs,YjcDs,ZjcDs); |
`ifdef ckcDs |
assign oicDs=YjcDs;assign ljcDs=ZjcDs; |
`else |
YicDs dkcDs(i_clk,YjcDs,ZjcDs,oicDs,ljcDs); |
`endif |
endmodule |
|
module iicDs(i_clk,kjcDs,micDs,yicDs,ekcDs,MjcDs,qicDs,oicDs,fkcDs,i_tx_busy, |
gkcDs);input i_clk,kjcDs;input micDs;input[35:0]yicDs;input ekcDs,MjcDs,qicDs; |
output wire oicDs;output wire[7:0]fkcDs;input i_tx_busy;output wire gkcDs;wire |
hkcDs,ikcDs,jkcDs,kkcDs;wire[35:0]lkcDs;wire YjcDs,mkcDs,nkcDs,okcDs,pkcDs, |
qkcDs,rkcDs,skcDs;wire[35:0]tkcDs,ukcDs;wire[6:0]vkcDs,wkcDs; |
`ifdef xkcDs |
assign hkcDs=micDs;assign lkcDs=yicDs;assign kkcDs=1'd0; |
`else |
assign hkcDs=(jkcDs)&&(~mkcDs);dicDs#(36,10)ykcDs(i_clk,kjcDs,micDs,yicDs, |
hkcDs,lkcDs,jkcDs,kkcDs); |
`endif |
assign gkcDs=kkcDs;KjcDs zkcDs(i_clk,hkcDs,lkcDs,ekcDs,qicDs,MjcDs,YjcDs,tkcDs |
,mkcDs,rkcDs); |
`ifdef AkcDs |
assign nkcDs=YjcDs;assign ukcDs=tkcDs;assign rkcDs=ikcDs; |
`else |
assign rkcDs=nkcDs;xicDs BkcDs(i_clk,YjcDs,tkcDs,nkcDs,ukcDs,ikcDs); |
`endif |
gjcDs CkcDs(i_clk,nkcDs,ukcDs,qkcDs,okcDs,vkcDs,ikcDs);licDs DkcDs(i_clk,okcDs |
,vkcDs,pkcDs,wkcDs,(ekcDs||qicDs||jkcDs||mkcDs),skcDs,qkcDs);EkcDs FkcDs(i_clk |
,pkcDs,wkcDs,oicDs,fkcDs,skcDs,i_tx_busy);endmodule |
|
module akcDs(i_clk,micDs,GkcDs,HkcDs,oicDs,ljcDs);input i_clk,micDs,GkcDs;input |
[5:0]HkcDs;output reg oicDs;output reg[35:0]ljcDs;reg[2:0]jjcDs,IkcDs;wire |
JkcDs;assign JkcDs=((jjcDs==IkcDs)&&(IkcDs!=0))||((micDs)&&(~GkcDs)&&(KkcDs== |
2'd1));initial jjcDs=3'd0;always@(posedge i_clk)if((micDs)&&(~GkcDs))jjcDs<=0; |
else if(JkcDs)jjcDs<=(micDs)?3'd1:3'd0;else if(micDs)jjcDs<=jjcDs+3'd1;reg[35:0 |
]LkcDs;always@(posedge i_clk)if(JkcDs)LkcDs[35:30]<=HkcDs;else if(micDs)case( |
jjcDs)3'd0:LkcDs[35:30]<=HkcDs;3'd1:LkcDs[29:24]<=HkcDs;3'd2:LkcDs[23:18]<= |
HkcDs;3'd3:LkcDs[17:12]<=HkcDs;3'd4:LkcDs[11:6]<=HkcDs;3'd5:LkcDs[5:0]<=HkcDs; |
default:begin end endcase reg[1:0]KkcDs;always@(posedge i_clk)if(oicDs)KkcDs<= |
ljcDs[35:34];always@(posedge i_clk)if((micDs)&&(~GkcDs)&&(KkcDs==2'd1))ljcDs[35 |
:30]<=6'd46;else ljcDs<=LkcDs;initial IkcDs=3'd0;always@(posedge i_clk)if(( |
micDs)&&(~GkcDs))IkcDs<=0;else if((micDs)&&((IkcDs==0)||(JkcDs)))begin if(HkcDs |
[5:4]==2'd3)IkcDs<=3'd2;else if(HkcDs[5:4]==2'd2)IkcDs<=3'd1;else if(HkcDs[5:3 |
]==3'd2)IkcDs<=3'd2;else if(HkcDs[5:3]==3'd1)IkcDs<=3'd2+{1'd0,HkcDs[2:1]};else |
IkcDs<=3'd6;end else if(JkcDs)IkcDs<=0;always@(posedge i_clk)oicDs<=JkcDs; |
endmodule |
|
module EkcDs(i_clk,micDs,MkcDs,oicDs,fkcDs,ricDs,AicDs);input i_clk;input micDs |
;input[6:0]MkcDs;output reg oicDs;output reg[7:0]fkcDs;output wire ricDs;input |
AicDs;initial fkcDs=8'd0;always@(posedge i_clk)if((micDs)&&(~ricDs))begin if( |
MkcDs[6])fkcDs<=8'd10;else if(MkcDs[5:0]<=6'd9)fkcDs<=8'd48+{4'd0,MkcDs[3:0]}; |
else if(MkcDs[5:0]<=6'd35)fkcDs<=8'd65+{2'd0,MkcDs[5:0]}-8'd10;else if(MkcDs[5 |
:0]<=6'd61)fkcDs<=8'd97+{2'd0,MkcDs[5:0]}-8'd36;else if(MkcDs[5:0]==6'd62)fkcDs |
<=8'd64;else fkcDs<=8'd37;end always@(posedge i_clk)if((oicDs)&&(~AicDs))oicDs |
<=1'd0;else if((micDs)&&(~oicDs))oicDs<=1'd1;assign ricDs=oicDs;endmodule |
|
module WjcDs(i_clk,micDs,SjcDs,oicDs,NkcDs,OkcDs);input i_clk,micDs;input[7:0] |
SjcDs;output reg oicDs,NkcDs;output reg[5:0]OkcDs;always@(posedge i_clk)oicDs |
<=micDs;always@(posedge i_clk)begin NkcDs<=1'd1;OkcDs<=6'd0;if((SjcDs>=8'd48) |
&&(SjcDs<=8'd57))OkcDs<={2'd0,SjcDs[3:0]};else if((SjcDs>=8'd65)&&(SjcDs<=8'd90 |
))OkcDs<=(SjcDs[5:0]-6'd1+6'd10);else if((SjcDs>=8'd97)&&(SjcDs<=8'd122))OkcDs |
<=(SjcDs[5:0]+6'd3);else if(SjcDs==8'd64)OkcDs<=6'd62;else if(SjcDs==8'd37) |
OkcDs<=6'd63;else NkcDs<=1'd0;end endmodule |
i_interrupt;output wire o_tx_stb;output wire[7:0]o_tx_data;input i_tx_busy; |
output wire o_dbg;reg geVMD2;wire heVMD2;wire[35:0]ieVMD2;jeVMD2 keVMD2(i_clk, |
i_rx_stb,i_rx_data,heVMD2,ieVMD2);wire leVMD2,meVMD2,neVMD2,oeVMD2;wire[35:0] |
peVMD2,qeVMD2;wire reVMD2,seVMD2;assign meVMD2=(~leVMD2)&&(reVMD2);assign |
oeVMD2=geVMD2;teVMD2#(36,6)ueVMD2(i_clk,oeVMD2,heVMD2,ieVMD2,meVMD2,peVMD2, |
reVMD2,seVMD2);veVMD2 weVMD2(i_clk,geVMD2,meVMD2,peVMD2,leVMD2,o_wb_cyc, |
o_wb_stb,o_wb_we,o_wb_addr,o_wb_data,i_wb_ack,i_wb_stall,i_wb_err,i_wb_data, |
neVMD2,qeVMD2);wire xeVMD2;yeVMD2 zeVMD2(i_clk,oeVMD2,neVMD2,qeVMD2,o_wb_cyc, |
i_interrupt,neVMD2,o_tx_stb,o_tx_data,i_tx_busy,xeVMD2);reg[(LGWATCHDOG-1):0] |
AeVMD2;initial geVMD2=1'd0;initial AeVMD2=0;always@(posedge i_clk)if((~o_wb_cyc |
)||(i_wb_ack))begin AeVMD2<=0;geVMD2<=1'd0;end else if(&AeVMD2)begin geVMD2<= |
1'd1;AeVMD2<=0;end else begin AeVMD2<=AeVMD2+{{(LGWATCHDOG-1){1'd0}},1'd1}; |
geVMD2<=1'd0;end assign o_dbg=oeVMD2;endmodule module BeVMD2(i_clk,CeVMD2, |
DeVMD2,EeVMD2,FeVMD2);input i_clk,CeVMD2;input[35:0]DeVMD2;output reg EeVMD2; |
output reg[35:0]FeVMD2;wire GeVMD2=(DeVMD2[35:33]==3'd3);reg[7:0]HeVMD2;initial |
HeVMD2=8'd0;always@(posedge i_clk)if((CeVMD2)&&(GeVMD2))HeVMD2<=HeVMD2+8'd1;reg |
[31:0]IeVMD2[0:255];always@(posedge i_clk)if(CeVMD2)IeVMD2[HeVMD2]<={DeVMD2[32 |
:31],DeVMD2[29:0]};reg[35:0]JeVMD2;always@(posedge i_clk)if(CeVMD2)JeVMD2<= |
DeVMD2;reg[7:0]KeVMD2;always@(posedge i_clk)KeVMD2=HeVMD2-{JeVMD2[32:31],JeVMD2 |
[29:24]};reg[24:0]LeVMD2;always@(posedge i_clk)case(JeVMD2[32:30])3'd0:LeVMD2 |
<={19'd0,JeVMD2[29:24]};3'd2:LeVMD2<={13'd0,JeVMD2[29:18]};3'd4:LeVMD2<={7'd0, |
JeVMD2[29:12]};3'd6:LeVMD2<={1'd0,JeVMD2[29:6]};3'd1:LeVMD2<={{(19){JeVMD2[29] |
}},JeVMD2[29:24]};3'd3:LeVMD2<={{(13){JeVMD2[29]}},JeVMD2[29:18]};3'd5:LeVMD2 |
<={{(7){JeVMD2[29]}},JeVMD2[29:12]};3'd7:LeVMD2<={{(1){JeVMD2[29]}},JeVMD2[29:6 |
]};endcase wire[31:0]MeVMD2;assign MeVMD2={{(7){LeVMD2[24]}},LeVMD2};reg[9:0] |
NeVMD2;always@(posedge i_clk)if(~JeVMD2[34])NeVMD2<=10'd1+{6'd0,JeVMD2[33:31]} |
;else NeVMD2<=10'd9+{1'd0,JeVMD2[33:31],JeVMD2[29:24]};reg[31:0]OeVMD2;always@ |
(posedge i_clk)OeVMD2<=IeVMD2[KeVMD2];reg[2:0]PeVMD2;initial PeVMD2=0;always@( |
posedge i_clk)PeVMD2<={PeVMD2[1:0],CeVMD2};always@(posedge i_clk)EeVMD2<=PeVMD2 |
[2];always@(posedge i_clk)if(JeVMD2[35:30]==6'd46)FeVMD2<=JeVMD2;else casez( |
JeVMD2[35:30])6'b001??0:FeVMD2<={4'd0,MeVMD2[31:0]};6'b001??1:FeVMD2<={3'd1, |
MeVMD2[31:30],1'd1,MeVMD2[29:0]};6'b010???:FeVMD2<={3'd3,OeVMD2[31:30],JeVMD2[ |
30],OeVMD2[29:0]};6'b10????:FeVMD2<={5'd24,JeVMD2[30],20'd0,NeVMD2};6'b11????: |
FeVMD2<={5'd24,JeVMD2[30],20'd0,NeVMD2};default:FeVMD2<=JeVMD2;endcase |
endmodule module teVMD2(i_clk,QeVMD2,ReVMD2,SeVMD2,TeVMD2,UeVMD2,VeVMD2,WeVMD2 |
);parameter BW=66,LGFLEN=10;input i_clk,QeVMD2;input ReVMD2;input[(BW-1):0] |
SeVMD2;input TeVMD2;output reg[(BW-1):0]UeVMD2;output reg VeVMD2;output wire |
WeVMD2;localparam XeVMD2=(1<<LGFLEN);reg[(BW-1):0]YeVMD2[0:(XeVMD2-1)];reg[( |
LGFLEN-1):0]ZeVMD2,afVMD2;reg bfVMD2;initial bfVMD2=1'd0;always@(posedge i_clk |
)if(QeVMD2)bfVMD2<=1'd0;else if(TeVMD2)bfVMD2<=(bfVMD2)&&(ReVMD2);else if( |
ReVMD2)bfVMD2<=(ZeVMD2+2==afVMD2);else if(ZeVMD2+1==afVMD2)bfVMD2<=1'd1;initial |
ZeVMD2=0;always@(posedge i_clk)if(QeVMD2)ZeVMD2<={(LGFLEN){1'd0}};else if( |
ReVMD2)begin if((TeVMD2)||(~bfVMD2))ZeVMD2<=ZeVMD2+{{(LGFLEN-1){1'd0}},1'd1}; |
end always@(posedge i_clk)if(ReVMD2)YeVMD2[ZeVMD2]<=SeVMD2;reg cfVMD2;initial |
cfVMD2=1'd0;always@(posedge i_clk)if(QeVMD2)cfVMD2<=1'd0;else if(ReVMD2)cfVMD2 |
<=(cfVMD2)&&(TeVMD2);else if(TeVMD2)cfVMD2<=(afVMD2+1==ZeVMD2);else cfVMD2<=( |
afVMD2==ZeVMD2);initial afVMD2=0;always@(posedge i_clk)if(QeVMD2)afVMD2<={( |
LGFLEN){1'd0}};else if(TeVMD2)begin if((ReVMD2)||(~cfVMD2))afVMD2<=afVMD2+{{( |
LGFLEN-1){1'd0}},1'd1};end always@(posedge i_clk)UeVMD2<=YeVMD2[(TeVMD2)?( |
afVMD2+{{(LGFLEN-1){1'd0}},1'd1}):(afVMD2)];wire[(LGFLEN-1):0]dfVMD2;assign |
dfVMD2=ZeVMD2+{{(LGFLEN-1){1'd0}},1'd1};assign WeVMD2=((ReVMD2)&&(bfVMD2)&&(~ |
TeVMD2))||((TeVMD2)&&(cfVMD2)&&(~ReVMD2));wire[(LGFLEN-1):0]efVMD2;assign |
efVMD2=afVMD2+{{(LGFLEN-1){1'd0}},1'd1};always@(posedge i_clk)if(QeVMD2)VeVMD2 |
<=1'd0;else VeVMD2<=(~TeVMD2)&&(ZeVMD2!=afVMD2)||(TeVMD2)&&(ZeVMD2!=efVMD2); |
endmodule module yeVMD2(i_clk,QeVMD2,CeVMD2,ffVMD2,gfVMD2,hfVMD2,ifVMD2,EeVMD2 |
,jfVMD2,i_tx_busy,kfVMD2);input i_clk,QeVMD2;input CeVMD2;input[35:0]ffVMD2; |
input gfVMD2,hfVMD2,ifVMD2;output wire EeVMD2;output wire[7:0]jfVMD2;input |
i_tx_busy;output wire kfVMD2;wire lfVMD2,mfVMD2,nfVMD2,ofVMD2;wire[35:0]pfVMD2 |
;wire qfVMD2,rfVMD2,sfVMD2,tfVMD2,ufVMD2,vfVMD2,wfVMD2,xfVMD2;wire[35:0]yfVMD2 |
,zfVMD2;wire[6:0]AfVMD2,BfVMD2;assign lfVMD2=(nfVMD2)&&(~rfVMD2);teVMD2#(36,10 |
)CfVMD2(i_clk,QeVMD2,CeVMD2,ffVMD2,lfVMD2,pfVMD2,nfVMD2,ofVMD2);assign kfVMD2= |
ofVMD2;DfVMD2 EfVMD2(i_clk,lfVMD2,pfVMD2,gfVMD2,ifVMD2,hfVMD2,qfVMD2,yfVMD2, |
rfVMD2,wfVMD2);assign wfVMD2=sfVMD2;FfVMD2 GfVMD2(i_clk,qfVMD2,yfVMD2,sfVMD2, |
zfVMD2,mfVMD2);HfVMD2 IfVMD2(i_clk,sfVMD2,zfVMD2,vfVMD2,tfVMD2,AfVMD2,mfVMD2); |
JfVMD2 KfVMD2(i_clk,tfVMD2,AfVMD2,ufVMD2,BfVMD2,(gfVMD2||ifVMD2||nfVMD2||rfVMD2 |
),xfVMD2,vfVMD2);LfVMD2 MfVMD2(i_clk,ufVMD2,BfVMD2,EeVMD2,jfVMD2,xfVMD2, |
i_tx_busy);endmodule module NfVMD2(i_clk,CeVMD2,OfVMD2,EeVMD2,PfVMD2,QfVMD2); |
input i_clk,CeVMD2;input[7:0]OfVMD2;output reg EeVMD2,PfVMD2;output reg[5:0] |
QfVMD2;always@(posedge i_clk)EeVMD2<=CeVMD2;always@(posedge i_clk)begin PfVMD2 |
<=1'd1;QfVMD2<=6'd0;if((OfVMD2>=8'd48)&&(OfVMD2<=8'd57))QfVMD2<={2'd0,OfVMD2[3 |
:0]};else if((OfVMD2>=8'd65)&&(OfVMD2<=8'd90))QfVMD2<=(OfVMD2[5:0]-6'd1+6'd10) |
;else if((OfVMD2>=8'd97)&&(OfVMD2<=8'd122))QfVMD2<=(OfVMD2[5:0]+6'd3);else if( |
OfVMD2==8'd64)QfVMD2<=6'd62;else if(OfVMD2==8'd37)QfVMD2<=6'd63;else PfVMD2<= |
1'd0;end endmodule module JfVMD2(i_clk,CeVMD2,RfVMD2,EeVMD2,SfVMD2,ifVMD2, |
i_tx_busy,TfVMD2);input i_clk,CeVMD2;input[6:0]RfVMD2;output reg EeVMD2;output |
reg[6:0]SfVMD2;input ifVMD2;input i_tx_busy;output wire TfVMD2;reg UfVMD2, |
VfVMD2;initial UfVMD2=1'd1;initial VfVMD2=1'd1;always@(posedge i_clk)if((~ |
i_tx_busy)&&(EeVMD2))UfVMD2<=(SfVMD2[6]);always@(posedge i_clk)if((CeVMD2)&&(~ |
TfVMD2))VfVMD2<=(RfVMD2[6]);reg[6:0]WfVMD2;initial WfVMD2=7'd0;always@(posedge |
i_clk)if((~i_tx_busy)&&(EeVMD2))begin if(SfVMD2[6])WfVMD2<=0;else WfVMD2<= |
WfVMD2+7'd1;end reg XfVMD2;initial XfVMD2=1'd0;always@(posedge i_clk)XfVMD2<=( |
WfVMD2>7'd72);initial EeVMD2=1'd0;always@(posedge i_clk)if((CeVMD2)&&(~TfVMD2) |
)begin EeVMD2<=(XfVMD2)||(~RfVMD2[6]);SfVMD2<=RfVMD2;end else if(~TfVMD2)begin |
EeVMD2<=(~i_tx_busy)&&(~ifVMD2)&&(~UfVMD2)&&(VfVMD2);SfVMD2<=7'd64;end else if |
(~i_tx_busy)EeVMD2<=1'd0;reg YfVMD2;initial YfVMD2=1'd0;always@(posedge i_clk) |
YfVMD2<=(EeVMD2);assign TfVMD2=(YfVMD2)||(EeVMD2);endmodule module HfVMD2(i_clk |
,CeVMD2,DeVMD2,i_tx_busy,EeVMD2,SfVMD2,TfVMD2);input i_clk,CeVMD2;input[35:0] |
DeVMD2;input i_tx_busy;output reg EeVMD2;output reg[6:0]SfVMD2;output reg |
TfVMD2;wire[2:0]ZfVMD2;assign ZfVMD2=(DeVMD2[35:33]==3'd0)?3'd1:(DeVMD2[35:32] |
==4'd2)?3'd6:(DeVMD2[35:32]==4'd3)?(3'd2+{1'd0,DeVMD2[31:30]}):(DeVMD2[35:34] |
==2'd1)?3'd2:(DeVMD2[35:34]==2'd2)?3'd1:3'd6;reg agVMD2;reg[2:0]bgVMD2;reg[29:0 |
]JeVMD2;initial EeVMD2=1'd0;initial TfVMD2=1'd0;initial agVMD2=1'd0;always@( |
posedge i_clk)if((CeVMD2)&&(~TfVMD2))begin bgVMD2<=ZfVMD2-3'd1;JeVMD2<=DeVMD2[ |
29:0];EeVMD2<=1'd1;SfVMD2<={1'd0,DeVMD2[35:30]};TfVMD2<=1'd1;agVMD2<=1'd1;end |
else if((EeVMD2)&&(i_tx_busy))begin TfVMD2<=1'd1;agVMD2<=1'd1;end else if( |
EeVMD2)EeVMD2<=1'd0;else if(bgVMD2>0)begin EeVMD2<=1'd1;SfVMD2<={1'd0,JeVMD2[29 |
:24]};JeVMD2[29:6]<=JeVMD2[23:0];bgVMD2<=bgVMD2-3'd1;TfVMD2<=1'd1;agVMD2<=1'd1 |
;end else if(~SfVMD2[6])begin EeVMD2<=1'd1;SfVMD2<=7'd64;TfVMD2<=1'd1;agVMD2<= |
1'd1;end else begin agVMD2<=1'd0;TfVMD2<=(agVMD2);end endmodule module DfVMD2( |
i_clk,CeVMD2,ffVMD2,cgVMD2,dgVMD2,hfVMD2,EeVMD2,egVMD2,TfVMD2,i_tx_busy);input |
i_clk;input CeVMD2;input[35:0]ffVMD2;input cgVMD2,dgVMD2,hfVMD2;output reg |
EeVMD2;output reg[35:0]egVMD2;output reg TfVMD2;input i_tx_busy;reg fgVMD2, |
ggVMD2;initial fgVMD2=1'd0;always@(posedge i_clk)if((EeVMD2)&&(~i_tx_busy)&&( |
egVMD2[35:30]==6'd4))fgVMD2<=hfVMD2;else fgVMD2<=(fgVMD2)||(hfVMD2);wire hgVMD2 |
;reg igVMD2;reg[35:0]jgVMD2;initial jgVMD2=36'd0;always@(posedge i_clk)if(( |
CeVMD2)||(EeVMD2))jgVMD2<=36'd0;else if(~jgVMD2[35])jgVMD2<=jgVMD2+36'd43; |
initial igVMD2=1'd0;always@(posedge i_clk)if((EeVMD2)&&(~i_tx_busy)&&(egVMD2[35 |
:31]==5'd0))igVMD2<=1'd1;else if(~jgVMD2[35])igVMD2<=1'd0;assign hgVMD2=(~ |
igVMD2)&&(jgVMD2[35]);initial EeVMD2=1'd0;initial TfVMD2=1'd0;always@(posedge |
i_clk)if((EeVMD2)&&(i_tx_busy))begin TfVMD2<=1'd1;end else if(EeVMD2)begin |
EeVMD2<=1'd0;TfVMD2<=1'd1;end else if(TfVMD2)TfVMD2<=1'd0;else if(CeVMD2)begin |
egVMD2<=ffVMD2;EeVMD2<=1'd1;TfVMD2<=1'd1;end else if((fgVMD2)&&(~ggVMD2))begin |
EeVMD2<=1'd1;egVMD2<={6'd4,30'd0};TfVMD2<=1'd1;end else if(hgVMD2)begin EeVMD2 |
<=1'd1;TfVMD2<=1'd1;if(cgVMD2)egVMD2<={6'd1,30'd0};else egVMD2<={6'd0,30'd0}; |
end initial ggVMD2=1'd0;always@(posedge i_clk)if((fgVMD2)&&((~EeVMD2)&&(~TfVMD2 |
)&&(~CeVMD2)))ggVMD2<=1'd1;else if(~hfVMD2)ggVMD2<=1'd0;endmodule module kgVMD2 |
(i_clk,CeVMD2,lgVMD2,mgVMD2,EeVMD2,egVMD2);input i_clk,CeVMD2,lgVMD2;input[5:0 |
]mgVMD2;output reg EeVMD2;output reg[35:0]egVMD2;reg[2:0]bgVMD2,ngVMD2;reg[1:0 |
]ogVMD2;wire pgVMD2;assign pgVMD2=((bgVMD2==ngVMD2)&&(ngVMD2!=0))||((CeVMD2)&& |
(~lgVMD2)&&(ogVMD2==2'd1));initial bgVMD2=3'd0;always@(posedge i_clk)if((CeVMD2 |
)&&(~lgVMD2))bgVMD2<=0;else if(pgVMD2)bgVMD2<=(CeVMD2)?3'd1:3'd0;else if(CeVMD2 |
)bgVMD2<=bgVMD2+3'd1;reg[35:0]qgVMD2;always@(posedge i_clk)if(pgVMD2)qgVMD2[35 |
:30]<=mgVMD2;else if(CeVMD2)case(bgVMD2)3'd0:qgVMD2[35:30]<=mgVMD2;3'd1:qgVMD2 |
[29:24]<=mgVMD2;3'd2:qgVMD2[23:18]<=mgVMD2;3'd3:qgVMD2[17:12]<=mgVMD2;3'd4: |
qgVMD2[11:6]<=mgVMD2;3'd5:qgVMD2[5:0]<=mgVMD2;default:begin end endcase always |
@(posedge i_clk)if(EeVMD2)ogVMD2<=egVMD2[35:34];always@(posedge i_clk)if(( |
CeVMD2)&&(~lgVMD2)&&(ogVMD2==2'd1))egVMD2[35:30]<=6'd46;else egVMD2<=qgVMD2; |
initial ngVMD2=3'd0;always@(posedge i_clk)if((CeVMD2)&&(~lgVMD2))ngVMD2<=0;else |
if((CeVMD2)&&((ngVMD2==0)||(pgVMD2)))begin if(mgVMD2[5:4]==2'd3)ngVMD2<=3'd2; |
else if(mgVMD2[5:4]==2'd2)ngVMD2<=3'd1;else if(mgVMD2[5:3]==3'd2)ngVMD2<=3'd2; |
else if(mgVMD2[5:3]==3'd1)ngVMD2<=3'd2+{1'd0,mgVMD2[2:1]};else ngVMD2<=3'd6;end |
else if(pgVMD2)ngVMD2<=0;always@(posedge i_clk)EeVMD2<=pgVMD2;endmodule module |
FfVMD2(i_clk,CeVMD2,ffVMD2,EeVMD2,rgVMD2,dgVMD2);parameter DW=32,CW=36,TBITS=10 |
;input i_clk,CeVMD2;input[(CW-1):0]ffVMD2;output wire EeVMD2;output wire[(CW-1 |
):0]rgVMD2;input dgVMD2;reg sgVMD2;reg[35:0]tgVMD2;wire[31:0]MeVMD2;assign |
MeVMD2=ffVMD2[31:0];always@(posedge i_clk)if((CeVMD2)&&(~sgVMD2))begin if( |
ffVMD2[35:32]!=4'd2)begin tgVMD2<=ffVMD2;end else if(MeVMD2[31:6]==26'd0)tgVMD2 |
<={6'd12,MeVMD2[5:0],24'd0};else if(MeVMD2[31:12]==20'd0)tgVMD2<={6'd13,MeVMD2 |
[11:0],18'd0};else if(MeVMD2[31:18]==14'd0)tgVMD2<={6'd14,MeVMD2[17:0],12'd0}; |
else if(MeVMD2[31:24]==8'd0)tgVMD2<={6'd15,MeVMD2[23:0],6'd0};else begin tgVMD2 |
<=ffVMD2;end end initial sgVMD2=1'd0;always@(posedge i_clk)if((CeVMD2)&&(~ |
sgVMD2))sgVMD2<=CeVMD2;else if(~dgVMD2)sgVMD2<=1'd0;wire ugVMD2;assign ugVMD2= |
(sgVMD2)&&(~dgVMD2);reg PeVMD2;always@(posedge i_clk)PeVMD2<=sgVMD2;wire[35:0] |
JeVMD2;assign JeVMD2=tgVMD2;reg[(TBITS-1):0]vgVMD2;reg wgVMD2;always@(posedge |
i_clk)if(ugVMD2)begin if(rgVMD2[35:33]==3'd1)vgVMD2<=0;else if(rgVMD2[35:33]== |
3'd7)vgVMD2<=vgVMD2+{{(TBITS-1){1'd0}},1'd1};end always@(posedge i_clk)if(( |
ugVMD2)&&(rgVMD2[35:33]==3'd1))wgVMD2<=1'd0;else if(vgVMD2==10'd1023)wgVMD2<= |
1'd1;reg[31:0]IeVMD2[0:((1<<TBITS)-1)];always@(posedge i_clk)IeVMD2[vgVMD2]<={ |
JeVMD2[32:31],JeVMD2[29:0]};reg xgVMD2,ygVMD2;reg[(TBITS-1):0]zgVMD2;reg[(TBITS |
-1):0]AgVMD2;initial zgVMD2=0;initial xgVMD2=0;always@(posedge i_clk)begin |
ygVMD2<=((AgVMD2-vgVMD2)=={{(TBITS-1){1'd0}},1'd1});if((ugVMD2)||(~sgVMD2)) |
begin zgVMD2<=vgVMD2+{(TBITS){1'd1}};AgVMD2=vgVMD2+{{(TBITS-1){1'd1}},1'd0}; |
xgVMD2<=1'd0;end else if((~xgVMD2)&&(~BgVMD2)&&((~AgVMD2[TBITS-1])||(wgVMD2))) |
begin zgVMD2<=AgVMD2;AgVMD2=AgVMD2-{{(TBITS-1){1'd0}},1'd1};xgVMD2<=ygVMD2;end |
end reg[1:0]CgVMD2;reg DgVMD2,EgVMD2;reg[(DW-1):0]OeVMD2;reg[(TBITS-1):0]FgVMD2 |
,GgVMD2,HgVMD2;always@(posedge i_clk)begin OeVMD2<=IeVMD2[zgVMD2];FgVMD2<= |
zgVMD2;DgVMD2<=(OeVMD2=={JeVMD2[32:31],JeVMD2[29:0]});GgVMD2<=FgVMD2;HgVMD2<= |
vgVMD2-FgVMD2;EgVMD2<=({1'd0,FgVMD2}<{wgVMD2,vgVMD2})&&(FgVMD2!=vgVMD2);end |
always@(posedge i_clk)if((ugVMD2)||(~sgVMD2))CgVMD2<=0;else CgVMD2<={CgVMD2[0] |
,1'd1};reg BgVMD2;reg[(TBITS-1):0]IgVMD2;always@(posedge i_clk)if((ugVMD2)||(~ |
sgVMD2)||(~PeVMD2))BgVMD2<=1'd0;else if(~BgVMD2)begin BgVMD2<=(EgVMD2)&&(DgVMD2 |
)&&(JeVMD2[35:33]==3'd7)&&(CgVMD2==2'd3);end reg JgVMD2,KgVMD2,LgVMD2;always@( |
posedge i_clk)if(~BgVMD2)begin IgVMD2<=HgVMD2;LgVMD2<=(HgVMD2<10'd1313);JgVMD2 |
<=(HgVMD2==10'd1);KgVMD2<=(HgVMD2<10'd10);end wire[(TBITS-1):0]MgVMD2;wire[9:0 |
]NgVMD2;wire[2:0]OgVMD2;assign MgVMD2=IgVMD2;assign OgVMD2=IgVMD2[2:0]-3'd2; |
assign NgVMD2=IgVMD2-10'd10;reg[(CW-1):0]PgVMD2;always@(posedge i_clk)begin if |
((~sgVMD2)||(~PeVMD2)||(ugVMD2))begin PgVMD2<=JeVMD2;end else if((BgVMD2)&&( |
LgVMD2))begin PgVMD2<=JeVMD2;if(JgVMD2)PgVMD2[35:30]<={5'd3,JeVMD2[30]};else if |
(KgVMD2)PgVMD2[35:30]<={2'd2,OgVMD2,JeVMD2[30]};else PgVMD2[35:24]<={2'd1, |
NgVMD2[8:6],JeVMD2[30],NgVMD2[5:0]};end else PgVMD2<=JeVMD2;end assign EeVMD2= |
sgVMD2;assign rgVMD2=(PeVMD2)?(PgVMD2):(tgVMD2);endmodule module veVMD2(i_clk, |
QeVMD2,CeVMD2,ffVMD2,TfVMD2,o_wb_cyc,o_wb_stb,o_wb_we,o_wb_addr,o_wb_data, |
i_wb_ack,i_wb_stall,i_wb_err,i_wb_data,EeVMD2,egVMD2);input i_clk,QeVMD2;input |
CeVMD2;input[35:0]ffVMD2;output wire TfVMD2;output reg o_wb_cyc;output reg |
o_wb_stb;output reg o_wb_we;output reg[31:0]o_wb_addr,o_wb_data;input i_wb_ack |
,i_wb_stall,i_wb_err;input[31:0]i_wb_data;output reg EeVMD2;output reg[35:0] |
egVMD2;wire QgVMD2,RgVMD2,SgVMD2,TgVMD2;assign QgVMD2=(CeVMD2)&&(~TfVMD2); |
assign SgVMD2=(QgVMD2)&&(ffVMD2[35:34]==2'd1);assign RgVMD2=(QgVMD2)&&(ffVMD2[ |
35:30]==6'd46);wire[31:0]UgVMD2;assign UgVMD2={ffVMD2[32:31],ffVMD2[29:0]}; |
assign TgVMD2=((QgVMD2)&&(ffVMD2[35:33]!=3'd3)&&(ffVMD2[35:30]!=6'd46));reg[2:0 |
]VgVMD2;reg[9:0]WgVMD2,bgVMD2;reg XgVMD2,YgVMD2,ZgVMD2,ahVMD2,bhVMD2;reg chVMD2 |
;initial YgVMD2=1'd1;initial VgVMD2=3'd0;initial EeVMD2=1'd0;always@(posedge |
i_clk)if(QeVMD2)begin VgVMD2<=3'd0;EeVMD2<=1'd1;egVMD2<={6'd3,i_wb_data[29:0]} |
;o_wb_cyc<=1'd0;o_wb_stb<=1'd0;end else case(VgVMD2)3'd0:begin o_wb_cyc<=1'd0; |
o_wb_stb<=1'd0;EeVMD2<=1'd0;XgVMD2<=ffVMD2[30];o_wb_we<=(~ffVMD2[35]);egVMD2<= |
{4'd2,o_wb_addr};o_wb_we<=(ffVMD2[35:34]!=2'd3);o_wb_data<=UgVMD2;if(CeVMD2) |
begin casez(ffVMD2[35:32])4'd0:begin o_wb_addr<=ffVMD2[31:0];end 4'b001?:begin |
o_wb_addr<=o_wb_addr+{ffVMD2[32:31],ffVMD2[29:0]};end 4'b01??:begin VgVMD2<= |
3'd2;o_wb_cyc<=1'd1;o_wb_stb<=1'd1;end 4'b11??:begin if(YgVMD2)EeVMD2<=1'd1; |
VgVMD2<=3'd1;o_wb_cyc<=1'd1;o_wb_stb<=1'd1;end default:;endcase end end 3'd1: |
begin o_wb_cyc<=1'd1;o_wb_stb<=1'd1;if(i_wb_err)VgVMD2<=3'd0;EeVMD2<=(i_wb_err |
)||(i_wb_ack);if(i_wb_err)egVMD2<={6'd5,i_wb_data[29:0]};else egVMD2<={3'd7, |
i_wb_data[31:30],XgVMD2,i_wb_data[29:0]};if((XgVMD2)&&(~i_wb_stall))o_wb_addr |
<=o_wb_addr+32'd1;if(~i_wb_stall)begin if((chVMD2)||(ZgVMD2))begin VgVMD2<=3'd3 |
;o_wb_stb<=1'd0;end end end 3'd2:begin o_wb_cyc<=1'd1;o_wb_stb<=1'd1;if( |
i_wb_err)egVMD2<={6'd5,i_wb_data[29:0]};else egVMD2<={6'd2,i_wb_data[29:0]};if |
((XgVMD2)&&(~i_wb_stall))o_wb_addr<=o_wb_addr+32'd1;EeVMD2<=(i_wb_err)||(~ |
i_wb_stall);if(i_wb_err)begin VgVMD2<=3'd5;o_wb_cyc<=1'd0;o_wb_stb<=1'd0;end |
else if(~i_wb_stall)begin VgVMD2<=3'd4;o_wb_stb<=1'd0;end end 3'd3:begin |
o_wb_cyc<=1'd1;o_wb_stb<=1'd0;if(i_wb_err)egVMD2<={6'd5,i_wb_data[29:0]};else |
egVMD2<={3'd7,i_wb_data[31:30],XgVMD2,i_wb_data[29:0]};EeVMD2<=(((i_wb_ack)&&( |
~o_wb_we))||(i_wb_err));if(((ahVMD2)&&(i_wb_ack))||(bhVMD2)||(i_wb_err))begin |
o_wb_cyc<=1'd0;VgVMD2<=3'd0;end end 3'd4:begin egVMD2<={6'd5,i_wb_data[29:0]}; |
EeVMD2<=(i_wb_err)||(TgVMD2);o_wb_data<=UgVMD2;o_wb_cyc<=1'd1;o_wb_stb<=1'd0;if |
(TgVMD2)begin o_wb_cyc<=1'd0;VgVMD2<=3'd0;end else if(i_wb_err)begin o_wb_cyc |
<=1'd0;VgVMD2<=3'd5;end else if(SgVMD2)begin VgVMD2<=3'd2;o_wb_stb<=1'd1;end |
else if(RgVMD2)VgVMD2<=3'd3;end 3'd5:begin o_wb_cyc<=1'd0;o_wb_stb<=1'd0;egVMD2 |
<={6'd5,i_wb_data[29:0]};EeVMD2<=(TgVMD2);if((RgVMD2)||(TgVMD2))VgVMD2<=3'd0; |
end default:begin EeVMD2<=1'd1;egVMD2<={6'd3,i_wb_data[29:0]};VgVMD2<=3'd0; |
o_wb_cyc<=1'd0;o_wb_stb<=1'd0;end endcase assign TfVMD2=(VgVMD2!=3'd0)&&(VgVMD2 |
!=3'd4)&&(VgVMD2!=3'd5);always@(posedge i_clk)if(QeVMD2)YgVMD2<=1'd1;else if(( |
~o_wb_cyc)&&(CeVMD2)&&(~ffVMD2[35]))YgVMD2<=1'd1;else if(o_wb_cyc)YgVMD2<=1'd0 |
;always@(posedge i_clk)if(~o_wb_cyc)WgVMD2<=10'd0;else if((o_wb_stb)&&(~ |
i_wb_stall)&&(~i_wb_ack))WgVMD2<=WgVMD2+10'd1;else if(((~o_wb_stb)||(i_wb_stall |
))&&(i_wb_ack))WgVMD2<=WgVMD2-10'd1;always@(posedge i_clk)ahVMD2<=(~o_wb_stb) |
&&(WgVMD2==10'd1)||(o_wb_stb)&&(WgVMD2==10'd0);always@(posedge i_clk)bhVMD2<=( |
~o_wb_stb)&&(WgVMD2==10'd0);always@(posedge i_clk)if(~o_wb_stb)bgVMD2<=ffVMD2[9 |
:0];else if((o_wb_stb)&&(~i_wb_stall)&&(|bgVMD2))bgVMD2<=bgVMD2-10'd1;always@( |
posedge i_clk)begin chVMD2<=(~o_wb_cyc)&&(ffVMD2[9:0]==10'd1);ZgVMD2<=(o_wb_stb |
)&&(bgVMD2[9:2]==8'd0)&&((~bgVMD2[1])||((~bgVMD2[0])&&(~i_wb_stall)));end |
endmodule module jeVMD2(i_clk,CeVMD2,OfVMD2,EeVMD2,egVMD2);input i_clk,CeVMD2; |
input[7:0]OfVMD2;output wire EeVMD2;output wire[35:0]egVMD2;wire dhVMD2,ehVMD2 |
;wire[5:0]fhVMD2;NfVMD2 ghVMD2(i_clk,CeVMD2,OfVMD2,dhVMD2,ehVMD2,fhVMD2);wire |
qfVMD2;wire[35:0]hhVMD2;kgVMD2 ihVMD2(i_clk,dhVMD2,ehVMD2,fhVMD2,qfVMD2,hhVMD2 |
);BeVMD2 jhVMD2(i_clk,qfVMD2,hhVMD2,EeVMD2,egVMD2);endmodule module LfVMD2( |
i_clk,CeVMD2,khVMD2,EeVMD2,jfVMD2,TfVMD2,dgVMD2);input i_clk;input CeVMD2;input |
[6:0]khVMD2;output reg EeVMD2;output reg[7:0]jfVMD2;output wire TfVMD2;input |
dgVMD2;initial jfVMD2=8'd0;always@(posedge i_clk)if((CeVMD2)&&(~TfVMD2))begin |
if(khVMD2[6])jfVMD2<=8'd10;else if(khVMD2[5:0]<=6'd9)jfVMD2<=8'd48+{4'd0,khVMD2 |
[3:0]};else if(khVMD2[5:0]<=6'd35)jfVMD2<=8'd65+{2'd0,khVMD2[5:0]}-8'd10;else |
if(khVMD2[5:0]<=6'd61)jfVMD2<=8'd97+{2'd0,khVMD2[5:0]}-8'd36;else if(khVMD2[5:0 |
]==6'd62)jfVMD2<=8'd64;else jfVMD2<=8'd37;end always@(posedge i_clk)if((EeVMD2 |
)&&(~dgVMD2))EeVMD2<=1'd0;else if((CeVMD2)&&(~EeVMD2))EeVMD2<=1'd1;assign |
TfVMD2=EeVMD2;endmodule |