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URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

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    /s6soc/trunk
    from Rev 7 to Rev 8
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Rev 7 → Rev 8

/rtl/wbpwmaudio.v
120,7 → 120,7
initial timer = DEFAULT_RELOAD;
always @(posedge i_clk)
if (timer == 0)
timer <= {{(32-TIMING_BITS){1'b0}}, w_reload_value };
timer <= w_reload_value;
else
timer <= timer - {{(TIMING_BITS-1){1'b0}},1'b1};
 
/rtl/rtclight.v
53,8 → 53,8
// A once-per-day strobe on the last clock of the day
o_ppd);
parameter DEFAULT_SPEED = 32'd2814750,
IMPLEMENT_TIMER=1, IMPLEMENT_STOPWATCH=1,
CKBITS = 24; // 100 Mhz
CKBITS = 24, // 100 Mhz
IMPLEMENT_TIMER=1, IMPLEMENT_STOPWATCH=1;
input i_clk;
input i_wb_cyc, i_wb_stb, i_wb_we;
input [2:0] i_wb_addr;
412,9 → 412,17
// meaning that my verilator simulation is running about 300x slower
// than board time.
// initial ckspeed = 32'd786432000;
always @(posedge i_clk)
if ((sp_sel)&&(i_wb_we))
ckspeed <= i_wb_data;
generate
if (CKBITS < 32)
begin
always @(posedge i_clk)
if ((sp_sel)&&(i_wb_we))
ckspeed <= i_wb_data[(CKBITS-1):0];
end else begin
always @(posedge i_clk)
if ((sp_sel)&&(i_wb_we))
ckspeed <= i_wb_data;
end endgenerate
 
assign o_interrupt = tm_int || al_int;
 
423,6 → 431,14
// connecting this module to a year/month/date date/calendar module.
assign o_ppd = (ck_ppd)&&(ck_pps);
 
wire [31:0] w_ckspeed;
generate
if (CKBITS < 32)
assign w_ckspeed = { {(32-CKBITS){1'b0}}, ckspeed };
else
assign w_ckspeed = ckspeed;
endgenerate
 
always @(posedge i_clk)
case(i_wb_addr[2:0])
3'b000: o_data <= { 10'h0, ck_last_clock };
429,7 → 445,7
3'b001: o_data <= bus_timer_return;
3'b010: o_data <= bus_stopwatch_return;
3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };
3'b100: o_data <= ckspeed;
3'b100: o_data <= w_ckspeed;
default: o_data <= 32'h000;
endcase
 
/rtl/wbqspiflash.v
52,7 → 52,7
//
///////////////////////////////////////////////////////////////////////////
//
`include "flash_config.v"
`include "flashconfig.v"
//
`define WBQSPI_RESET 0
`define WBQSPI_RESET_QUADMODE 1
/rtl/cpu/ziptimer.v
121,7 → 121,7
initial o_int = 1'b0;
always @(posedge i_clk)
if (i_ce)
o_int<=(r_running)&&(r_value == {{(VW-1){1'b0}},1'b1 });
o_int <= (r_running)&&(r_value == { {(VW-1){1'b0}}, 1'b1 });
else
o_int <= 1'b0;
 
132,9 → 132,9
 
generate
if (VW < BW-1)
assign o_wb_data = { r_auto_reload, {(BW-1-VW){1'b0}}, r_value };
else
assign o_wb_data = { r_auto_reload, r_value };
else
assign o_wb_data = { r_auto_reload, {(BW-1-VW){1'b0}}, r_value };
endgenerate
 
endmodule
/rtl/wbdeppsimple.v
0,0 → 1,155
////////////////////////////////////////////////////////////////////////////////
//
// Filename: wbdeppsimple.v
//
// Project: CMod S6 System on a Chip, ZipCPU demonstration project
//
// Purpose: This is a very simple DEPP to Wishbone driver. It cannot handle
// pipeline reads or writes, it cannot compress anything being
// transmitted, however it can read/write a 32-bit wishbone bus with a
// proper software driver.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
module wbdeppsimple(i_clk,
i_astb_n, i_dstb_n, i_write_n,i_depp, o_depp, o_wait,
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_int);
input i_clk;
// DEPP interface
input i_astb_n, i_dstb_n, i_write_n;
input [7:0] i_depp;
output reg [7:0] o_depp;
output wire o_wait;
// Wishbone master interface
output reg o_wb_cyc, o_wb_stb, o_wb_we;
output reg [31:0] o_wb_addr, o_wb_data;
input i_wb_ack, i_wb_stall, i_wb_err;
input [31:0] i_wb_data;
input i_int;
 
// Synchronize the incoming signals
reg x_dstb_n, x_astb_n, x_write_n,
r_dstb_n, r_astb_n, r_write_n,
l_dstb_n, l_astb_n;
reg [7:0] x_depp, r_depp;
initial x_dstb_n = 1'b1;
initial r_dstb_n = 1'b1;
initial l_dstb_n = 1'b1;
initial x_astb_n = 1'b1;
initial r_astb_n = 1'b1;
initial l_astb_n = 1'b1;
always @(posedge i_clk)
begin
{ x_dstb_n, x_astb_n, x_write_n, x_depp }
<= { i_dstb_n, i_astb_n, i_write_n, i_depp };
{ r_dstb_n, r_astb_n, r_write_n, r_depp }
<= { x_dstb_n, x_astb_n, x_write_n, x_depp };
{ l_dstb_n, l_astb_n } <= { r_dstb_n, r_astb_n };
end
 
wire w_wait;
assign w_wait = ~(&{x_dstb_n, x_astb_n,
r_dstb_n, r_astb_n,
l_dstb_n, l_astb_n});
 
reg [7:0] addr;
reg [31:0] r_data;
 
wire astb, dstb, w_write;
assign astb = (~r_astb_n)&&(l_astb_n);
assign dstb = (~r_dstb_n)&&(l_dstb_n);
assign w_write= (~r_write_n);
 
initial o_wb_cyc = 1'b0;
initial o_wb_stb = 1'b0;
initial addr = 8'h00;
always @(posedge i_clk)
begin
if ((w_write)&&(astb))
addr <= r_depp;
 
if ((w_write)&&(dstb)&&(addr[7:3]==5'h00))
begin
case(addr[2:0])
//
3'b000: o_wb_addr[31:24] <= r_depp;
3'b001: o_wb_addr[23:16] <= r_depp;
3'b010: o_wb_addr[15: 8] <= r_depp;
3'b011: o_wb_addr[ 7: 0] <= r_depp;
//
3'b100: o_wb_data[31:24] <= r_depp;
3'b101: o_wb_data[23:16] <= r_depp;
3'b110: o_wb_data[15: 8] <= r_depp;
3'b111: o_wb_data[ 7: 0] <= r_depp;
//
endcase
end
if ((o_wb_cyc)&&(i_wb_ack)&&(~o_wb_we))
r_data <= i_wb_data;
 
// Direct BUS control
if ((w_write)&&(dstb)&&(|addr[7:3]))
begin
o_wb_cyc <= r_depp[0];
o_wb_stb <= r_depp[0];
o_wb_we <= r_depp[1];
end else begin
o_wb_stb <= 1'b0;
if ((o_wb_cyc)&&(i_wb_ack))
o_wb_cyc <= 1'b0;
end
end
 
assign o_wait = (w_wait);
 
reg r_int, r_err;
initial r_int = 1'b0;
initial r_err = 1'b0;
always @(posedge i_clk)
begin
if (addr[4])
o_depp <= { 5'h0, o_wb_cyc, r_int, r_err };
else case(addr[2:0])
3'b000: o_depp <= o_wb_addr[31:24];
3'b001: o_depp <= o_wb_addr[23:16];
3'b010: o_depp <= o_wb_addr[15: 8];
3'b011: o_depp <= o_wb_addr[ 7: 0];
3'b100: o_depp <= r_data[31:24];
3'b101: o_depp <= r_data[23:16];
3'b110: o_depp <= r_data[15: 8];
3'b111: o_depp <= r_data[ 7: 0];
endcase
 
r_int <= (i_int) ||((r_int)&&((~dstb)||(w_write)||(~addr[4])));
r_err <= (i_wb_err)||((r_err)&&((~dstb)||(w_write)||(~addr[4])));
end
 
endmodule
/rtl/builddate.v
1,0 → 1,155
`define DATESTAMP 32'h20160422
`define DATESTAMP 32'h20160423
/rtl/alttop.v
49,7 → 49,10
i_uart, o_uart, i_uart_cts, o_uart_rts,
i_kp_row, o_kp_col,
i_gpio, o_gpio,
io_scl, io_sda);
io_scl, io_sda,
i_depp_astb_n, i_depp_dstb_n, i_depp_write_n, io_depp_data,
o_depp_wait
);
input i_clk_8mhz;
//
// Quad SPI Flash
76,6 → 79,10
output wire [15:2] o_gpio;
// and our I2C port
inout io_scl, io_sda;
// Finally, the DEPP interface ... if so enabled
input i_depp_astb_n, i_depp_dstb_n, i_depp_write_n;
inout [7:0] io_depp_data;
output wire o_depp_wait;
 
//
// Clock management
107,22 → 114,6
.RST(1'b0));
 
//
// Generate active-high reset.
//
// Actually, we don't. Instead, let this board reset through
// the reconfiguration/power on process and we never use this
// wire.
//
/*
reg r_reset;
initial r_reset = 1'b1;
always @(posedge i_clk_12mhz)
r_reset <= 1'b0;
*/
assign reset_s = 1'b0;
 
 
//
// The UART serial interface
//
// Perhaps this should be part of our simulation model as well.
137,7 → 128,7
 
wire rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, tx_break;
assign tx_break = 1'b0;
rxuart rcvuart(clk_s, reset_s, uart_setup,
rxuart rcvuart(clk_s, 1'b0, uart_setup,
i_uart, rx_stb, rx_data,
rx_break, rx_parity_err, rx_frame_err, rx_ck_uart);
txuart tcvuart(clk_s, reset_s, uart_setup, tx_break, tx_stb, tx_data,
159,9 → 150,15
wire [3:0] qspi_dat;
wire [1:0] qspi_bmod;
wire [15:0] w_gpio;
wire [7:0] w_depp_data;
 
`ifndef BYPASS_LOGIC
altbusmaster slavedbus(clk_s, reset_s,
// External ... bus control (if enabled)
// DEPP I/O Control
i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
io_depp_data, w_depp_data, o_depp_wait,
// External UART interface
rx_stb, rx_data, tx_stb, tx_data, tx_busy, o_uart_rts,
// SPI/SD-card flash
o_qspi_cs_n, o_qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod,
187,6 → 184,34
assign io_qspi_dat = (~qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
:((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
 
`else
reg [26:0] r_counter;
always @(posedge clk_s)
r_counter <= r_counter+1;
assign o_led[0] = r_counter[26];
assign o_led[1] = r_counter[25];
assign o_led[2] = r_counter[24];
assign o_led[3] = r_counter[23];
// assign o_led[0] = 1'b1;
// assign o_led[1] = 1'b0;
// assign o_led[2] = 1'b1;
// assign o_led[3] = 1'b0;
 
assign w_gpio = 16'h3;
assign o_pwm = 1'b0;
assign o_pwm_shutdown_n = 1'b0;
assign o_pwm_gain = 1'b0;
 
assign o_depp_wait = (~i_depp_astb_n);
assign w_depp_data = 8'h00;
assign io_qspi_dat = 4'bzzzz;
assign o_qspi_cs_n = 1'b1;
assign o_qspi_sck = 1'b1;
 
assign uart_setup = 30'h080002b6;
 
assign o_uart_rts = 1'b1;
`endif
//
// I2C support
//
201,4 → 226,9
assign io_scl = (w_gpio[1]) ? 1'bz : 1'b0;
assign o_gpio[15:2] = w_gpio[15:2];
 
//
// DEPP return data support
//
assign io_depp_data = (~i_depp_write_n)? 8'bzzzz_zzzz : w_depp_data;
 
endmodule
/rtl/busmaster.v
59,11 → 59,10
o_uart_setup,
// GPIO lines
i_gpio, o_gpio);
parameter ZIP_ADDRESS_WIDTH=23, ZA=ZIP_ADDRESS_WIDTH,
parameter BUS_ADDRESS_WIDTH=23, ZIP_ADDRESS_WIDTH=BUS_ADDRESS_WIDTH,
CMOD_ZIPCPU_RESET_ADDRESS=23'h400100,
BUS_ADDRESS_WIDTH=23, BAW=23; // 24bits->2,258,23b->2181
ZA=ZIP_ADDRESS_WIDTH, BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
input i_clk, i_rst;
// The bus commander, via an external JTAG port
input i_rx_stb;
input [7:0] i_rx_data;
output reg o_tx_stb;
260,7 → 259,7
&&(wb_addr[3:0]==4'h0)&&(wb_we),
wb_data, pic_data, int_vector, w_interrupt);
 
initial bus_err_addr = `DATESTAMP;
initial bus_err_addr = 0; // `DATESTAMP;
always @(posedge i_clk)
if (wb_err)
bus_err_addr <= wb_addr;
290,7 → 289,7
assign rtc_ack = r_rtc_ack;
 
rtclight
#(32'h35afe5,23,0,0) // 80 MHz clock
#(23'h35afe5,23,0,0) // 80 MHz clock
thetime(i_clk, wb_cyc,
((wb_stb)&&(rtc_sel)), wb_we,
{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
/rtl/altbusmaster.v
43,9 → 43,13
`define FANCY_ICAP_ACCESS
`endif
`define FLASH_ACCESS
`define CFG_SCOPE
`define INCLUDE_RTC // 2017 slice LUTs w/o, 2108 with (!!!)
`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
`define INCLUDE_RTC // About 90 LUTs
module altbusmaster(i_clk, i_rst,
// DEPP I/O Control
i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
i_depp_data, o_depp_data, o_depp_wait,
// External UART interface
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
o_uart_rts,
// The SPI Flash lines
58,15 → 62,19
o_uart_setup,
// GPIO lines
i_gpio, o_gpio);
parameter ZIP_ADDRESS_WIDTH=23, ZA=ZIP_ADDRESS_WIDTH,
CMOD_ZIPCPU_RESET_ADDRESS=23'h400100,
BUS_ADDRESS_WIDTH=23, BAW=23; // 24bits->2,258,23b->2181
parameter BUS_ADDRESS_WIDTH=23,
BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
input i_clk, i_rst;
// The bus commander, via an external JTAG port
// The bus commander, via an external DEPP port
input i_depp_astb_n, i_depp_dstb_n, i_depp_write_n;
input wire [7:0] i_depp_data;
output wire [7:0] o_depp_data;
output wire o_depp_wait;
// Serial inputs
input i_rx_stb;
input [7:0] i_rx_data;
output wire o_tx_stb;
output wire [7:0] o_tx_data;
output reg o_tx_stb;
output reg [7:0] o_tx_data;
input i_tx_busy;
output wire o_uart_rts;
// SPI flash control
95,7 → 103,7
//
//
wire wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
wire [31:0] wb_data, wb_idata;
wire [31:0] wb_data, wb_idata, w_wbu_addr;
wire [(BAW-1):0] wb_addr;
wire [5:0] io_addr;
assign io_addr = {
109,27 → 117,12
// Wires going to devices
// And then headed back home
wire w_interrupt;
// Oh, and the debug control for the ZIP CPU
wire zip_dbg_ack, zip_dbg_stall;
wire [31:0] zip_dbg_data;
 
 
`ifdef WBUBUS
//
//
// The BUS master (source): The WB to UART conversion bus
//
//
wire zip_cyc, zip_stb, zip_we, zip_cpu_int;
wire [(ZA-1):0] w_zip_addr;
wire [(BAW-1):0] zip_addr;
wire [31:0] zip_data;
// and then coming from devices
wire zip_ack, zip_stall, zip_err;
wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
wire [(BAW-1):0] dwb_addr;
wire [31:0] dwb_odata;
 
// wire [31:0] zip_debug;
wbubus busbdriver(i_clk, i_rx_stb, i_rx_data,
// The wishbone interface
wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
138,12 → 131,25
// Provide feedback to the UART
o_tx_stb, o_tx_data, i_tx_busy);
assign o_uart_rts = (~rx_rdy);
`else
//
//
// Another BUS master (source): A conversion from DEPP to busmaster
//
//
wbdeppsimple deppdrive(i_clk,
i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
i_depp_data, o_depp_data, o_depp_wait,
wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
wb_ack, wb_stall, wb_err, wb_idata,
w_interrupt);
`endif
 
generate
if (ZA < BAW)
assign wb_addr = { {(BAW-ZA){1'b0}}, w_wbu_addr };
if (BAW < 32)
assign wb_addr = w_wbu_addr[(BAW-1):0];
else
assign wb_addr = w_zip_addr;
assign wb_addr = w_wbu_addr;
endgenerate
 
wire io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
154,7 → 160,7
assign rtc_stall = 1'b0;
`endif
wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
reg io_ack, uart_ack;
reg io_ack;
 
wire [31:0] flash_data, scop_data, cfg_data, mem_data, pwm_data,
spio_data, gpio_data, uart_data;
162,7 → 168,6
reg [(BAW-1):0] bus_err_addr;
 
assign wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
||(uart_ack)
`ifdef INCLUDE_RTC
||(rtc_ack)
`endif
186,9 → 191,8
: 32'h00))));
*/
assign wb_idata = (io_ack|scop_ack)?((io_ack )? io_data : scop_data)
: ((cfg_ack|uart_ack) ? ((cfg_ack)?cfg_data: uart_data)
: ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
: flash_data)); // if (flash_ack)
: ((cfg_ack) ? cfg_data : flash_data));//if (flash_ack)
assign wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
 
// Addresses ...
195,9 → 199,9
// 0000 xxxx configuration/control registers
// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
assign io_sel =((wb_cyc)&&(io_addr[5:0]==6'h1));
assign flctl_sel= 1'b0; // ((wb_cyc)&&(io_addr[5:1]==5'h1));
assign scop_sel =((wb_cyc)&&(io_addr[5:1]==5'h1));
assign cfg_sel =((wb_cyc)&&(io_addr[5:2]==4'h1));
assign scop_sel =((wb_cyc)&&(io_addr[5:0]==6'h2));
assign flctl_sel=((wb_cyc)&&(io_addr[5:0]==6'h3));
assign cfg_sel =((wb_cyc)&&(io_addr[5:1]==5'h2));
// zip_sel is not on the bus at this point
`ifdef INCLUDE_RTC
assign rtc_sel =((wb_cyc)&&(io_addr[5:3]==3'h1));
206,16 → 210,15
assign flash_sel=((wb_cyc)&&(io_addr[5]));
 
assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
/*
assign many_sel =((wb_cyc)&&(wb_stb)&&(
{3'h0, io_sel}
+{3'h0, flctl_sel}
// +{3'h0, scop_sel}
+{3'h0, scop_sel}
+{3'h0, cfg_sel}
+{3'h0, rtc_sel}
+{3'h0, mem_sel}
+{3'h0, flash_sel} > 1));
*/
assign many_sel = 1'b0;
// assign many_sel = 1'b0;
 
wire many_ack;
assign many_ack =((wb_cyc)&&(
238,17 → 241,16
reg rx_rdy;
wire [10:0] int_vector;
assign int_vector = { gpio_int, pwm_int, keypad_int,
1'b0, rx_rdy, tmrb_int, tmra_int,
~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
rtc_interrupt, scop_interrupt,
wb_err, button_int };
 
wire [31:0] pic_data;
icontrol #(11) pic(i_clk, 1'b0,
(wb_cyc)&&(wb_stb)&&(io_sel)
icontrol #(11) pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
&&(wb_addr[3:0]==4'h0)&&(wb_we),
wb_data, pic_data, int_vector, w_interrupt);
 
initial bus_err_addr = `DATESTAMP;
initial bus_err_addr = 0; // `DATESTAMP;
always @(posedge i_clk)
if (wb_err)
bus_err_addr <= wb_addr;
255,11 → 257,13
 
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
wire [31:0] timer_a, timer_b;
ziptimer zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
ziptimer #(32,20)
zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
wb_we, wb_data, zta_ack, zta_stall, timer_a,
tmra_int);
ziptimer zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
ziptimer #(32,20)
zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
tmrb_int);
276,7 → 280,7
assign rtc_ack = r_rtc_ack;
 
rtclight
#(32'h35afe5) // 80 MHz clock
#(23'h35afe5,23,0,0) // 80 MHz clock
thetime(i_clk, wb_cyc,
((wb_stb)&&(rtc_sel)), wb_we,
{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
338,8 → 342,38
// hardware buffer.
//
// We'll add the flag for two stop bits.
assign o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
// assign o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
assign o_uart_setup = 30'h0000208d; // 9600 MBaud, 8N1
 
initial o_tx_stb = 1'b0;
initial o_tx_data = 8'h00;
always @(posedge i_clk)
if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
begin
o_tx_data <= wb_data[7:0];
o_tx_stb <= 1'b1;
end
else if ((o_tx_stb)&&(~i_tx_busy))
o_tx_stb <= 1'b0;
initial rx_rdy = 1'b0;
always @(posedge i_clk)
if (i_rx_stb)
r_rx_data <= i_rx_data;
always @(posedge i_clk)
begin
if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
rx_rdy <= i_rx_stb;
else if (i_rx_stb)
rx_rdy <= (rx_rdy | i_rx_stb);
end
assign o_uart_rts = (~rx_rdy);
assign uart_data = { 23'h0, ~rx_rdy, r_rx_data };
//
// uart_ack gets returned as part of io_ack, since that happens when
// io_sel and wb_stb are defined
//
// always @(posedge i_clk)
// uart_ack<= ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
 
 
 
349,7 → 383,7
wire flash_cs_n, flash_sck, flash_mosi;
wbqspiflashp #(24) flashmem(i_clk,
wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
wb_addr[21:0], wb_data,
wb_addr[(24-3):0], wb_data,
flash_ack, flash_stall, flash_data,
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
flash_interrupt);
377,8 → 411,17
//
// ON-CHIP RAM MEMORY ACCESS
//
`ifdef IMPLEMENT_ONCHIP_RAM
memdev #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
`else
assign mem_data = 32'h00;
assign mem_stall = 1'b0;
reg r_mem_ack;
always @(posedge i_clk)
r_mem_ack <= (wb_cyc)&&(wb_stb)&&(mem_sel);
assign mem_ack = r_mem_ack;
`endif
 
//
//
389,15 → 432,22
//
wire [31:0] scop_cfg_data;
wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
`ifdef CFG_SCOPE
`ifdef DBG_SCOPE
wire scop_cfg_trigger;
assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
// Wishbone interface
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
i_clk, wb_cyc, (wb_stb)&&(scop_sel),
wb_we, wb_addr[0], wb_data,
scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
scop_cfg_interrupt);
`else
reg r_scop_cfg_ack;
always @(posedge i_clk)
r_scop_cfg_ack <= (wb_cyc)&&(wb_stb)&&(scop_sel);
assign scop_cfg_ack = r_scop_cfg_ack;
assign scop_cfg_data = 32'h000;
assign scop_cfg_stall= 1'b0;
`endif
 
assign scop_interrupt = scop_cfg_interrupt;
407,4 → 457,3
 
endmodule
 
// 0x8684 interrupts ...???
/rtl/Makefile
0,0 → 1,89
################################################################################
#
# Filename: rtl/Makefile
#
# Project: CMod S6 System on a Chip, ZipCPU demonstration project
#
# Purpose: This makefile builds a verilator simulation of the zipsystem.
# It does not make the system within Vivado or Quartus.
#
# Creator: Dan Gisselquist, Ph.D.
# Gisselquist Technology, LLC
#
################################################################################
#
# Copyright (C) 2015-2016, Gisselquist Technology, LLC
#
# This program is free software (firmware): you can redistribute it and/or
# modify it under the terms of the GNU General Public License as published
# by the Free Software Foundation, either version 3 of the License, or (at
# your option) any later version.
#
# This program is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program. (It's in the $(ROOT)/doc directory, run make with no
# target there if the PDF file isn't present.) If not, see
# <http://www.gnu.org/licenses/> for a copy.
#
# License: GPL, v3, as defined and found on www.gnu.org,
# http://www.gnu.org/licenses/gpl.html
#
#
################################################################################
#
#
.PHONY: all
all: busmaster altbusmaster
 
CPUD := cpu
RAWZIP := zipbones.v zipcpu.v cpudefs.v \
prefetch.v idecode.v cpuops.v memops.v \
wbdblpriarb.v
ZIPSRC := $(addprefix $(CPUD)/,$(RAWZIP))
BUSSRC := builddate.v llqspi.v wbicape6.v wbicapesimple.v wbscope.v \
memdev.v rtclight.v spio.v wbgpio.v wbpwmaudio.v
MAINSRC := busmaster.v builddate.v flash_config.v wbqspiflash.v \
$(BUSSRC) $(ZIPSRC)
# toplevel.v rxuart.v txuart.v
ALTSRC := altbusmaster.v builddate.v flash_config.v wbqspiflash.v \
$(BUSSRC) wbdeppsimple.v
# alttop.v rxuart.v txuart.v
# rtcdate.v wbubus.v
 
VOBJ := obj_dir
 
$(VOBJ)/Vbusmaster.cpp: $(MAINSRC)
verilator -cc -y $(CPUD) busmaster.v
$(VOBJ)/Vbusmaster.h: $(VOBJ)/Vbusmaster.cpp
 
$(VOBJ)/Valtbusmaster.cpp: $(ALTSRC)
verilator -cc -y $(CPUD) altbusmaster.v
$(VOBJ)/Valtbusmaster.h: $(VOBJ)/Valtbusmaster.cpp
 
$(VOBJ)/Vbusmaster__ALL.a: $(VOBJ)/Vbusmaster.cpp $(VOBJ)/Vbusmaster.h
cd $(VOBJ); make --no-print-directory -f Vbusmaster.mk
 
$(VOBJ)/Valtbusmaster__ALL.a: $(VOBJ)/Valtbusmaster.cpp $(VOBJ)/Valtbusmaster.h
cd $(VOBJ); make --no-print-directory -f Valtbusmaster.mk
 
cpudefs.h: cpudefs.v
@echo "Building cpudefs.h"
@echo "// " > $@
@echo "// Do not edit this file, it is automatically generated!" >> $@
@echo "// To generate this file, \"make cpudefs.h\" in the rtl directory." >> $@
@echo "// " >> $@
@grep "^\`" $^ | sed -e '{ s/^`/#/ }' >> $@
 
.PHONY: busmaster
busmaster: $(VOBJ)/Vbusmaster__ALL.a
 
.PHONY: altbusmaster
altbusmaster: $(VOBJ)/Valtbusmaster__ALL.a
 
.PHONY: clean
clean:
rm -rf $(VOBJ) cpudefs.h
/rtl/spio.v
6,6 → 6,8
//
// Purpose:
//
// With the USB cord on top, the board facing you, LED[0] is on the left.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
/sw/host/regdefs.cpp
0,0 → 1,162
////////////////////////////////////////////////////////////////////////////////
//
// Filename: regdefs.cpp
//
// Project: CMod S6 System on a Chip, ZipCPU demonstration project
//
// Purpose: To give human readable names to the various registers available
// internal to the processor on the wishbone bus. This file is
// primarily used for name to number translation within wbregs.cpp.
// All names for a given register are equivalent, save only that the
// register will always be identified by its first name in any output.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#include <stdio.h>
#include <stdlib.h>
#include <strings.h>
#include <ctype.h>
#include "regdefs.h"
 
const REGNAME raw_bregs[] = {
{ R_VERSION, "VERSION" },
{ R_ICONTROL, "ICONTROL" },
{ R_ICONTROL, "INT" },
{ R_ICONTROL, "PIC" },
{ R_ICONTROL, "INTC" },
{ R_BUSERR, "BUSERR" },
{ R_BUSERR, "BUS" },
{ R_ITIMERA, "TMRA" },
{ R_ITIMERB, "TMRB" },
{ R_PWM, "PWMAUDIO" },
{ R_PWM, "PWM" },
{ R_PWM, "PWMDATA" },
{ R_PWM, "AUDIO" },
{ R_SPIO, "SPIO" },
{ R_GPIO, "GPIO" },
{ R_UART, "UART" },
{ R_UART, "UART-RX" },
{ R_UART, "UARTRX" },
{ R_UART, "RX" },
{ R_UART, "UART-TX" },
{ R_UART, "UARTTX" },
{ R_UART, "TX" },
//
{ R_QSPI_EREG, "QSPIEREG" },
{ R_QSPI_EREG, "QSPIE" },
{ R_QSPI_CREG, "QSPICONF" },
{ R_QSPI_CREG, "QSPIC" },
{ R_QSPI_SREG, "QSPISTAT" },
{ R_QSPI_SREG, "QSPIS" },
{ R_QSPI_IDREG, "QSPIID" },
{ R_QSPI_IDREG, "QSPII" },
//
{ R_CLOCK, "CLOCK" },
{ R_CLOCK, "TIME" },
{ R_TIMER, "TIMER" },
{ R_STOPWATCH, "STOPWACH" },
{ R_STOPWATCH, "STOPWATCH" },
{ R_CKALARM, "CKALARM" },
{ R_CKALARM, "ALARM" },
// { R_DATE, "DATE" },
// Scopes are defined and come and go. Be aware, therefore, not all
// of these scopes may be defined at the same time.
{ R_SCOPE, "SCOPE" },
{ R_SCOPE, "SCOP" },
{ R_SCOPED, "SCOPDATA" },
{ R_SCOPED, "SCDATA" },
{ R_SCOPED, "SCOPED" },
{ R_SCOPED, "SCOPD" },
//
// For working with the ICAPE interface ... if I can ever get a
// testing environment suitable to prove that it works.
//
{ R_CFG_CRC, "FPGACRC" },
{ R_CFG_FAR_MAJ, "FPGAFARH" },
{ R_CFG_FAR_MIN, "FPGAFARL" },
{ R_CFG_FDRI, "FPGAFDRI" },
{ R_CFG_FDRO, "FPGAFDRO" },
{ R_CFG_CMD, "FPGACMD" },
{ R_CFG_CTL, "FPGACTL" },
{ R_CFG_MASK, "FPGAMASK" },
{ R_CFG_STAT, "FPGASTAT" },
{ R_CFG_LOUT, "FPGALOUT" },
{ R_CFG_COR1, "FPGACOR1" },
{ R_CFG_COR2, "FPGACOR2" },
{ R_CFG_PWRDN, "FPGAPWRDN" },
{ R_CFG_FLR, "FPGAFLR" },
{ R_CFG_IDCODE, "FPGAIDCODE" },
{ R_CFG_CWDT, "FPGACWDT" },
{ R_CFG_HCOPT, "FPGAHCOPT" },
{ R_CFG_CSBO, "FPGACSBO" },
{ R_CFG_GEN1, "FPGAGEN1" },
{ R_CFG_GEN2, "FPGAGEN2" },
{ R_CFG_GEN3, "FPGAGEN3" },
{ R_CFG_GEN4, "FPGAGEN4" },
{ R_CFG_GEN5, "FPGAGEN5" },
{ R_CFG_MODE, "FPGAMODE" },
{ R_CFG_GWE, "FPGAGWE" },
{ R_CFG_GTS, "FPGAGTS" },
{ R_CFG_MFWR, "FPGAMFWR" },
{ R_CFG_CCLK, "FPGACCLK" },
{ R_CFG_SEU, "FPGASEU" },
{ R_CFG_EXP, "FPGAEXP" },
{ R_CFG_RDBK, "FPGARDBK" },
{ R_CFG_BOOTSTS, "BOOTSTS" },
{ R_CFG_EYE, "FPGAEYE" },
{ R_CFG_CBC, "FPGACBC" },
//
{ RAMBASE, "MEM" },
{ SPIFLASH, "FLASH" }
};
 
#define RAW_NREGS (sizeof(raw_bregs)/sizeof(bregs[0]))
 
const REGNAME *bregs = raw_bregs;
const int NREGS = RAW_NREGS;
 
unsigned addrdecode(const char *v) {
if (isalpha(v[0])) {
for(int i=0; i<NREGS; i++)
if (strcasecmp(v, bregs[i].m_name)==0)
return bregs[i].m_addr;
fprintf(stderr, "Unknown register: %s\n", v);
exit(-2);
} else
return strtoul(v, NULL, 0);
}
 
const char *addrname(const unsigned v) {
for(int i=0; i<NREGS; i++)
if (bregs[i].m_addr == v)
return bregs[i].m_name;
return NULL;
}
 
/sw/host/flashdrvr.h
0,0 → 1,53
////////////////////////////////////////////////////////////////////////////////
//
// Filename: flashdrvr.h
//
// Project: XuLA2-LX25 System on a Chip
//
// Purpose: Flash driver. Encapsulate writing to the flash device.
//
// Creator: Dan Gisselquist
// Gisselquist Tecnology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
//
#ifndef FLASHDRVR_H
#define FLASHDRVR_H
 
#include "regdefs.h"
 
class FLASHDRVR {
private:
DEVBUS *m_fpga;
 
void flwait(void);
public:
FLASHDRVR(DEVBUS *fpga) : m_fpga(fpga) {}
bool erase_sector(const unsigned sector, const bool verify_erase=true);
bool write_page(const unsigned addr, const unsigned len,
const unsigned *data, const bool verify_write=true);
bool write(const unsigned addr, const unsigned len,
const unsigned *data, const bool verify=false);
};
 
#endif
/sw/host/twoc.h
0,0 → 1,46
////////////////////////////////////////////////////////////////////////////
//
// Filename: twoc.h
//
// Project: A Doubletime Pipelined FFT
//
// Purpose: Some various two's complement related C++ helper routines.
// Specifically, these help extract signed numbers from
// packed bitfields, while guaranteeing that the upper bits
// are properly sign extended (or not) as desired.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
#ifndef TWOC_H
#define TWOC_H
 
extern long sbits(const long val, const int bits);
extern unsigned long ubits(const long val, const int bits);
 
#endif
 
/sw/host/deppbus.cpp
0,0 → 1,243
////////////////////////////////////////////////////////////////////////////////
//
// Filename: deppbus.cpp
//
// Project: CMod S6 System on a Chip, ZipCPU demonstration project
//
// Purpose: This is a *very* simple Depp to Wishbone driver conversion.
// Look in devbus.cpp for a description of how to use the driver.
//
// The driver is simple: there are 9 registers of interest to run this
// driver. The first four registers, 0-3, are address registers, MSB
// first. Place your 32-bit address into these registers. The next four
// registers, 4-7, are data registers. If writing data, place the data
// to write into these registers. The last register, 16, is a strobe
// register. Write a 1 to read, and a 3 to write, to this register. A
// bus transaction will then take place. Once completed, registers 4-7
// will contain the resulting data.
//
// That's the internal workings of this driver. The above description is
// accomplished in the readio() and writeio() routines.
//
// This is *not* a fully featured DEVBUS class--it does not support
// pipelined reads or writes. It does not support compression. It does,
// however, support reading and writing a simple 32-bit wishbone bus.
// That is good enough, of itself, for now.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#include <stdlib.h>
#include <stdio.h>
#include "dpcdecl.h"
#include "dmgr.h"
#include "depp.h"
#include "deppbus.h"
 
DEPPBUS::DEPPBUS(char *szSel) {
if (!DmgrOpen(&m_dev, szSel)) {
fprintf(stderr, "Open failed!\n");
exit(EXIT_FAILURE);
}
 
if (!DeppEnable(m_dev)) {
fprintf(stderr, "Could not enable DEPP interface\n");
exit(EXIT_FAILURE);
}
 
m_int = false, m_err = false;
}
 
DEPPBUS::~DEPPBUS(void) {
if (m_dev)
DmgrClose(m_dev);
m_dev = 0;
}
 
void DEPPBUS::kill(void) { close(); }
void DEPPBUS::close(void) { DmgrClose(m_dev); m_dev = 0; }
 
void DEPPBUS::depperr(void) {
ERC erc = DmgrGetLastError();
if (erc != ercNoErc) {
char scode[cchErcMax], msg[cchErcMsgMax];
DmgrSzFromErc(erc,scode,msg);
fprintf(stderr, "ErrCode : %s\n", scode);
fprintf(stderr, "ErrMessage: %s\n", msg);
close();
exit(EXIT_FAILURE);
}
}
 
void DEPPBUS::writeio(const BUSW a, const BUSW v) {
bool good = true;
 
// Set the address for our data
good = good && DeppPutReg(m_dev, 0, (a>>24)&0x0ff, false);
good = good && DeppPutReg(m_dev, 1, (a>>16)&0x0ff, false);
good = good && DeppPutReg(m_dev, 2, (a>> 8)&0x0ff, false);
good = good && DeppPutReg(m_dev, 3, a &0x0ff, false);
if (!good) {
fprintf(stderr, "BUS CYCLE FAILED\n");
depperr(); close();
exit(EXIT_FAILURE);
}
 
// Set the data to be transmitted
good = good && DeppPutReg(m_dev, 4, (v>>24)&0x0ff, false);
good = good && DeppPutReg(m_dev, 5, (v>>16)&0x0ff, false);
good = good && DeppPutReg(m_dev, 6, (v>> 8)&0x0ff, false);
good = good && DeppPutReg(m_dev, 7, v &0x0ff, false);
if (!good) {
fprintf(stderr, "BUS CYCLE FAILED\n");
depperr(); close();
exit(EXIT_FAILURE);
}
 
// Perform the operation
good = good && DeppPutReg(m_dev,16, 0x3, false);
if (!good) {
fprintf(stderr, "BUS CYCLE FAILED\n");
depperr(); close();
exit(EXIT_FAILURE);
}
 
// Now, let's check for any bus errors and/or interrupts
BYTE retn;
good = good && DeppGetReg(m_dev,16, &retn, false);
m_err = m_err | (retn&1);
m_int = m_int | (retn&2);
 
if (!good) {
fprintf(stderr, "BUS CYCLE FAILED\n");
depperr(); close();
exit(EXIT_FAILURE);
}
 
if (m_err)
throw BUSERR(a);
}
 
DEVBUS::BUSW DEPPBUS::readio(const DEVBUS::BUSW a) {
BUSW v = 0;
BYTE retn;
bool good = true;
 
// Set the address for our data
good = good && DeppPutReg(m_dev, 0, (a>>24)&0x0ff, false);
good = good && DeppPutReg(m_dev, 1, (a>>16)&0x0ff, false);
good = good && DeppPutReg(m_dev, 2, (a>> 8)&0x0ff, false);
good = good && DeppPutReg(m_dev, 3, a &0x0ff, false);
 
if (!good) {
fprintf(stderr, "BUS CYCLE FAILED\n");
depperr(); close();
exit(EXIT_FAILURE);
}
 
// Run the bus cycle
good = good && DeppPutReg(m_dev,16, 0x1, false);
if (!good) {
fprintf(stderr, "BUS CYCLE FAILED\n");
depperr(); close();
exit(EXIT_FAILURE);
}
 
// Check for any bus errors and/or interrupts
good = good && DeppGetReg(m_dev,16, &retn, false);
if (!good) {
fprintf(stderr, "BUS CYCLE FAILED\n");
depperr(); close();
exit(EXIT_FAILURE);
}
 
m_err = m_err | (retn&1);
m_int = m_int | (retn&2);
 
if (m_err)
throw BUSERR(a);
 
// Otherwise let's get our result
good = good && DeppGetReg(m_dev, 4, &retn, false); v = (retn & 0x0ff);
good = good && DeppGetReg(m_dev, 5, &retn, false); v = (v<<8)|(retn & 0x0ff);
good = good && DeppGetReg(m_dev, 6, &retn, false); v = (v<<8)|(retn & 0x0ff);
good = good && DeppGetReg(m_dev, 7, &retn, false); v = (v<<8)|(retn & 0x0ff);
if (!good) {
fprintf(stderr, "BUS CYCLE FAILED\n");
depperr(); close();
exit(EXIT_FAILURE);
}
 
return v;
}
 
void DEPPBUS::readi(const BUSW a, const int len, BUSW *buf) {
for(int i=0; i<len; i++)
buf[i] = readio(a+i);
} void DEPPBUS::readz(const BUSW a, const int len, BUSW *buf) {
for(int i=0; i<len; i++)
buf[i] = readio(a);
}
 
void DEPPBUS::writei(const BUSW a, const int len, const BUSW *buf) {
for(int i=0; i<len; i++)
writeio(a+i, buf[i]);
} void DEPPBUS::writez(const BUSW a, const int len, const BUSW *buf) {
for(int i=0; i<len; i++)
writeio(a, buf[i]);
}
 
bool DEPPBUS::poll(void) {
if (m_int)
return true;
// Check for any bus errors and/or interrupts
BYTE retn;
DeppGetReg(m_dev,16, &retn, false);
m_err = m_err | (retn&1);
m_int = m_int | (retn&2);
 
if (m_int)
return true;
return false;
} void DEPPBUS::usleep(unsigned msec) {
if (!poll())
usleep(msec);
} void DEPPBUS::wait(void) {
while(!poll())
usleep(5);
} bool DEPPBUS::bus_err(void) const {
return m_err;
} void DEPPBUS::reset_err(void) {
m_err = false;
} void DEPPBUS::clear(void) {
m_int = false;
m_err = false;
}
 
/sw/host/regdefs.h
0,0 → 1,156
////////////////////////////////////////////////////////////////////////////////
//
// Filename: regdefs.h
//
// Project: CMod S6 System on a Chip, ZipCPU demonstration project
//
// Purpose:
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#ifndef REGDEFS_H
#define REGDEFS_H
 
#define R_VERSION 0x00000108
#define R_ICONTROL 0x00000100
#define R_BUSERR 0x00000101
#define R_ITIMERA 0x00000102
#define R_ITIMERB 0x00000103
#define R_PWM 0x00000104
#define R_SPIO 0x00000105
#define R_GPIO 0x00000106
#define R_UART 0x00000107
 
// WB Scope registers
#define R_SCOPE 0x00000200
#define R_SCOPED 0x00000201
//
// And because the flash driver needs these constants defined ...
#define R_QSPI_EREG 0x0000030c
#define R_QSPI_CREG 0x0000030d
#define R_QSPI_SREG 0x0000030e
#define R_QSPI_IDREG 0x0000030f
//
// FPGA CONFIG/ICAP REGISTERS
#define R_CFG_CRC 0x00000400
#define R_CFG_FAR_MAJ 0x00000401
#define R_CFG_FAR_MIN 0x00000402
#define R_CFG_FDRI 0x00000403
#define R_CFG_FDRO 0x00000404
#define R_CFG_CMD 0x00000405
#define R_CFG_CTL 0x00000406
#define R_CFG_MASK 0x00000407
#define R_CFG_STAT 0x00000408
#define R_CFG_LOUT 0x00000409
#define R_CFG_COR1 0x0000040a
#define R_CFG_COR2 0x0000040b
#define R_CFG_PWRDN 0x0000040c
#define R_CFG_FLR 0x0000040d
#define R_CFG_IDCODE 0x0000040e
#define R_CFG_CWDT 0x0000040f
#define R_CFG_HCOPT 0x00000410
#define R_CFG_CSBO 0x00000412
#define R_CFG_GEN1 0x00000413
#define R_CFG_GEN2 0x00000414
#define R_CFG_GEN3 0x00000415
#define R_CFG_GEN4 0x00000416
#define R_CFG_GEN5 0x00000417
#define R_CFG_MODE 0x00000418
#define R_CFG_GWE 0x00000419
#define R_CFG_GTS 0x0000041a
#define R_CFG_MFWR 0x0000041b
#define R_CFG_CCLK 0x0000041c
#define R_CFG_SEU 0x0000041d
#define R_CFG_EXP 0x0000041e
#define R_CFG_RDBK 0x0000041f
#define R_CFG_BOOTSTS 0x00000420
#define R_CFG_EYE 0x00000421
#define R_CFG_CBC 0x00000422
// RTC clock control
#define R_CLOCK 0x00000800
#define R_TIMER 0x00000801
#define R_STOPWATCH 0x00000802
#define R_CKALARM 0x00000803
 
// RAM memory space
#define RAMBASE 0x00002000
#define MEMWORDS (1<<12)
// Flash memory space
#define SPIFLASH 0x00040000
#define FLASHWORDS (1<<18)
// SDRAM memory space
#define SDRAMBASE 0x00400000
#define SDRAMWORDS (1<<24)
 
// Interrupt control constants
// #define GIE 0x80000000 // Enable all interrupts
// #define SCOPEN 0x80080008 // Enable WBSCOPE interrupts
// #define ISPIF_EN 0x80040004 // Enable SPI Flash interrupts
// #define ISPIF_DIS 0x00040000 // Disable SPI Flash interrupts
// #define ISPIF_CLR 0x00000004 // Clear pending SPI Flash interrupt
 
// Flash control constants
#define ERASEFLAG 0x80000000
#define DISABLEWP 0x10000000
 
#define SZPAGE 64
#define PGLEN 64
#define NPAGES 32
#define SECTORSZ (NPAGES * SZPAGE)
#define NSECTORS 256
#define SECTOROF(A) ((A) & (-1<<10))
#define PAGEOF(A) ((A) & (-1<<6))
 
#define RAMLEN MEMWORDS
 
// Scop definition/sequences
#define SCOPE_NO_RESET 0x80000000
#define SCOPE_TRIGGER (0x08000000|SCOPE_NO_RESET)
#define SCOPE_DISABLE (0x04000000)
 
typedef struct {
unsigned m_addr;
const char *m_name;
} REGNAME;
 
extern const REGNAME *bregs;
extern const int NREGS;
// #define NREGS (sizeof(bregs)/sizeof(bregs[0]))
 
extern unsigned addrdecode(const char *v);
extern const char *addrname(const unsigned v);
 
// #include "ttybus.h"
// #include "portbus.h"
// #include "deppbus.h"
 
// typedef DEPPBUS FPGA;
 
#endif
/sw/host/deppbus.h
0,0 → 1,79
////////////////////////////////////////////////////////////////////////////////
//
// Filename: deppbus.h
//
// Project: CMod S6 System on a Chip, ZipCPU demonstration project
//
// Purpose: An instantiation of a generic interface to a wishbone on a
// device. This particular instantiation uses a simplified
// interface over a Digilent Adept Asynchronous Parallel Port Interface
// (DEPP)--useful for working with the CMod-S6.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#ifndef DEPPBUS_H
#define DEPPBUS_H
 
#include "dpcdecl.h"
#include "dmgr.h"
#include "devbus.h"
 
class DEPPBUS : public DEVBUS {
HIF m_dev;
bool m_int, m_err;
 
void depperr(void);
 
public:
typedef DEVBUS::BUSW BUSW;
 
DEPPBUS(char *szSel);
~DEPPBUS(void);
 
void kill(void);
void close(void);
 
void writeio(const BUSW a, const BUSW v);
BUSW readio(const BUSW a);
 
void readi(const BUSW a, const int len, BUSW *buf);
void readz(const BUSW a, const int len, BUSW *buf);
 
void writei(const BUSW a, const int len, const BUSW *buf);
void writez(const BUSW a, const int len, const BUSW *buf);
bool poll(void);
void usleep(unsigned msec);
void wait(void);
bool bus_err(void) const;
void reset_err(void);
void clear(void);
};
 
#endif
/sw/host/wbregs.cpp
0,0 → 1,122
////////////////////////////////////////////////////////////////////////////////
//
// Filename: wbregs.cpp
//
// Project: CMod S6 System on a Chip, ZipCPU demonstration project
//
// Purpose: To give a user access, via a command line program, to read
// and write wishbone registers one at a time. Thus this program
// implements readio() and writeio() but nothing more.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
//
//
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <strings.h>
#include <ctype.h>
#include <string.h>
#include <signal.h>
#include <assert.h>
 
#include "deppbus.h"
// #include "port.h"
#include "regdefs.h"
 
typedef DEPPBUS FPGA;
 
FPGA *m_fpga;
void closeup(int v) {
m_fpga->kill();
exit(0);
}
 
int main(int argc, char **argv) {
int skp=0;
 
skp=1;
for(int argn=0; argn<argc-skp; argn++) {
if (argv[argn+skp][0] == '-') {
// switch(argv[argn+skp][j]) {
// default:
// break;
// }
skp++; argn--;
} else
argv[argn] = argv[argn+skp];
} argc -= skp;
 
char szSel[64];
strcpy(szSel, "SN:210282768825");
m_fpga = new DEPPBUS(szSel);
 
signal(SIGSTOP, closeup);
signal(SIGHUP, closeup);
 
if ((argc < 1)||(argc > 2)) {
// usage();
printf("USAGE: wbregs address [value]\n");
exit(-1);
}
 
const char *nm;
unsigned address = addrdecode(argv[0]), value;
nm = addrname(address);
if (nm == NULL)
nm = "no name";
 
if (argc < 2) {
FPGA::BUSW v;
try {
unsigned char a, b, c, d;
v = m_fpga->readio(address);
a = (v>>24)&0x0ff;
b = (v>>16)&0x0ff;
c = (v>> 8)&0x0ff;
d = (v )&0x0ff;
printf("%08x (%8s) : [%c%c%c%c] %08x\n", address, nm,
isgraph(a)?a:'.', isgraph(b)?b:'.',
isgraph(c)?c:'.', isgraph(d)?d:'.', v);
} catch(BUSERR b) {
printf("%08x (%8s) : BUS-ERROR\n", address, nm);
}
} else {
value = strtoul(argv[1], NULL, 0);
m_fpga->writeio(address, value);
printf("%08x (%8s)-> %08x\n", address, nm, value);
}
 
if (m_fpga->poll())
printf("FPGA was interrupted\n");
delete m_fpga;
}
 
/sw/host/flashdrvr.cpp
0,0 → 1,219
////////////////////////////////////////////////////////////////////////////////
//
// Filename: flashdrvr.cpp
//
// Project: CMod S6 System on a Chip, ZipCPU demonstration project
//
// Purpose: Flash driver. Encapsulate writing to the flash device.
//
// Creator: Dan Gisselquist
// Gisselquist Tecnology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
//
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <strings.h>
#include <ctype.h>
#include <string.h>
#include <signal.h>
#include <assert.h>
 
#include "port.h"
#include "regdefs.h"
#include "flashdrvr.h"
 
const bool HIGH_SPEED = false;
 
void FLASHDRVR::flwait(void) {
DEVBUS::BUSW v;
 
v = m_fpga->readio(R_QSPI_EREG);
if ((v&ERASEFLAG)==0)
return;
m_fpga->writeio(R_ICONTROL, ISPIF_DIS);
m_fpga->clear();
m_fpga->writeio(R_ICONTROL, ISPIF_EN);
 
do {
// Start by checking that we are still erasing. The interrupt
// may have been generated while we were setting things up and
// disabling things, so this just double checks for us. If
// the interrupt was tripped, we're done. If not, we can now
// wait for an interrupt.
v = m_fpga->readio(R_QSPI_EREG);
if (v&ERASEFLAG) {
m_fpga->usleep(400);
if (m_fpga->poll()) {
m_fpga->clear();
m_fpga->writeio(R_ICONTROL, ISPIF_EN);
}
}
} while(v & ERASEFLAG);
}
 
bool FLASHDRVR::erase_sector(const unsigned sector, const bool verify_erase) {
DEVBUS::BUSW page[SZPAGE];
 
printf("Erasing sector: %08x\n", sector);
m_fpga->writeio(R_QSPI_EREG, DISABLEWP);
m_fpga->writeio(R_QSPI_EREG, ERASEFLAG + sector);
 
// If we're in high speed mode and we want to verify the erase, then
// we can skip waiting for the erase to complete by issueing a read
// command immediately. As soon as the erase completes the read will
// begin sending commands back. This allows us to recover the lost
// time between the interrupt and the next command being received.
if ((!HIGH_SPEED)||(!verify_erase)) {
flwait();
 
printf("@%08x -> %08x\n", R_QSPI_EREG,
m_fpga->readio(R_QSPI_EREG));
printf("@%08x -> %08x\n", R_QSPI_SREG,
m_fpga->readio(R_QSPI_SREG));
printf("@%08x -> %08x\n", sector,
m_fpga->readio(sector));
}
 
// Now, let's verify that we erased the sector properly
if (verify_erase) {
for(int i=0; i<NPAGES; i++) {
m_fpga->readi(sector+i*SZPAGE, SZPAGE, page);
for(int i=0; i<SZPAGE; i++)
if (page[i] != 0xffffffff)
return false;
}
}
 
return true;
}
 
bool FLASHDRVR::write_page(const unsigned addr, const unsigned len,
const unsigned *data, const bool verify_write) {
DEVBUS::BUSW buf[SZPAGE];
 
assert(len > 0);
assert(len <= PGLEN);
assert(PAGEOF(addr)==PAGEOF(addr+len-1));
 
if (len <= 0)
return true;
 
// Write the page
m_fpga->writeio(R_ICONTROL, ISPIF_DIS);
m_fpga->clear();
m_fpga->writeio(R_ICONTROL, ISPIF_EN);
printf("Writing page: 0x%08x - 0x%08x\n", addr, addr+len-1);
m_fpga->writeio(R_QSPI_EREG, DISABLEWP);
m_fpga->writei(addr, len, data);
 
// If we're in high speed mode and we want to verify the write, then
// we can skip waiting for the write to complete by issueing a read
// command immediately. As soon as the write completes the read will
// begin sending commands back. This allows us to recover the lost
// time between the interrupt and the next command being received.
if ((!HIGH_SPEED)||(!verify_write)) {
flwait();
} if (verify_write) {
// NOW VERIFY THE PAGE
m_fpga->readi(addr, len, buf);
for(unsigned i=0; i<len; i++) {
if (buf[i] != data[i]) {
printf("\nVERIFY FAILS[%d]: %08x\n", i, i+addr);
printf("\t(Flash[%d]) %08x != %08x (Goal[%08x])\n",
i, buf[i], data[i], i+addr);
return false;
}
}
} return true;
}
 
bool FLASHDRVR::write(const unsigned addr, const unsigned len,
const unsigned *data, const bool verify) {
// Work through this one sector at a time.
// If this buffer is equal to the sector value(s), go on
// If not, erase the sector
 
// m_fpga->writeio(R_QSPI_CREG, 2);
// m_fpga->readio(R_VERSION); // Read something innocuous
// m_fpga->writeio(R_QSPI_SREG, 0);
// m_fpga->readio(R_VERSION); // Read something innocuous
 
for(unsigned s=SECTOROF(addr); s<SECTOROF(addr+len+SECTORSZ-1); s+=SECTORSZ) {
// printf("IN LOOP, s=%08x\n", s);
// Do we need to erase?
bool need_erase = false;
unsigned newv = 0; // (s<addr)?addr:s;
{
DEVBUS::BUSW *sbuf = new DEVBUS::BUSW[SECTORSZ];
const DEVBUS::BUSW *dp;
unsigned base,ln;
base = (addr>s)?addr:s;
ln=((addr+len>s+SECTORSZ)?(s+SECTORSZ):(addr+len))-base;
m_fpga->readi(base, ln, sbuf);
 
dp = &data[base-addr];
for(unsigned i=0; i<ln; i++) {
if ((sbuf[i]&dp[i]) != dp[i]) {
printf("\nNEED-ERASE @0x%08x ... %08x != %08x (Goal)\n",
i+base-addr, sbuf[i], dp[i]);
need_erase = true;
newv = i+base;
break;
} else if ((sbuf[i] != dp[i])&&(newv == 0)) {
// if (newv == 0)
// printf("MEM[%08x] = %08x (!= %08x (Goal))\n",
// i+base, sbuf[i], dp[i]);
newv = i+base;
}
}
}
 
if (newv == 0)
continue; // This sector already matches
 
// Just erase anyway
if ((need_erase)&&(!erase_sector(s, verify))) {
printf("SECTOR ERASE FAILED!\n");
return false;
} else if (!need_erase)
printf("NO ERASE NEEDED\n");
else {
printf("ERASING SECTOR %08x\n", s);
newv = (s<addr) ? addr : s;
}
for(unsigned p=newv; (p<s+SECTORSZ)&&(p<addr+len); p=PAGEOF(p+PGLEN))
if (!write_page(p, (p+PGLEN<addr+len)
?((PAGEOF(p)!=PAGEOF(p+PGLEN-1))?(PAGEOF(p+PGLEN-1)-p):PGLEN)
:(addr+len-p), &data[p-addr]), verify) {
printf("WRITE-PAGE FAILED!\n");
return false;
}
}
 
m_fpga->writeio(R_QSPI_EREG, 0); // Re-enable write protection
 
return true;
}
 
/sw/host/twoc.cpp
0,0 → 1,105
////////////////////////////////////////////////////////////////////////////
//
// Filename: twoc.cpp
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: Some various two's complement related C++ helper routines.
// Specifically, these help extract signed numbers from
// packed bitfields, while guaranteeing that the upper bits
// are properly sign extended (or not) as desired.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
#include <stdio.h>
#include <assert.h>
#include "twoc.h"
 
long sbits(const long val, const int bits) {
long r;
 
r = val & ((1l<<bits)-1);
if (r & (1l << (bits-1)))
r |= (-1l << bits);
return r;
}
 
bool sfits(const long val, const int bits) {
long alt = sbits(val, bits);
return (sbits(val, bits) == bits);
}
 
unsigned long ubits(const long val, const int bits) {
unsigned long r = val & ((1l<<bits)-1);
return r;
}
 
unsigned long rndbits(const long val, const int bits_in, const int bits_out) {
long s = sbits(val, bits_in); // Signed input value
long t = s; // Truncated input value
long r; // Result
 
// printf("RNDBITS(%08lx, %d, %d)\n", val, bits_in, bits_out);
// printf("S = %lx\n", s);
// printf("T = %lx\n", t);
// assert(bits_in > bits_out);
if (bits_in == bits_out)
r = s;
else if (bits_in-1 == bits_out) {
t = sbits(val>>1, bits_out);
// printf("TEST! S = %ld, T = %ld\n", s, t);
if (3 == (s&3))
t = t+1;
r = t;
} else {
// A. 0XXXX.0xxxxx -> 0XXXX
// B. 0XXX0.100000 -> 0XXX0;
// C. 0XXX1.100000 -> 0XXX1+1;
// D. 0XXXX.1zzzzz -> 0XXXX+1;
// E. 1XXXX.0xxxxx -> 1XXXX
// F. 1XXX0.100000 -> ??? XXX0;
// G. 1XXX1.100000 -> ??? XXX1+1;
// H. 1XXXX.1zzzzz -> 1XXXX+1;
t = sbits(val>>(bits_in-bits_out), bits_out); // Truncated value
if (0 == ((s >> (bits_in-bits_out-1))&1)) {
// printf("A\n");
r = t;
} else if (0 != (s & ((1<<(bits_in-bits_out-1))-1))) {
// printf("D\n");
r = t+1;
} else if (t&1) {
// printf("C\n");
r = t+1;
} else { // 3 ..?11
// printf("B\n");
r = t;
}
} return r;
}
 
 
/sw/host/Makefile
0,0 → 1,47
all:
PROGRAMS := wbregs
all: $(PROGRAMS)
 
CXX := g++
OBJDIR := obj-pc
BUSSRCS:= deppbus.cpp regdefs.cpp
SOURCES:= wbregs.cpp # flashload.cpp/ziprun.cpp
ADEPT := ../../../refs/digilent.adept.sdk_2.3.1
HEADERS:= deppbus.h devbus.h flashdrvr.h regdefs.h twoc.h
OBJECTS:= $(addprefix $(OBJDIR)/,$(subst .cpp,.o,$(SOURCES)))
BUSOBJS:= $(addprefix $(OBJDIR)/,$(subst .cpp,.o,$(BUSSRCS)))
CFLAGS := -g -Wall -I$(ADEPT)/inc -I.
LIBS := -L /usr/lib64/digilent/adept -ldmgr -ldepp
 
%.o: $(OBJDIR)/ $(OBJDIR)/%.o
$(OBJDIR)/%.o: %.cpp
$(CXX) $(CFLAGS) -c $< -o $@
 
.PHONY: clean
clean:
rm -rf $(OBJDIR)/ $(PROGRAMS)
 
wbregs: $(OBJDIR)/wbregs.o $(BUSOBJS)
$(CXX) $(CFLAGS) $^ $(LIBS) -o $@
 
define build-depends
@echo "Building dependency file(s)"
@$(CXX) $(CFLAGS) -MM $(SOURCES) > $(OBJDIR)/xdepends.txt
@sed -e 's/^.*.o: /$(OBJDIR)\/&/' < $(OBJDIR)/xdepends.txt > $(OBJDIR)/depends.txt
@rm $(OBJDIR)/xdepends.txt
endef
 
tags: $(SOURCES) $(HEADERS)
@ctags $(SOURCES) $(HEADERS)
 
.PHONY: depends
depends: tags
$(build-depends)
 
$(OBJDIR)/depends.txt: $(OBJDIR)/ $(SOURCES) $(HEADERS)
$(build-depends)
 
$(OBJDIR)/:
@bash -c "if [ ! -e $(OBJDIR) ]; then mkdir -p $(OBJDIR); fi"
 
-include $(OBJDIR)/depends.txt
/sw/host/devbus.h
0,0 → 1,144
////////////////////////////////////////////////////////////////////////////////
//
// Filename: devbus.h
//
// Project: XuLA2 board
//
// Purpose: The purpose of this file is to document an interface which
// any device with a bus, whether it be implemented over a UART,
// an ethernet, or a PCI express bus, must implement. This describes
// only an interface, and not how that interface is to be accomplished.
//
// The neat part of this interface is that, if programs are designed to
// work with it, than the implementation details may be changed later
// and any program that once worked with the interface should be able
// to continue to do so. (i.e., switch from a UART controlled bus to a
// PCI express controlled bus, with minimal change to the software of
// interest.)
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
//
#ifndef DEVBUS_H
#define DEVBUS_H
 
#include <stdio.h>
#include <unistd.h>
 
typedef unsigned int uint32;
 
class BUSERR {
public:
uint32 addr;
BUSERR(const uint32 a) : addr(a) {};
};
 
class DEVBUS {
public:
typedef uint32 BUSW;
 
virtual void kill(void) = 0;
virtual void close(void) = 0;
 
// Write a single value to a single address
// a is the address of the value to be read as it exists on the
// wishbone bus within the FPGA.
// v is the singular value to write to this address
virtual void writeio(const BUSW a, const BUSW v) = 0;
 
// Read a single value to a single address
// a is the address of the value to be read as it exists on the
// wishbone bus within the FPGA.
// This function returns the value read from the device wishbone
// at address a.
virtual BUSW readio(const BUSW a) = 0;
 
// Read a series of values from values from a block of memory
// a is the address of the value to be read as it exists on the
// wishbone bus within the FPGA.
// len is the number of words to read
// buf is a pointer to a place to store the words once read.
// This is equivalent to:
// for(int i=0; i<len; i++)
// buf[i] = readio(a+i);
// only it's faster in our implementation.
virtual void readi(const BUSW a, const int len, BUSW *buf) = 0;
 
// Read a series of values from the same address in memory. This
// call is identical to readi, save that the address is not incremented
// from one read to the next. It is equivalent to:
// for(int i=0; i<len; i++)
// buf[i] = readio(a);
// only it's faster in our implementation.
//
virtual void readz(const BUSW a, const int len, BUSW *buf) = 0;
 
// Write a series of values into a block of memory on the FPGA
// a is the address of the value to be written as it exists on the
// wishbone bus within the FPGA.
// len is the number of words to write
// buf is a pointer to a place to from whence to grab the data
// to be written.
// This is equivalent to:
// for(int i=0; i<len; i++)
// writeio(a+i, buf[i]);
// only it's faster in our implementation.
virtual void writei(const BUSW a, const int len, const BUSW *buf) = 0;
// Write a series of values into the same address on the FPGA bus. This
// call is identical to writei, save that the address is not incremented
// from one write to the next. It is equivalent to:
// for(int i=0; i<len; i++)
// writeio(a, buf[i]);
// only it's faster in our implementation.
//
virtual void writez(const BUSW a, const int len, const BUSW *buf) = 0;
 
// Query whether or not an interrupt has taken place
virtual bool poll(void) = 0;
 
// Sleep until interrupt, but sleep no longer than msec milliseconds
virtual void usleep(unsigned msec) = 0;
 
// Sleep until an interrupt, no matter how long it takes for that
// interrupt to take place
virtual void wait(void) = 0;
 
// Query whether or not a bus error has taken place. This is somewhat
// of a misnomer, as my current bus error detection code exits any
// interface, but ... it is what it is.
virtual bool bus_err(void) const = 0;
 
// Clear any bus error condition.
virtual void reset_err(void) = 0;
 
// Clear any interrupt condition that has already been noticed by
// the interface, does not check for further interrupt
virtual void clear(void) = 0;
 
virtual ~DEVBUS(void) { };
};
 
#endif
/Makefile
69,8 → 69,11
axload:
djtgcfg enum
djtgcfg init -d CmodS6
djtgcfg erase -d CmodS6 -i 0
djtgcfg prog -d CmodS6 -i 0 -f xilinx/alttop.bit
# Might also be able to do a ...
# djtgcfg erase -d CmodS6 -i 0
# but I can't speak to whether it would be useful or not.
 
xload:
djtgcfg init -d CmodS6
djtgcfg prog -d CmodS6 -i 0 -f xilinx/toplevel.bit
/cmod.ucf
69,18 → 69,18
NET "io_qspi_dat<3>" LOC="P10" | IOSTANDARD = LVCMOS33;
 
#DEPP Signals
# NET "DEPP_WAIT" LOC = "B6" | IOSTANDARD = LVCMOS33;
# NET "DEPP_ASTB" LOC = "A6" | IOSTANDARD = LVCMOS33;
# NET "DEPP_DSTB" LOC = "B7" | IOSTANDARD = LVCMOS33;
# NET "DEPP_WRITE" LOC = "A7" | IOSTANDARD = LVCMOS33;
# NET "DBUS<0>" LOC = "B9" | IOSTANDARD = LVCMOS33;
# NET "DBUS<1>" LOC = "A9" | IOSTANDARD = LVCMOS33;
# NET "DBUS<2>" LOC = "B10" | IOSTANDARD = LVCMOS33;
# NET "DBUS<3>" LOC = "A10" | IOSTANDARD = LVCMOS33;
# NET "DBUS<4>" LOC = "B11" | IOSTANDARD = LVCMOS33;
# NET "DBUS<5>" LOC = "A11" | IOSTANDARD = LVCMOS33;
# NET "DBUS<6>" LOC = "B12" | IOSTANDARD = LVCMOS33;
# NET "DBUS<7>" LOC = "A12" | IOSTANDARD = LVCMOS33;
NET "o_depp_wait" LOC = "B6" | IOSTANDARD = LVCMOS33;
NET "i_depp_astb_n" LOC = "A6" | IOSTANDARD = LVCMOS33;
NET "i_depp_dstb_n" LOC = "B7" | IOSTANDARD = LVCMOS33;
NET "i_depp_write_n" LOC = "A7" | IOSTANDARD = LVCMOS33;
NET "io_depp_data<0>" LOC = "B9" | IOSTANDARD = LVCMOS33;
NET "io_depp_data<1>" LOC = "A9" | IOSTANDARD = LVCMOS33;
NET "io_depp_data<2>" LOC = "B10" | IOSTANDARD = LVCMOS33;
NET "io_depp_data<3>" LOC = "A10" | IOSTANDARD = LVCMOS33;
NET "io_depp_data<4>" LOC = "B11" | IOSTANDARD = LVCMOS33;
NET "io_depp_data<5>" LOC = "A11" | IOSTANDARD = LVCMOS33;
NET "io_depp_data<6>" LOC = "B12" | IOSTANDARD = LVCMOS33;
NET "io_depp_data<7>" LOC = "A12" | IOSTANDARD = LVCMOS33;
 
#IO PORTs
 
137,6 → 137,16
NET "i_gpio<14>" LOC = "G2" | IOSTANDARD = LVCMOS33;
NET "i_gpio<15>" LOC = "J1" | IOSTANDARD = LVCMOS33;
 
NET "o_kp_col<0>" LOC = "J2" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "o_kp_col<1>" LOC = "K1" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "o_kp_col<2>" LOC = "P7" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "o_kp_col<3>" LOC = "D13" | IOSTANDARD = LVCMOS33 | PULLUP;
 
NET "i_kp_row<0>" LOC = "E13" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "i_kp_row<1>" LOC = "N5" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "i_kp_row<2>" LOC = "P12" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "i_kp_row<3>" LOC = "N6" | IOSTANDARD = LVCMOS33 | PULLUP;
 
# NET "PORTA<0>" LOC = "P5" | IOSTANDARD = LVCMOS33 | PULLUP; # PIO01, i_uart
# NET "PORTA<1>" LOC = "N5" | IOSTANDARD = LVCMOS33 | PULLUP; # PIO02, o_uart
# NET "PORTA<2>" LOC = "N6" | IOSTANDARD = LVCMOS33 | PULLUP; # PIO03, io_scl

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