URL
https://opencores.org/ocsvn/scan_based_serial_communication/scan_based_serial_communication/trunk
Subversion Repositories scan_based_serial_communication
Compare Revisions
- This comparison shows the changes necessary to convert path
/scan_based_serial_communication/trunk
- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/SCAN_README.txt
10,6 → 10,7
VERSION |
1.0 - June 27, 2010 |
1.1 - January 7, 2011 |
1.2 - Feb 7, 2013 |
|
SCAN DESCRIPTION |
This is a simple scan chain implemented with deperlify. It has been |
58,6 → 59,11
address and data bits should most likely match the total size |
in order to avoid bugs. |
|
An optional research field is included in the scan signal list. |
When the scan reset bet is set to 1, all bits in the scan chain |
are set to their optional reset value when specified, or zero |
when it is not specified. |
|
Due to the buffering latches, complex internal interfaces can be |
emulated using the scan chain. For instance, an SRAM could be |
connected to a clock, chip select, write enable, 64-bit data-in, |
102,4 → 108,4
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|
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/scan_signal_list.pl
22,10 → 22,10
|
|
{ size => 1, writable => 1, name => 'write_data_1'}, |
{ size => 2, writable => 1, name => 'write_data_2'}, |
{ size => 2, writable => 1, name => 'write_data_2', reset => 3}, |
{ size => 3, writable => 1, name => 'write_data_3'}, |
|
{ size => 16, writable => 1, name => 'write_data_array', addr_bits => 2, data_bits => 4}, |
{ size => 16, writable => 1, name => 'write_data_array', addr_bits => 2, data_bits => 4, reset => 0xAA55}, |
|
# Outputs - chip to outside |
{ size => 1, writable => 0, name => 'read_data_1'}, |
/scan_testbench.perl.v
199,11 → 199,17
load_chip(); |
|
// Make sure reset worked |
if (chip_internal_write_data_array !== 0) |
$display("RESET TEST FAILED"); |
else |
if (chip_internal_write_data_1 !== 1'd0 || |
chip_internal_write_data_2 !== 2'd3 || |
chip_internal_write_data_3 !== 3'd0 || |
chip_internal_write_data_array !== 16'hAA55 |
) begin |
$display("RESET TEST FAILED"); |
$finish; |
end else begin |
$display("RESET TEST PASSED"); |
|
end |
|
// Write each variable |
scan_reset = 1'b0; |
|
212,7 → 218,7
write_data_3 = 3'd3; |
|
write_data_array_addr = 2'd2; |
write_data_array_data = 4'hA; |
write_data_array_data = 4'hB; |
|
rotate_chain(); |
load_chip(); |
221,7 → 227,7
if (chip_internal_write_data_1 !== 1'd1 || |
chip_internal_write_data_2 !== 2'd2 || |
chip_internal_write_data_3 !== 3'd3 || |
chip_internal_write_data_array !== 15'h0A00) begin |
chip_internal_write_data_array !== 16'hAB55) begin |
$display("TEST 1 FAILED"); |
$display("%d %d %d %h", |
chip_internal_write_data_1, |
228,6 → 234,7
chip_internal_write_data_2, |
chip_internal_write_data_3, |
chip_internal_write_data_array); |
$finish; |
end else |
$display("TEST 1 PASSED"); |
|
262,6 → 269,7
read_data_2_read, |
read_data_3_read, |
read_data_array_data_read); |
$finish; |
end else |
$display("TEST 2 PASSED"); |
|
/scan.perl.v
130,8 → 130,9
|
my $name = $signal_list[$i]{name}; |
my $size = $signal_list[$i]{size}; |
my $addr_bits = $signal_list[$i]{addr_bits}; |
my $data_bits = $signal_list[$i]{data_bits}; |
my $addr_bits = 0 + $signal_list[$i]{addr_bits}; |
my $data_bits = 0 + $signal_list[$i]{data_bits}; |
my $reset = 0 + $signal_list[$i]{reset}; |
|
my $size_begin = $signal_list[$i]{start}; |
my $size_end = $size_begin + $size - 1; |
143,10 → 144,10
my $data_end = $data_begin + $data_bits - 1; |
|
if ($signal_list[$i]{addr_bits} == 0) { |
print " $name = scan_slave[$size_end:$size_begin];\n"; |
print " $name = scan_slave[$scan_reset_bit] ? ${size}'d${reset} : scan_slave[$size_end:$size_begin];\n"; |
} else { |
if ($scan_reset_exists) { |
print " if (scan_slave[$scan_reset_bit]) ${name} = ${size}'d0; else\n"; |
print " if (scan_slave[$scan_reset_bit]) ${name} = ${size}'d${reset}; else\n"; |
} |
print " case (scan_slave[$addr_end:$addr_begin])\n"; |
for (my $a = 0; ($a+1-1)*$data_bits < $size; $a++) { |