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URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

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    from Rev 37 to Rev 38
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Rev 37 → Rev 38

/sdr_ctrl/trunk/rtl/top/sdrc_top.v
60,7 → 60,7
`include "sdrc_define.v"
module sdrc_top
(
sdr_width ,
cfg_sdr_width ,
cfg_colbits ,
// WB bus
123,7 → 123,7
// ----------------------------------------------
input sdram_clk ; // SDRAM Clock
input sdram_resetn ; // Reset Signal
input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
input [1:0] cfg_sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address,
// 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
 
243,7 → 243,7
.clk (sdram_clk ) ,
.pad_clk (sdram_pad_clk ) ,
.reset_n (sdram_resetn ) ,
.sdr_width (sdr_width ) ,
.sdr_width (cfg_sdr_width ) ,
.cfg_colbits (cfg_colbits ) ,
 
/* Request from app */
/sdr_ctrl/trunk/verif/tb/tb_top.sv
115,11 → 115,11
`endif
// System
`ifdef SDR_32BIT
.sdr_width (2'b00 ), // 32 BIT SDRAM
.cfg_sdr_width (2'b00 ), // 32 BIT SDRAM
`elsif SDR_16BIT
.sdr_width (2'b01 ), // 16 BIT SDRAM
.cfg_sdr_width (2'b01 ), // 16 BIT SDRAM
`else
.sdr_width (2'b10 ), // 8 BIT SDRAM
.cfg_sdr_width (2'b10 ), // 8 BIT SDRAM
`endif
.cfg_colbits (2'b00 ), // 8 Bit Column Address
 

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