OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /sdr_ctrl/trunk/verif/tb
    from Rev 56 to Rev 68
    Reverse comparison

Rev 56 → Rev 68

/tb_core.sv
70,7 → 70,7
reg app_req ; // Application Request
reg [8:0] app_req_len ; // Burst Request length
wire app_req_ack ; // Application Request Ack
reg [24:0] app_req_addr ; // Application Address
reg [25:0] app_req_addr ; // Application Address
reg app_req_wr_n ; // 1 -> Read, 0 -> Write
reg [dw-1:0] app_wr_data ; // Write Data
reg [dw/8-1:0] app_wr_en_n ; // Write Enable, Active Low
104,7 → 104,7
`endif
 
wire [1:0] sdr_ba ; // SDRAM Bank Select
wire [11:0] sdr_addr ; // SDRAM ADRESS
wire [12:0] sdr_addr ; // SDRAM ADRESS
wire sdr_init_done ; // SDRAM Init Done
 
// to fix the sdram interface timing issue
187,7 → 187,7
assign Dq[31:24] = (sdr_den_n[3] == 1'b0) ? sdr_dout[31:24] : 8'hZZ;
mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
.Dq (Dq ) ,
.Addr (sdr_addr ),
.Addr (sdr_addr[11:0] ),
.Ba (sdr_ba ),
.Clk (sdram_clk_d ),
.Cke (sdr_cke ),
205,7 → 205,7
 
IS42VM16400K u_sdram16 (
.dq (Dq ),
.addr (sdr_addr ),
.addr (sdr_addr[11:0] ),
.ba (sdr_ba ),
.clk (sdram_clk_d ),
.cke (sdr_cke ),
221,7 → 221,7
 
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
.Dq (Dq ) ,
.Addr (sdr_addr ),
.Addr (sdr_addr[11:0] ),
.Ba (sdr_ba ),
.Clk (sdram_clk_d ),
.Cke (sdr_cke ),
/tb_top.sv
78,7 → 78,7
// -------------------------------------
reg wb_stb_i ;
wire wb_ack_o ;
reg [24:0] wb_addr_i ;
reg [25:0] wb_addr_i ;
reg wb_we_i ; // 1 - Write, 0 - Read
reg [dw-1:0] wb_dat_i ;
reg [dw/8-1:0] wb_sel_i ; // Byte enable
104,7 → 104,7
`endif
 
wire [1:0] sdr_ba ; // SDRAM Bank Select
wire [11:0] sdr_addr ; // SDRAM ADRESS
wire [12:0] sdr_addr ; // SDRAM ADRESS
wire sdr_init_done ; // SDRAM Init Done
 
// to fix the sdram interface timing issue
175,7 → 175,7
`ifdef SDR_32BIT
mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
.Dq (Dq ) ,
.Addr (sdr_addr ),
.Addr (sdr_addr[11:0] ),
.Ba (sdr_ba ),
.Clk (sdram_clk_d ),
.Cke (sdr_cke ),
190,7 → 190,7
 
IS42VM16400K u_sdram16 (
.dq (Dq ),
.addr (sdr_addr ),
.addr (sdr_addr[11:0] ),
.ba (sdr_ba ),
.clk (sdram_clk_d ),
.cke (sdr_cke ),
205,7 → 205,7
 
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
.Dq (Dq ) ,
.Addr (sdr_addr ),
.Addr (sdr_addr[11:0] ),
.Ba (sdr_ba ),
.Clk (sdram_clk_d ),
.Cke (sdr_cke ),

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.