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/rtl/top/sdrc_top.v
0,0 → 1,277
/*********************************************************************
SDRAM Controller top File
This file is part of the sdram controller project
http://www.opencores.org/cores/sdr_ctrl/
Description: SDRAM Controller Core Module
2 types of SDRAMs are supported, 1Mx16 2 bank, or 4Mx16 4 bank.
This block integrate following sub modules
 
sdrc_core
SDRAM Controller file
wb2sdrc
This module transalate the bus protocl from wishbone to custome
sdram controller
To Do:
nothing
Author(s): Dinesh Annayya, dinesha@opencores.org
Version : 1.0 - 8th Jan 2012
Initial version with 16/32 Bit SDRAM Support
: 1.1 - 24th Jan 2012
8 Bit SDRAM Support is added
 
Copyright (C) 2000 Authors and OPENCORES.ORG
This source file may be used and distributed without
restriction provided that this copyright statement is not
removed from the file and that any derivative work contains
the original copyright notice and the associated disclaimer.
This source file is free software; you can redistribute it
and/or modify it under the terms of the GNU Lesser General
Public License as published by the Free Software Foundation;
either version 2.1 of the License, or (at your option) any
later version.
This source is distributed in the hope that it will be
useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE. See the GNU Lesser General Public License for more
details.
You should have received a copy of the GNU Lesser General
Public License along with this source; if not, download it
from http://www.opencores.org/lgpl.shtml
*******************************************************************/
 
 
`include "sdrc.def"
module sdrc_top
(
sdr_width,
cfg_colbits,
 
// WB bus
wb_rst_i ,
wb_clk_i ,
 
wb_stb_i ,
wb_ack_o ,
wb_addr_i ,
wb_we_i ,
wb_dat_i ,
wb_sel_i ,
wb_dat_o ,
wb_cyc_i ,
wb_cti_i ,
 
/* Interface to SDRAMs */
sdram_clk,
sdram_pad_clk,
sdram_resetn,
sdr_cs_n,
sdr_cke,
sdr_ras_n,
sdr_cas_n,
sdr_we_n,
sdr_dqm,
sdr_ba,
sdr_addr,
pad_sdr_din,
sdr_dout,
sdr_den_n,
 
/* Parameters */
sdr_init_done,
cfg_req_depth, //how many req. buffer should hold
cfg_sdr_en,
cfg_sdr_mode_reg,
cfg_sdr_tras_d,
cfg_sdr_trp_d,
cfg_sdr_trcd_d,
cfg_sdr_cas,
cfg_sdr_trcar_d,
cfg_sdr_twr_d,
cfg_sdr_rfsh,
cfg_sdr_rfmax);
parameter APP_AW = 30; // Application Address Width
parameter APP_DW = 32; // Application Data Width
parameter APP_BW = 4; // Application Byte Width
parameter APP_RW = 9; // Application Request Width
 
parameter SDR_DW = 16; // SDR Data Width
parameter SDR_BW = 2; // SDR Byte Width
parameter dw = 32; // data width
parameter tw = 8; // tag id width
parameter bl = 9; // burst_lenght_width
 
//-----------------------------------------------
// Global Variable
// ----------------------------------------------
input sdram_clk ; // SDRAM Clock
input sdram_pad_clk ; // SDRAM Clock from Pad, used for registering Read Data
input sdram_resetn ; // Reset Signal
input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
 
//--------------------------------------
// Wish Bone Interface
// -------------------------------------
input wb_rst_i ;
input wb_clk_i ;
 
input wb_stb_i ;
output wb_ack_o ;
input [29:0] wb_addr_i ;
input wb_we_i ; // 1 - Write, 0 - Read
input [dw-1:0] wb_dat_i ;
input [dw/8-1:0]wb_sel_i ; // Byte enable
output [dw-1:0] wb_dat_o ;
input wb_cyc_i ;
input [2:0] wb_cti_i ;
 
//------------------------------------------------
// Interface to SDRAMs
//------------------------------------------------
output sdr_cke ; // SDRAM CKE
output sdr_cs_n ; // SDRAM Chip Select
output sdr_ras_n ; // SDRAM ras
output sdr_cas_n ; // SDRAM cas
output sdr_we_n ; // SDRAM write enable
output [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask
output [1:0] sdr_ba ; // SDRAM Bank Enable
output [11:0] sdr_addr ; // SDRAM Address
input [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input
output [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output
output [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable
 
//------------------------------------------------
// Configuration Parameter
//------------------------------------------------
output sdr_init_done ; // Indicate SDRAM Initialisation Done
input [3:0] cfg_sdr_tras_d ; // Active to precharge delay
input [3:0] cfg_sdr_trp_d ; // Precharge to active delay
input [3:0] cfg_sdr_trcd_d ; // Active to R/W delay
input cfg_sdr_en ; // Enable SDRAM controller
input [1:0] cfg_req_depth ; // Maximum Request accepted by SDRAM controller
input [11:0] cfg_sdr_mode_reg ;
input [2:0] cfg_sdr_cas ; // SDRAM CAS Latency
input [3:0] cfg_sdr_trcar_d ; // Auto-refresh period
input [3:0] cfg_sdr_twr_d ; // Write recovery delay
input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh;
input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
 
//--------------------------------------------
// SDRAM controller Interface
//--------------------------------------------
wire app_req ; // SDRAM request
wire [29:0] app_req_addr ; // SDRAM Request Address
wire [bl-1:0] app_req_len ;
wire app_req_wr_n ; // 0 - Write, 1 -> Read
wire app_req_ack ; // SDRAM request Accepted
wire app_busy_n ; // 0 -> sdr busy
wire [dw/8-1:0] app_wr_en_n ; // Active low sdr byte-wise write data valid
wire app_wr_next_req ; // Ready to accept the next write
wire app_rd_valid ; // sdr read valid
wire app_last_rd ; // Indicate last Read of Burst Transfer
wire [dw-1:0] app_wr_data ; // sdr write data
wire [dw-1:0] app_rd_data ; // sdr read data
 
wb2sdrc u_wb2sdrc (
// WB bus
.wb_rst_i (wb_rst_i ) ,
.wb_clk_i (wb_clk_i ) ,
 
.wb_stb_i (wb_stb_i ) ,
.wb_ack_o (wb_ack_o ) ,
.wb_addr_i (wb_addr_i ) ,
.wb_we_i (wb_we_i ) ,
.wb_dat_i (wb_dat_i ) ,
.wb_sel_i (wb_sel_i ) ,
.wb_dat_o (wb_dat_o ) ,
.wb_cyc_i (wb_cyc_i ) ,
.wb_cti_i (wb_cti_i ) ,
 
 
//SDRAM Controller Hand-Shake Signal
.sdram_clk (sdram_clk ) ,
.sdram_resetn (sdram_resetn ) ,
.sdr_req (app_req ) ,
.sdr_req_addr (app_req_addr ) ,
.sdr_req_len (app_req_len ) ,
.sdr_req_wr_n (app_req_wr_n ) ,
.sdr_req_ack (app_req_ack ) ,
.sdr_busy_n (app_busy_n ) ,
.sdr_wr_en_n (app_wr_en_n ) ,
.sdr_wr_next (app_wr_next_req ) ,
.sdr_rd_valid (app_rd_valid ) ,
.sdr_last_rd (app_last_rd ) ,
.sdr_wr_data (app_wr_data ) ,
.sdr_rd_data (app_rd_data )
 
);
 
 
sdrc_core #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_sdrc_core (
.clk (sdram_clk ) ,
.pad_clk (sdram_pad_clk ) ,
.reset_n (sdram_resetn ) ,
.sdr_width (sdr_width ) ,
.cfg_colbits (cfg_colbits ) ,
 
/* Request from app */
.app_req (app_req ) ,// Transfer Request
.app_req_addr (app_req_addr ) ,// SDRAM Address
.app_req_addr_mask (29'h0 ) ,// Address mask for queue wrap
.app_req_len (app_req_len ) ,// Burst Length (in 16 bit words)
.app_req_wrap (1'b0 ) ,// Wrap mode request
.app_req_wr_n (app_req_wr_n ) ,// 0 => Write request, 1 => read req
.app_req_ack (app_req_ack ) ,// Request has been accepted
.sdr_core_busy_n (app_core_busy_n ) ,// OK to arbitrate next request
.cfg_req_depth (cfg_req_depth ) ,//how many req. buffer should hold
.app_wr_data (app_wr_data ) ,
.app_wr_en_n (app_wr_en_n ) ,
.app_rd_data (app_rd_data ) ,
.app_rd_valid (app_rd_valid ) ,
.app_last_rd (app_last_rd ) ,
.app_wr_next_req (app_wr_next_req ) ,
.sdr_init_done (sdr_init_done ) ,
.app_req_dma_last (app_req ) ,
/* Interface to SDRAMs */
.sdr_cs_n (sdr_cs_n ) ,
.sdr_cke (sdr_cke ) ,
.sdr_ras_n (sdr_ras_n ) ,
.sdr_cas_n (sdr_cas_n ) ,
.sdr_we_n (sdr_we_n ) ,
.sdr_dqm (sdr_dqm ) ,
.sdr_ba (sdr_ba ) ,
.sdr_addr (sdr_addr ) ,
.pad_sdr_din (pad_sdr_din ) ,
.sdr_dout (sdr_dout ) ,
.sdr_den_n (sdr_den_n ) ,
/* Parameters */
.cfg_sdr_en (cfg_sdr_en ) ,
.cfg_sdr_mode_reg (cfg_sdr_mode_reg ) ,
.cfg_sdr_tras_d (cfg_sdr_tras_d ) ,
.cfg_sdr_trp_d (cfg_sdr_trp_d ) ,
.cfg_sdr_trcd_d (cfg_sdr_trcd_d ) ,
.cfg_sdr_cas (cfg_sdr_cas ) ,
.cfg_sdr_trcar_d (cfg_sdr_trcar_d ) ,
.cfg_sdr_twr_d (cfg_sdr_twr_d ) ,
.cfg_sdr_rfsh (cfg_sdr_rfsh ) ,
.cfg_sdr_rfmax (cfg_sdr_rfmax )
);
endmodule // sdrc_core
rtl/top/sdrc_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl/lib/sync_fifo.v =================================================================== --- rtl/lib/sync_fifo.v (nonexistent) +++ rtl/lib/sync_fifo.v (revision 31) @@ -0,0 +1,148 @@ +/********************************************************************* + + This file is part of the sdram controller project + http://www.opencores.org/cores/sdr_ctrl/ + + Description: SYNC FIFO + Parameters: + W : Width (integer) + D : Depth (integer, power of 2, 4 to 256) + + To Do: + nothing + + Author(s): Dinesh Annayya, dinesha@opencores.org + + Copyright (C) 2000 Authors and OPENCORES.ORG + + This source file may be used and distributed without + restriction provided that this copyright statement is not + removed from the file and that any derivative work contains + the original copyright notice and the associated disclaimer. + + This source file is free software; you can redistribute it + and/or modify it under the terms of the GNU Lesser General + Public License as published by the Free Software Foundation; + either version 2.1 of the License, or (at your option) any +later version. + + This source is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + PURPOSE. See the GNU Lesser General Public License for more + details. + + You should have received a copy of the GNU Lesser General + Public License along with this source; if not, download it + from http://www.opencores.org/lgpl.shtml + +*******************************************************************/ + + +module sync_fifo (clk, + reset_n, + wr_en, + wr_data, + full, + empty, + rd_en, + rd_data); + + parameter W = 8; + parameter D = 4; + + parameter AW = (D == 4) ? 2 : + (D == 8) ? 3 : + (D == 16) ? 4 : + (D == 32) ? 5 : + (D == 64) ? 6 : + (D == 128) ? 7 : + (D == 256) ? 8 : 0; + + output [W-1 : 0] rd_data; + input [W-1 : 0] wr_data; + input clk, reset_n, wr_en, rd_en; + output full, empty; + + // synopsys translate_off + + initial begin + if (AW == 0) begin + $display ("%m : ERROR!!! Fifo depth %d not in range 4 to 256", D); + end // if (AW == 0) + end // initial begin + + // synopsys translate_on + + + reg [W-1 : 0] mem[D-1 : 0]; + reg [AW-1 : 0] rd_ptr, wr_ptr; + reg full, empty; + + wire [W-1 : 0] rd_data; + + always @ (posedge clk or negedge reset_n) + if (reset_n == 1'b0) begin + wr_ptr <= {AW{1'b0}} ; + end + else begin + if (wr_en & !full) begin + wr_ptr <= wr_ptr + 1'b1 ; + end + end + + always @ (posedge clk or negedge reset_n) + if (reset_n == 1'b0) begin + rd_ptr <= {AW{1'b0}} ; + end + else begin + if (rd_en & !empty) begin + rd_ptr <= rd_ptr + 1'b1 ; + end + end + + + always @ (posedge clk or negedge reset_n) + if (reset_n == 1'b0) begin + empty <= 1'b1 ; + end + else begin + empty <= (((wr_ptr - rd_ptr) == {{(AW-1){1'b0}}, 1'b1}) & rd_en & ~wr_en) ? 1'b1 : + ((wr_ptr == rd_ptr) & ~rd_en & wr_en) ? 1'b0 : empty ; + end + + always @ (posedge clk or negedge reset_n) + if (reset_n == 1'b0) begin + full <= 1'b0 ; + end + else begin + full <= (((wr_ptr - rd_ptr) == {{(AW-1){1'b1}}, 1'b0}) & ~rd_en & wr_en) ? 1'b1 : + (((wr_ptr - rd_ptr) == {AW{1'b1}}) & rd_en & ~wr_en) ? 1'b0 : full ; + end + + always @ (posedge clk) + if (wr_en) + mem[wr_ptr] <= wr_data; + +assign rd_data = mem[rd_ptr]; + + +// synopsys translate_off + always @(posedge clk) begin + if (wr_en && full) begin + $display("%m : Error! sfifo overflow!"); + end + end + + always @(posedge clk) begin + if (rd_en && empty) begin + $display("%m : error! sfifo underflow!"); + end + end + +// synopsys translate_on +//--------------------------------------- + +endmodule + +
rtl/lib/sync_fifo.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl/lib/async_fifo.v =================================================================== --- rtl/lib/async_fifo.v (nonexistent) +++ rtl/lib/async_fifo.v (revision 31) @@ -0,0 +1,317 @@ +/********************************************************************* + + ASYNC FIFO + + This file is part of the sdram controller project + http://www.opencores.org/cores/sdr_ctrl/ + + Description: ASYNC FIFO + + To Do: + nothing + + Author(s): Dinesh Annayya, dinesha@opencores.org + + Copyright (C) 2000 Authors and OPENCORES.ORG + + This source file may be used and distributed without + restriction provided that this copyright statement is not + removed from the file and that any derivative work contains + the original copyright notice and the associated disclaimer. + + This source file is free software; you can redistribute it + and/or modify it under the terms of the GNU Lesser General + Public License as published by the Free Software Foundation; + either version 2.1 of the License, or (at your option) any +later version. + + This source is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + PURPOSE. See the GNU Lesser General Public License for more + details. + + You should have received a copy of the GNU Lesser General + Public License along with this source; if not, download it + from http://www.opencores.org/lgpl.shtml + +*******************************************************************/ + +//------------------------------------------- +// async FIFO +//----------------------------------------------- +`timescale 1ns/1ps + +module async_fifo (wr_clk, + wr_reset_n, + wr_en, + wr_data, + full, // sync'ed to wr_clk + afull, // sync'ed to wr_clk + rd_clk, + rd_reset_n, + rd_en, + empty, // sync'ed to rd_clk + aempty, // sync'ed to rd_clk + rd_data); + + parameter W = 4'd8; + parameter DP = 3'd4; + parameter WR_FAST = 1'b1; + parameter RD_FAST = 1'b1; + parameter FULL_DP = DP; + parameter EMPTY_DP = 1'b0; + + parameter AW = (DP == 2) ? 1 : + (DP == 4) ? 2 : + (DP == 8) ? 3 : + (DP == 16) ? 4 : + (DP == 32) ? 5 : + (DP == 64) ? 6 : + (DP == 128) ? 7 : + (DP == 256) ? 8 : 0; + + output [W-1 : 0] rd_data; + input [W-1 : 0] wr_data; + input wr_clk, wr_reset_n, wr_en, rd_clk, rd_reset_n, + rd_en; + output full, empty; + output afull, aempty; // about full and about to empty + + + // synopsys translate_off + + initial begin + if (AW == 0) begin + $display ("%m : ERROR!!! Fifo depth %d not in range 2 to 256", DP); + end // if (AW == 0) + end // initial begin + + // synopsys translate_on + + reg [W-1 : 0] mem[DP-1 : 0]; + + /*********************** write side ************************/ + reg [AW:0] sync_rd_ptr_0, sync_rd_ptr_1; + wire [AW:0] sync_rd_ptr; + reg [AW:0] wr_ptr, grey_wr_ptr; + reg [AW:0] grey_rd_ptr; + reg full_q; + wire full_c; + wire afull_c; + wire [AW:0] wr_ptr_inc = wr_ptr + 1'b1; + wire [AW:0] wr_cnt = get_cnt(wr_ptr, sync_rd_ptr); + + assign full_c = (wr_cnt == FULL_DP) ? 1'b1 : 1'b0; + assign afull_c = (wr_cnt == FULL_DP-1) ? 1'b1 : 1'b0; + + + always @(posedge wr_clk or negedge wr_reset_n) begin + if (!wr_reset_n) begin + wr_ptr <= 0; + grey_wr_ptr <= 0; + full_q <= 0; + end + else if (wr_en) begin + wr_ptr <= wr_ptr_inc; + grey_wr_ptr <= bin2grey(wr_ptr_inc); + if (wr_cnt == (FULL_DP-1)) begin + full_q <= 1'b1; + end + end + else begin + if (full_q && (wr_cnt= rd_ptr) begin + get_cnt = (wr_ptr - rd_ptr); + end + else begin + get_cnt = DP*2 - (rd_ptr - wr_ptr); + end +end +endfunction + +// synopsys translate_off +always @(posedge wr_clk) begin + if (wr_en && full) begin + $display($time, "%m Error! afifo overflow!"); + $stop; + end +end + +always @(posedge rd_clk) begin + if (rd_en && empty) begin + $display($time, "%m error! afifo underflow!"); + $stop; + end +end +// synopsys translate_on + +endmodule
rtl/lib/async_fifo.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl/wb2sdrc/wb2sdrc.v =================================================================== --- rtl/wb2sdrc/wb2sdrc.v (nonexistent) +++ rtl/wb2sdrc/wb2sdrc.v (revision 31) @@ -0,0 +1,287 @@ +/********************************************************************* + + This file is part of the sdram controller project + http://www.opencores.org/cores/sdr_ctrl/ + + Description: WISHBONE to SDRAM Controller Bus Transalator + This module translate the WISHBONE protocol to custom sdram controller i/f + + To Do: + nothing + + Author(s): Dinesh Annayya, dinesha@opencores.org + + Copyright (C) 2000 Authors and OPENCORES.ORG + + This source file may be used and distributed without + restriction provided that this copyright statement is not + removed from the file and that any derivative work contains + the original copyright notice and the associated disclaimer. + + This source file is free software; you can redistribute it + and/or modify it under the terms of the GNU Lesser General + Public License as published by the Free Software Foundation; + either version 2.1 of the License, or (at your option) any +later version. + + This source is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + PURPOSE. See the GNU Lesser General Public License for more + details. + + You should have received a copy of the GNU Lesser General + Public License along with this source; if not, download it + from http://www.opencores.org/lgpl.shtml + +*******************************************************************/ + + +module wb2sdrc ( + // WB bus + wb_rst_i , + wb_clk_i , + + wb_stb_i , + wb_ack_o , + wb_addr_i , + wb_we_i , + wb_dat_i , + wb_sel_i , + wb_dat_o , + wb_cyc_i , + wb_cti_i , + + + //SDRAM Controller Hand-Shake Signal + sdram_clk , + sdram_resetn , + sdr_req , + sdr_req_addr , + sdr_req_len , + sdr_req_wr_n , + sdr_req_ack , + sdr_busy_n , + sdr_wr_en_n , + sdr_wr_next , + sdr_rd_valid , + sdr_last_rd , + sdr_wr_data , + sdr_rd_data + + ); + +parameter dw = 32; // data width +parameter tw = 8; // tag id width +parameter bl = 9; // burst_lenght_width +//-------------------------------------- +// Wish Bone Interface +// ------------------------------------- +input wb_rst_i ; +input wb_clk_i ; + +input wb_stb_i ; +output wb_ack_o ; +input [29:0] wb_addr_i ; +input wb_we_i ; // 1 - Write, 0 - Read +input [dw-1:0] wb_dat_i ; +input [dw/8-1:0]wb_sel_i ; // Byte enable +output [dw-1:0] wb_dat_o ; +input wb_cyc_i ; +input [2:0] wb_cti_i ; +/*************************************************** +The Cycle Type Idenfier [CTI_IO()] Address Tag provides +additional information about the current cycle. +The MASTER sends this information to the SLAVE. The SLAVE can use this +information to prepare the response for the next cycle. +Table 4-2 Cycle Type Identifiers +CTI_O(2:0) Description +000 Classic cycle. +001 Constant address burst cycle +010 Incrementing burst cycle +011 Reserved +100 Reserved +101 Reserved +110 Reserved +111 End-of-Burst +****************************************************/ +//-------------------------------------------- +// SDRAM controller Interface +//-------------------------------------------- +input sdram_clk ; // sdram clock +input sdram_resetn ; // sdram reset +output sdr_req ; // SDRAM request +output [29:0] sdr_req_addr ; // SDRAM Request Address +output [bl-1:0] sdr_req_len ; +output sdr_req_wr_n ; // 0 - Write, 1 -> Read +input sdr_req_ack ; // SDRAM request Accepted +input sdr_busy_n ; // 0 -> sdr busy +output [dw/8-1:0] sdr_wr_en_n ; // Active low sdr byte-wise write data valid +input sdr_wr_next ; // Ready to accept the next write +input sdr_rd_valid ; // sdr read valid +input sdr_last_rd ; // Indicate last Read of Burst Transfer +output [dw-1:0] sdr_wr_data ; // sdr write data +input [dw-1:0] sdr_rd_data ; // sdr read data + +//---------------------------------------------------- +// Wire Decleration +// --------------------------------------------------- +wire cmdfifo_full; +wire cmdfifo_empty; +wire wrdatafifo_full; +wire wrdatafifo_empty; +wire tagfifo_full; +wire tagfifo_empty; +wire rddatafifo_empty; +wire rddatafifo_full; + +reg pending_read; + + +// Generate Address Enable only when internal fifo (Address + data are not full + +assign wb_ack_o = (wb_stb_i && wb_cyc_i && wb_we_i) ? // Write Phase + ((!cmdfifo_full) && (!wrdatafifo_full)) : + (wb_stb_i && wb_cyc_i && !wb_we_i) ? // Read Phase + !rddatafifo_empty : 1'b0; + +// Accept the cmdfifo only when burst start + address enable + address +// valid is asserted +wire cmdfifo_wr = (wb_stb_i && wb_cyc_i && wb_we_i) ? wb_ack_o : + (wb_stb_i && wb_cyc_i && !wb_we_i) ? !pending_read: 1'b0 ; +wire cmdfifo_rd = sdr_req_ack; +assign sdr_req = !cmdfifo_empty; + +wire [bl-1:0] burst_length = 1; // 0 Mean 1 Transfer + +always @(posedge wb_rst_i or posedge wb_clk_i) begin + if(wb_rst_i) begin + pending_read <= 1'b0; + end else begin + pending_read <= wb_stb_i & wb_cyc_i & !wb_we_i & !wb_ack_o; + end +end + + // Address + Burst Length + W/R Request + async_fifo #(.W(30+bl+1),.DP(4)) u_cmdfifo ( + // Write Path Sys CLock Domain + .wr_clk (wb_clk_i), + .wr_reset_n (!wb_rst_i), + .wr_en (cmdfifo_wr), + .wr_data ({burst_length, + !wb_we_i, + wb_addr_i}), + .afull (), + .full (cmdfifo_full), + + // Read Path, SDRAM clock domain + .rd_clk (sdram_clk), + .rd_reset_n (sdram_resetn), + .aempty (), + .empty (cmdfifo_empty), + .rd_en (cmdfifo_rd), + .rd_data ({sdr_req_len, + sdr_req_wr_n, + sdr_req_addr}) + ); + +// synopsys translate_off +always @(posedge wb_clk_i) begin + if (cmdfifo_full == 1'b1 && cmdfifo_wr == 1'b1) begin + $display("ERROR:%m COMMAND FIFO WRITE OVERFLOW"); + end +end +// synopsys translate_off +always @(posedge sdram_clk) begin + if (cmdfifo_empty == 1'b1 && cmdfifo_rd == 1'b1) begin + $display("ERROR:%m COMMAND FIFO READ OVERFLOW"); + end +end +// synopsys translate_on + + +wire wrdatafifo_wr = wb_ack_o & wb_we_i ; +wire wrdatafifo_rd = sdr_wr_next; + + + // Write DATA + Data Mask FIFO + async_fifo #(.W(dw+(dw/8)), .DP(16)) u_wrdatafifo ( + // Write Path , System clock domain + .wr_clk (wb_clk_i), + .wr_reset_n (!wb_rst_i), + .wr_en (wrdatafifo_wr), + .wr_data ({~wb_sel_i, + wb_dat_i}), + .afull (), + .full (wrdatafifo_full), + + + // Read Path , SDRAM clock domain + .rd_clk (sdram_clk), + .rd_reset_n (sdram_resetn), + .aempty (), + .empty (wrdatafifo_empty), + .rd_en (wrdatafifo_rd), + .rd_data ({sdr_wr_en_n, + sdr_wr_data}) + ); +// synopsys translate_off +always @(posedge wb_clk_i) begin + if (wrdatafifo_full == 1'b1 && wrdatafifo_wr == 1'b1) begin + $display("ERROR:%m WRITE DATA FIFO WRITE OVERFLOW"); + end +end + +always @(posedge sdram_clk) begin + if (wrdatafifo_empty == 1'b1 && wrdatafifo_rd == 1'b1) begin + $display("ERROR:%m WRITE DATA FIFO READ OVERFLOW"); + end +end +// synopsys translate_on + +// ------------------------------------------------------------------- +// READ DATA FIFO +// ------------------------------------------------------------------ +wire rd_eop; // last read indication +wire rddatafifo_wr = sdr_rd_valid; +wire rddatafifo_rd = wb_ack_o & !wb_we_i & (rddatafifo_empty == 0); + + // READ DATA FIFO depth is kept small, assuming that Sys-CLock > SDRAM Clock + // READ DATA + EOP + async_fifo #(.W(dw+1), .DP(4)) u_rddatafifo ( + // Write Path , SDRAM clock domain + .wr_clk (sdram_clk), + .wr_reset_n (sdram_resetn), + .wr_en (rddatafifo_wr), + .wr_data ({sdr_last_rd, + sdr_rd_data}), + .afull (), + .full (rddatafifo_full), + + + // Read Path , SYS clock domain + .rd_clk (wb_clk_i), + .rd_reset_n (!wb_rst_i), + .empty (rddatafifo_empty), + .aempty (), + .rd_en (rddatafifo_rd), + .rd_data ({rd_eop, + wb_dat_o}) + ); + +// synopsys translate_off +always @(posedge sdram_clk) begin + if (rddatafifo_full == 1'b1 && rddatafifo_wr == 1'b1) begin + $display("ERROR:%m READ DATA FIFO WRITE OVERFLOW"); + end +end + +always @(posedge wb_clk_i) begin + if (rddatafifo_empty == 1'b1 && rddatafifo_rd == 1'b1) begin + $display("ERROR:%m READ DATA FIFO READ OVERFLOW"); + end +end +// synopsys translate_on + + +endmodule
rtl/wb2sdrc/wb2sdrc.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl/core/sdrc_bs_convert.v =================================================================== --- rtl/core/sdrc_bs_convert.v (revision 30) +++ rtl/core/sdrc_bs_convert.v (revision 31) @@ -216,7 +216,8 @@ saved_rd_data <= 24'h0; end else begin - lcl_mc_req_wr_n <= app_req_wr_n; + if(app_req_ack) + lcl_mc_req_wr_n <= app_req_wr_n; // During Write Phase if(app_req_ack && (app_req_wr_n == 0)) begin
/rtl/core/sdrc_core.v
90,6 → 90,7
app_wr_en_n,
app_rd_data,
app_rd_valid,
app_last_rd,
app_wr_next_req,
sdr_init_done,
app_req_dma_last,
154,6 → 155,7
input [APP_BW-1:0] app_wr_en_n ; // Byte wise Write Enable
output [APP_DW-1:0] app_rd_data ; // Read Data
output app_rd_valid ; // Read Valid
output app_last_rd ; // Last Read Transfer of a given Burst
//------------------------------------------------
// Interface to SDRAMs
215,7 → 217,7
wire x2b_ack;
wire [3:0] x2b_pre_ok;
wire x2b_refresh, x2b_act_ok, x2b_rdok, x2b_wrok;
wire xfr_rdstart, xfr_rdlast;
wire xfr_rdstart, app_last_rd;
wire xfr_wrstart, xfr_wrlast;
wire [`SDR_REQ_ID_W-1:0]xfr_id;
wire [APP_DW-1:0] app_rd_data;
419,7 → 421,7
.x2a_rdstart (xfr_rdstart ),
.x2a_wrstart (xfr_wrstart ),
.x2a_id (xfr_id ),
.x2a_rdlast (xfr_rdlast ),
.x2a_rdlast (app_last_rd ),
.x2a_wrlast (xfr_wrlast ),
.app_wrdt (add_wr_data_int ),
.app_wren_n (app_wr_en_n_int ),

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