URL
https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
Subversion Repositories sdr_ctrl
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- This comparison shows the changes necessary to convert path
/sdr_ctrl
- from Rev 40 to Rev 39
- ↔ Reverse comparison
Rev 40 → Rev 39
/trunk/rtl/wb2sdrc/wb2sdrc.v
11,13 → 11,9
nothing |
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Author(s): Dinesh Annayya, dinesha@opencores.org |
Version : 0.0 - Initial Release |
0.1 - 2nd Feb 2012 |
Async Fifo towards the application layer is selected with Registered Full Generation |
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Copyright (C) 2000 Authors and OPENCORES.ORG |
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This source file may be used and distributed without |
restriction provided that this copyright statement is not |
removed from the file and that any derivative work contains |
207,7 → 203,7
// Application layer to SDRAM Controller |
// ------------------------------------------------------------------ |
// Address + Burst Length + W/R Request |
async_fifo #(.W(30+bl+1),.DP(4),.WR_FAST(1'b0), .RD_FAST(1'b1)) u_cmdfifo ( |
async_fifo #(.W(30+bl+1),.DP(4)) u_cmdfifo ( |
// Write Path Sys CLock Domain |
.wr_clk (wb_clk_i ), |
.wr_reset_n (!wb_rst_i ), |
265,7 → 261,7
//------------------------------------------------------------------------ |
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// Write DATA + Data Mask FIFO |
async_fifo #(.W(dw+(dw/8)), .DP(8), .WR_FAST(1'b0), .RD_FAST(1'b1)) u_wrdatafifo ( |
async_fifo #(.W(dw+(dw/8)), .DP(16)) u_wrdatafifo ( |
// Write Path , System clock domain |
.wr_clk (wb_clk_i ), |
.wr_reset_n (!wb_rst_i ), |
325,7 → 321,7
// Tag handling per burst |
// |
// ------------------------------------------------------------------------ |
async_fifo #(.W(dw+1), .DP(4), .WR_FAST(1'b0), .RD_FAST(1'b1) ) u_rddatafifo ( |
async_fifo #(.W(dw+1), .DP(4)) u_rddatafifo ( |
// Write Path , SDRAM clock domain |
.wr_clk (sdram_clk ), |
.wr_reset_n (sdram_resetn ), |