URL
https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
Subversion Repositories sdr_ctrl
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdr_ctrl/trunk/rtl/core
- from Rev 31 to Rev 33
- ↔ Reverse comparison
Rev 31 → Rev 33
/sdrc_req_gen.v
6,29 → 6,27
http://www.opencores.org/cores/sdr_ctrl/ |
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Description: SDRAM Controller Reguest Generation |
The 2Mx32 SDRAM is addressed by a 21 bit address, |
each loation is 32 bits wide. |
This 21 bit address is mapped as follows: |
ADDR [7:0] : Column Address (256 columns) |
ADDR [18:8] : Row Address (2K Rows) |
ADDR [20:19] : Bank Address (2 banks) |
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The 4Mx16 SDRAM is addressed by a 22 bit address, |
each loation is 16 bits wide. |
This 22 bit address is mapped as follows: |
ADDR [7:0] : Column Address (256 columns) |
ADDR [21:10] : Row Address (4K Rows) |
ADDR [21:20] : Bank Address (4 banks) |
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The 8Mx16 SDRAM is addressed by a 23 bit address, |
each loation is 16 bits wide. |
This 23 bit address is mapped as follows: |
ADDR [8:0] : Column Address (512 columns) |
ADDR [20:9] : Row Address (4K Rows) |
ADDR [22:21] : Bank Address (4 banks) |
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Address Generation Based on cfg_colbits |
cfg_colbits= 2'b00 |
Address[7:0] - Column Address |
Address[9:8] - Bank Address |
Address[21:10] - Row Address |
cfg_colbits= 2'b01 |
Address[8:0] - Column Address |
Address[10:9] - Bank Address |
Address[22:11] - Row Address |
cfg_colbits= 2'b10 |
Address[9:0] - Column Address |
Address[11:10] - Bank Address |
Address[23:12] - Row Address |
cfg_colbits= 2'b11 |
Address[10:0] - Column Address |
Address[12:11] - Bank Address |
Address[24:13] - Row Address |
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The SDRAMs are operated in 4 beat burst mode. |
This module takes requests from the mc, |
This module takes requests from the memory controller, |
chops them to page boundaries if wrap=0, |
and passes the request to bank_ctl |
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/sdrc_core.v
10,7 → 10,7
This block integrate following sub modules |
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sdrc_bs_convert |
convert the system side 32 bit into equvailent 16/32 SDR format |
convert the system side 32 bit into equvailent 8/16/32 SDR format |
sdrc_req_gen |
This module takes requests from the app, chops them to burst booundaries |
if wrap=0, decodes the bank and passe the request to bank_ctl |
446,6 → 446,14
.rfsh_rmax (cfg_sdr_rfmax ) |
); |
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/****************************************************************************/ |
// Instantiate sdr_bs_convert |
// This model handle the bus with transaltion from application layer to |
// 8/16/32 SDRAM Memory format |
// During Write Phase, this block split the data as per SDRAM Width |
// During Read Phase, This block does the re-packing based on SDRAM |
// Width |
//--------------------------------------------------------------------------- |
sdrc_bs_convert #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_bs_convert ( |
.clk (clk ), |
.reset_n (reset_n ), |