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URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

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  • This comparison shows the changes necessary to convert path
    /sdr_ctrl/trunk/rtl/core
    from Rev 9 to Rev 13
    Reverse comparison

Rev 9 → Rev 13

/sdrc_req_gen.v
82,6 → 82,7
req_ack, // Request has been accepted
sdr_core_busy_n, // SDRAM Core Busy Indication
sdr_dev_config, // sdram configuration
cfg_colbits,
/* Req to bank_ctl */
r2x_idle,
109,6 → 110,7
parameter SDR_BW = 2; // SDR Byte Width
 
input clk, reset_n;
input [1:0] cfg_colbits; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
 
/* Request from app */
input req;
165,8 → 167,9
// accesses within the space for a Q. When splitting and calculating the next
// address only the LSBs are incremented, the MSBs remain = req_addr.
//
assign max_r2b_len = (sdr_width == 1'b0) ? ((sdr_dev_config == `SDR_CONFIG_IS_32M) ? (12'h200 - r2b_caddr) : (12'h100 - r2b_caddr)) :
(sdr_dev_config == `SDR_CONFIG_IS_8M) ? (12'h100 - r2b_caddr) : (12'h200 - r2b_caddr);
assign max_r2b_len = (cfg_colbits == 2'b00) ? (12'h100 - r2b_caddr) :
(cfg_colbits == 2'b01) ? (12'h200 - r2b_caddr) :
(cfg_colbits == 2'b10) ? (12'h400 - r2b_caddr) : (12'h800 - r2b_caddr);
 
assign page_ovflw = ({1'b0, lcl_req_len} > max_r2b_len) ? ~lcl_wrap : 1'b0;
 
245,31 → 248,26
//
// addrs bits for the bank, row and column
//
// SDR_CONFIG_IS_8M 2'b00
// SDR_CONFIG_IS_16M 2'b01
// SDR_CONFIG_IS_32M 2'b10
// SDR_CONFIG_IS_LGCY 2'b11
//
assign r2b_ba = ({sdr_width,sdr_dev_config} == {1'b0,`SDR_CONFIG_IS_8M}) ? curr_sdr_addr[20:19] :
({sdr_width,sdr_dev_config} == {1'b0,`SDR_CONFIG_IS_16M}) ? curr_sdr_addr[21:20] :
({sdr_width,sdr_dev_config} == {1'b0,`SDR_CONFIG_IS_32M}) ? curr_sdr_addr[22:21] :
({sdr_width,sdr_dev_config} == {1'b1,`SDR_CONFIG_IS_8M}) ? curr_sdr_addr[21:20] :
({sdr_width,sdr_dev_config} == {1'b1,`SDR_CONFIG_IS_16M}) ? curr_sdr_addr[22:21]:
({sdr_width,sdr_dev_config} == {1'b1,`SDR_CONFIG_IS_32M}) ? curr_sdr_addr[23:22] : curr_sdr_addr[9:8];
 
assign r2b_caddr = ({sdr_width,sdr_dev_config} == {1'b0,`SDR_CONFIG_IS_8M}) ? {4'b0, curr_sdr_addr[7:0]} :
({sdr_width,sdr_dev_config} == {1'b0,`SDR_CONFIG_IS_16M}) ? {4'b0, curr_sdr_addr[7:0]} :
({sdr_width,sdr_dev_config} == {1'b0,`SDR_CONFIG_IS_32M}) ? {3'b0, curr_sdr_addr[8:0]} :
({sdr_width,sdr_dev_config} == {1'b1,`SDR_CONFIG_IS_8M}) ? {3'b0, curr_sdr_addr[7:0]} :
({sdr_width,sdr_dev_config} == {1'b1,`SDR_CONFIG_IS_16M}) ? {3'b0, curr_sdr_addr[8:0]} :
({sdr_width,sdr_dev_config} == {1'b1,`SDR_CONFIG_IS_32M}) ? {2'b0, curr_sdr_addr[8:0]} : {4'b0, curr_sdr_addr[7:0]};
// Bank Bits are always - 2 Bits
assign r2b_ba = (cfg_colbits == 2'b00) ? {curr_sdr_addr[9:8]} :
(cfg_colbits == 2'b01) ? {curr_sdr_addr[10:9]} :
(cfg_colbits == 2'b10) ? {curr_sdr_addr[11:10]} : curr_sdr_addr[12:11];
 
assign r2b_raddr = ({sdr_width,sdr_dev_config} == {1'b0,`SDR_CONFIG_IS_8M}) ? {1'b0, curr_sdr_addr[18:8]} :
({sdr_width,sdr_dev_config} == {1'b0,`SDR_CONFIG_IS_16M}) ? curr_sdr_addr[19:8] :
({sdr_width,sdr_dev_config} == {1'b0,`SDR_CONFIG_IS_32M}) ? curr_sdr_addr[20:9] :
({sdr_width,sdr_dev_config} == {1'b1,`SDR_CONFIG_IS_8M}) ? {1'b0,curr_sdr_addr[19:8]} :
({sdr_width,sdr_dev_config} == {1'b1,`SDR_CONFIG_IS_16M}) ? curr_sdr_addr[20:9] :
({sdr_width,sdr_dev_config} == {1'b1,`SDR_CONFIG_IS_32M}) ? curr_sdr_addr[21:9] : {1'b0, curr_sdr_addr[20:10]};
/********************
* Colbits Mapping:
* 2'b00 - 8 Bit
* 2'b01 - 16 Bit
* 2'b10 - 10 Bit
* 2'b11 - 11 Bits
************************/
assign r2b_caddr = (cfg_colbits == 2'b00) ? {4'b0, curr_sdr_addr[7:0]} :
(cfg_colbits == 2'b01) ? {3'b0, curr_sdr_addr[8:0]} :
(cfg_colbits == 2'b10) ? {2'b0, curr_sdr_addr[9:0]} : {1'b0, curr_sdr_addr[10:0]};
 
assign r2b_raddr = (cfg_colbits == 2'b00) ? curr_sdr_addr[21:10] :
(cfg_colbits == 2'b01) ? curr_sdr_addr[22:11] :
(cfg_colbits == 2'b10) ? curr_sdr_addr[23:12] : curr_sdr_addr[24:13];
endmodule // sdr_req_gen
/sdrc_core.v
71,6 → 71,7
pad_clk,
reset_n,
sdr_width,
cfg_colbits,
 
/* Request from app */
app_req, // Transfer Request
133,7 → 134,9
input pad_clk ; // SDRAM Clock from Pad, used for registering Read Data
input reset_n ; // Reset Signal
input sdr_width ; // 0 - 32 Bit SDR, 1 - 16 Bit SDR
input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
 
 
//------------------------------------------------
// Request from app
//------------------------------------------------
169,18 → 172,18
//------------------------------------------------
// Configuration Parameter
//------------------------------------------------
output sdr_init_done ;
input [3:0] cfg_sdr_tras_d ;
input [3:0] cfg_sdr_trp_d ;
input [3:0] cfg_sdr_trcd_d ;
input cfg_sdr_en ;
output sdr_init_done ; // Indicate SDRAM Initialisation Done
input [3:0] cfg_sdr_tras_d ; // Active to precharge delay
input [3:0] cfg_sdr_trp_d ; // Precharge to active delay
input [3:0] cfg_sdr_trcd_d ; // Active to R/W delay
input cfg_sdr_en ; // Enable SDRAM controller
input [1:0] cfg_sdr_dev_config ; // 2'b00 - 8 MB, 01 - 16 MB, 10 - 32 MB , 11 - 64 MB
input [1:0] cfg_req_depth ;
input [APP_RW-1:0] app_req_len ;
input [1:0] cfg_req_depth ; // Maximum Request accepted by SDRAM controller
input [APP_RW-1:0] app_req_len ; // Application Burst Request length in 32 bit
input [11:0] cfg_sdr_mode_reg ;
input [2:0] cfg_sdr_cas ;
input [3:0] cfg_sdr_trcar_d ;
input [3:0] cfg_sdr_twr_d ;
input [2:0] cfg_sdr_cas ; // SDRAM CAS Latency
input [3:0] cfg_sdr_trcar_d ; // Auto-refresh period
input [3:0] cfg_sdr_twr_d ; // Write recovery delay
input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh;
input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
input app_req_dma_last; // this signal should close the bank
269,6 → 272,7
.clk (clk ),
.reset_n (reset_n ),
.sdr_dev_config (cfg_sdr_dev_config ),
.cfg_colbits (cfg_colbits ),
 
/* Request from app */
.r2x_idle (r2x_idle ),
/sdrc.def
27,6 → 27,6
`define SDR_CONFIG_IS_8M 2'b00
`define SDR_CONFIG_IS_16M 2'b01
`define SDR_CONFIG_IS_32M 2'b10
`define SDR_CONFIG_IS_LGCY 2'b11
`define SDR_CONFIG_IS_64M 2'b11
 
 

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