URL
https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
Subversion Repositories sdr_ctrl
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdr_ctrl/trunk/verif/log
- from Rev 28 to Rev 37
- ↔ Reverse comparison
Rev 28 → Rev 37
/top_SDR_16BIT_basic_test1.log
1131,5 → 1131,5
############################### |
# STATUS: SDRAM Write/Read TEST PASSED |
############################### |
# ** Note: $finish : ../tb/tb_top.sv(304) |
# ** Note: $finish : ../tb/tb_top.sv(283) |
# Time: 73460 ns Iteration: 0 Instance: /tb_top |
/top_sdr8_sim.log
1465,7 → 1465,7
############################### |
# STATUS: SDRAM Write/Read TEST PASSED |
############################### |
# ** Note: $finish : ../tb/tb_top.sv(304) |
# ** Note: $finish : ../tb/tb_top.sv(283) |
# Time: 77860 ns Iteration: 0 Instance: /tb_top |
### test 1: basic_test1 --> PASSED |
########################################### |
/top_SDR_8BIT_basic_test1.log
1438,5 → 1438,5
############################### |
# STATUS: SDRAM Write/Read TEST PASSED |
############################### |
# ** Note: $finish : ../tb/tb_top.sv(304) |
# ** Note: $finish : ../tb/tb_top.sv(283) |
# Time: 77860 ns Iteration: 0 Instance: /tb_top |
/top_sdr32_sim.log
52,7 → 52,7
# Loading work.sdrc_xfr_ctl |
# Loading work.sdrc_bs_convert |
# Loading work.mt48lc2m32b2 |
# ** Warning: (vsim-3015) ../tb/tb_top.sv(199): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42). |
# ** Warning: (vsim-3015) ../tb/tb_top.sv(182): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42). |
# Region: /tb_top/u_sdram32 |
# do run.do |
# tb_top.u_sdram32 : at time 10212.0 ns AREF : Auto Refresh |
760,7 → 760,7
############################### |
# STATUS: SDRAM Write/Read TEST PASSED |
############################### |
# ** Note: $finish : ../tb/tb_top.sv(304) |
# ** Note: $finish : ../tb/tb_top.sv(283) |
# Time: 71260 ns Iteration: 0 Instance: /tb_top |
### test 1: basic_test1 --> PASSED |
########################################### |
/top_sdr16_sim.log
1158,7 → 1158,7
############################### |
# STATUS: SDRAM Write/Read TEST PASSED |
############################### |
# ** Note: $finish : ../tb/tb_top.sv(304) |
# ** Note: $finish : ../tb/tb_top.sv(283) |
# Time: 73460 ns Iteration: 0 Instance: /tb_top |
### test 1: basic_test1 --> PASSED |
########################################### |
/top_SDR_32BIT_basic_test1.log
25,7 → 25,7
# Loading work.sdrc_xfr_ctl |
# Loading work.sdrc_bs_convert |
# Loading work.mt48lc2m32b2 |
# ** Warning: (vsim-3015) ../tb/tb_top.sv(199): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42). |
# ** Warning: (vsim-3015) ../tb/tb_top.sv(182): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42). |
# Region: /tb_top/u_sdram32 |
# do run.do |
# tb_top.u_sdram32 : at time 10212.0 ns AREF : Auto Refresh |
733,5 → 733,5
############################### |
# STATUS: SDRAM Write/Read TEST PASSED |
############################### |
# ** Note: $finish : ../tb/tb_top.sv(304) |
# ** Note: $finish : ../tb/tb_top.sv(283) |
# Time: 71260 ns Iteration: 0 Instance: /tb_top |