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URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

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  • This comparison shows the changes necessary to convert path
    /sdr_ctrl/trunk/verif/model
    from Rev 17 to Rev 32
    Reverse comparison

Rev 17 → Rev 32

/mt48lc8m8a2.v
115,10 → 115,14
wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4];
wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4];
 
`ifdef VERBOSE
wire Debug = 1'b1; // Debug messages : 1 = On
`else
wire Debug = 1'b0; // Debug messages : 1 = On
`endif
// Write Burst Mode
wire Write_burst_mode = Mode_reg[9];
 
reg Debug; // Debug messages : 1 = On
wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ
 
assign Dq = Dq_reg; // DQ buffer
158,7 → 162,6
time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
 
initial begin
Debug = 1'b0;
Dq_reg = {data_bits{1'bz}};
{Data_in_enable, Data_out_enable} = 0;

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