URL
https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
Subversion Repositories sdr_ctrl
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdr_ctrl
- from Rev 15 to Rev 16
- ↔ Reverse comparison
Rev 15 → Rev 16
/trunk/rtl/core/sdrc_req_gen.v
130,7 → 130,8
output [APP_RW-1:0] r2b_len; |
input b2r_ack, b2r_arb_ok, sdr_init_done; |
// |
input sdr_width; |
input [1:0] sdr_width; // 2'b00 - 32 Bit, 2'b01 - 16 Bit, 2'b1x - 8Bit |
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/****************************************************************************/ |
// Internal Nets |
206,7 → 207,9
curr_sdr_addr <= (req_ack) ? req_addr : |
(req_ld) ? next_sdr_addr : curr_sdr_addr; |
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sdr_addrs_mask <= (req_ack) ? (sdr_width ? {req_addr_mask,req_addr_mask[0]} : req_addr_mask) : sdr_addrs_mask; |
sdr_addrs_mask <= (req_ack) ?((sdr_width == 2'b00) ? req_addr_mask : |
(sdr_width == 2'b01) ? {req_addr_mask,req_addr_mask[0]} : |
{req_addr_mask,req_addr_mask[1:0]}) : sdr_addrs_mask; |
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end // always @ (posedge clk) |
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/trunk/rtl/core/sdrc_bs_convert.v
84,7 → 84,7
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input clk; |
input reset_n ; |
input sdr_width; |
input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit |
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input [APP_AW-1:0] app_req_addr; |
output [APP_AW:0] app_req_addr_int; |
123,29 → 123,17
reg [SDR_BW-1:0] app_wr_en_n_int; |
reg app_wr_next; |
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reg lcl_rd_valid; |
reg lcl_wr_next; |
reg [15:0] saved_rd_data; |
reg save_lower; |
reg upper_word; |
reg write_upper; |
reg [23:0] saved_rd_data; |
reg [7:0] rd_xfr_count; |
reg [7:0] wr_xfr_count; |
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reg [3:0] rd_state,next_rd_state; |
reg [3:0] wr_state,next_wr_state; |
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parameter SDR16_IDLE = 0, |
SDR16_RD_LO = 1, |
SDR16_RD_HI = 2, |
SDR16_WR_LO = 3, |
SDR16_WR_HI = 4; |
wire ok_to_req; |
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assign ok_to_req = ((wr_state == SDR16_IDLE) && (rd_state == SDR16_IDLE)); |
assign ok_to_req = ((wr_xfr_count == 0) && (rd_xfr_count == 0)); |
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always @(*) begin |
if(!sdr_width) // 32 Bit SDR Mode |
if(sdr_width == 2'b00) // 32 Bit SDR Mode |
begin |
app_req_addr_int = {1'b0,app_req_addr}; |
app_req_len_int = app_req_len; |
158,8 → 146,8
app_rd_valid = app_rd_valid_int; |
app_req_ack = app_req_ack_int; |
end |
else // 16 Bit SDR Mode |
begin |
else if(sdr_width == 2'b01) // 16 Bit SDR Mode |
begin |
// Changed the address and length to match the 16 bit SDR Mode |
app_req_addr_int = {app_req_addr,1'b0}; |
app_req_len_int = {app_req_len,1'b0}; |
166,9 → 154,9
app_req_dma_last_int = app_req_dma_last; |
app_sdr_req_int = app_sdr_req && ok_to_req; |
app_req_ack = app_req_ack_int; |
app_wr_next = lcl_wr_next; |
app_rd_valid = lcl_rd_valid; |
if(write_upper) |
app_wr_next = (app_wr_next_int & wr_xfr_count[0]); |
app_rd_valid = (rd_xfr_count & rd_xfr_count[0]); |
if(wr_xfr_count[0] == 1'b1) |
begin |
app_wr_en_n_int = app_wr_en_n[3:2]; |
app_wr_data_int = app_wr_data[31:16]; |
179,115 → 167,43
app_wr_data_int = app_wr_data[15:0]; |
end |
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app_rd_data = {app_rd_data_int[15:0],saved_rd_data}; |
end |
end |
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// |
// WRITES |
// |
always @(*) begin |
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lcl_wr_next = 1'b0; |
upper_word = 1'b0; |
next_wr_state = wr_state; |
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case(wr_state) |
SDR16_IDLE: |
app_rd_data = {app_rd_data_int,saved_rd_data[15:0]}; |
end else // 8 Bit SDR Mode |
begin |
// Changed the address and length to match the 16 bit SDR Mode |
app_req_addr_int = {app_req_addr,2'b0}; |
app_req_len_int = {app_req_len,2'b0}; |
app_req_dma_last_int = app_req_dma_last; |
app_sdr_req_int = app_sdr_req && ok_to_req; |
app_req_ack = app_req_ack_int; |
app_wr_next = (app_wr_next_int & (wr_xfr_count[1:0]== 2'b01)); |
app_rd_valid = (rd_xfr_count & (rd_xfr_count[1:0]== 2'b01)); |
// Note: counter is down counter from 00 -> 11 -> 10 -> 01 --> 00 |
if(wr_xfr_count[1:0] == 2'b01) |
begin |
if(app_req_ack_int && sdr_width) |
begin |
if(~app_req_wr_n) |
begin |
next_wr_state = SDR16_WR_LO; |
end |
end |
else |
begin |
next_wr_state = SDR16_IDLE; |
end |
app_wr_en_n_int = app_wr_en_n[3]; |
app_wr_data_int = app_wr_data[31:24]; |
end |
SDR16_WR_LO: |
else if(wr_xfr_count[1:0] == 2'b10) |
begin |
if(app_wr_next_int) |
begin |
upper_word = 1'b1; |
next_wr_state = SDR16_WR_HI; |
end |
end |
SDR16_WR_HI: |
begin |
if(app_wr_next_int) |
if(~(|wr_xfr_count)) |
begin |
lcl_wr_next = 1'b1; |
next_wr_state = SDR16_IDLE; |
end |
else |
begin |
lcl_wr_next = 1'b1; |
next_wr_state = SDR16_WR_LO; |
end |
app_wr_en_n_int = app_wr_en_n[2]; |
app_wr_data_int = app_wr_data[23:16]; |
end |
default: |
else if(wr_xfr_count[1:0] == 2'b11) |
begin |
next_wr_state = SDR16_IDLE; |
app_wr_en_n_int = app_wr_en_n[1]; |
app_wr_data_int = app_wr_data[15:8]; |
end |
endcase |
end |
// |
// READS |
// |
always @(*) begin |
else begin |
app_wr_en_n_int = app_wr_en_n[0]; |
app_wr_data_int = app_wr_data[7:0]; |
end |
|
app_rd_data = {app_rd_data_int,saved_rd_data[23:0]}; |
end |
end |
|
lcl_rd_valid = 1'b0; |
save_lower = 1'b0; |
next_rd_state = rd_state; |
|
case(rd_state) |
SDR16_IDLE: |
begin |
if(app_req_ack_int && sdr_width) |
begin |
if(app_req_wr_n) |
begin |
next_rd_state = SDR16_RD_LO; |
end |
end |
else |
begin |
next_rd_state = SDR16_IDLE; |
end |
end |
SDR16_RD_LO: |
begin |
if(app_rd_valid_int) |
begin |
save_lower = 1'b1; |
next_rd_state = SDR16_RD_HI; |
end |
end |
SDR16_RD_HI: |
begin |
if(app_rd_valid_int) |
if(~(|rd_xfr_count)) |
begin |
lcl_rd_valid = 1'b1; |
next_rd_state = SDR16_IDLE; |
end |
else |
begin |
lcl_rd_valid = 1'b1; |
next_rd_state = SDR16_RD_LO; |
end |
end |
default: |
begin |
next_rd_state = SDR16_IDLE; |
end |
endcase |
end |
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reg lcl_mc_req_wr_n; |
|
always @(posedge clk) |
294,42 → 210,38
begin |
if(!reset_n) |
begin |
rd_xfr_count <= 8'b0; |
wr_xfr_count <= 8'b0; |
rd_xfr_count <= 8'b0; |
wr_xfr_count <= 8'b0; |
lcl_mc_req_wr_n <= 1'b1; |
saved_rd_data <= 24'h0; |
end |
else |
begin |
if(app_req_ack) begin |
wr_xfr_count <= app_req_len - 1'b1; |
rd_xfr_count <= app_req_len - 1'b1; |
lcl_mc_req_wr_n <= app_req_wr_n; |
else begin |
lcl_mc_req_wr_n <= app_req_wr_n; |
|
// During Write Phase |
if(app_req_ack && (app_req_wr_n == 0)) begin |
wr_xfr_count <= app_req_len_int; |
end |
else if((lcl_wr_next & !lcl_mc_req_wr_n) || (lcl_rd_valid & lcl_mc_req_wr_n)) begin |
else if(app_wr_next_int & !lcl_mc_req_wr_n) begin |
wr_xfr_count <= wr_xfr_count - 1'b1; |
rd_xfr_count <= rd_xfr_count - 1'b1; |
end |
end |
end |
// |
// |
always @(posedge clk) |
begin |
if(!reset_n) |
begin |
rd_state <= SDR16_IDLE; |
wr_state <= SDR16_IDLE; |
saved_rd_data <= 16'b0; |
write_upper <= 1'b0; |
end |
else |
begin |
rd_state <= next_rd_state; |
wr_state <= next_wr_state; |
if(save_lower) |
saved_rd_data <= app_rd_data_int[15:0]; |
write_upper <= upper_word; |
end |
end |
|
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// During Read Phase |
if(app_req_ack && app_req_wr_n) begin |
rd_xfr_count <= app_req_len_int; |
end |
else if(app_rd_valid_int & lcl_mc_req_wr_n) begin |
rd_xfr_count <= rd_xfr_count - 1'b1; |
if(sdr_width == 2'b01) // 16 Bit SDR Mode |
saved_rd_data[15:0] <= app_rd_data_int; |
else begin// 8 bit SDR Mode - |
// Note: counter is down counter from 00 -> 11 -> 10 -> 01 --> 00 |
if(rd_xfr_count[1:0] == 2'b00) saved_rd_data[7:0] <= app_rd_data_int[7:0]; |
else if(rd_xfr_count[1:0] == 2'b11) saved_rd_data[15:8] <= app_rd_data_int[7:0]; |
else if(rd_xfr_count[1:0] == 2'b10) saved_rd_data[23:16] <= app_rd_data_int[7:0]; |
end |
end |
end |
end |
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endmodule // sdr_bs_convert |
/trunk/rtl/core/sdrc_core.v
35,7 → 35,9
Author(s): |
- Dinesh Annayya, dinesha@opencores.org |
Version : 1.0 - 8th Jan 2012 |
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Initial version with 16/32 Bit SDRAM Support |
: 1.1 - 24th Jan 2012 |
8 Bit SDRAM Support is added |
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Copyright (C) 2000 Authors and OPENCORES.ORG |
132,7 → 134,7
input clk ; // SDRAM Clock |
input pad_clk ; // SDRAM Clock from Pad, used for registering Read Data |
input reset_n ; // Reset Signal |
input sdr_width ; // 0 - 32 Bit SDR, 1 - 16 Bit SDR |
input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit |
input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits |
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255,8 → 257,8
assign sdr_cmd = {sdr_cs_n, sdr_ras_n, sdr_cas_n, sdr_we_n}; |
// synopsys translate_on |
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assign sdr_den_n = sdr_width ? {2'b00,sdr_den_n_int[1:0]} : sdr_den_n_int; |
assign sdr_dout = sdr_width ? {16'h0000,sdr_dout_int[15:0]} : sdr_dout_int; |
assign sdr_den_n = sdr_den_n_int ; |
assign sdr_dout = sdr_dout_int ; |
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/****************************************************************************/ |