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Rev 32 → Rev 33

/trunk/rtl/top/sdrc_top.v
5,8 → 5,12
This file is part of the sdram controller project
http://www.opencores.org/cores/sdr_ctrl/
Description: SDRAM Controller Core Module
2 types of SDRAMs are supported, 1Mx16 2 bank, or 4Mx16 4 bank.
Description: SDRAM Controller Top Module.
Support 81/6/32 Bit SDRAM.
Column Address is Programmable
Bank Bit are 2 Bit
Row Bits are 12 Bits
 
This block integrate following sub modules
 
sdrc_core
54,90 → 58,92
`include "sdrc.def"
module sdrc_top
(
sdr_width,
cfg_colbits,
 
sdr_width ,
cfg_colbits ,
// WB bus
wb_rst_i ,
wb_clk_i ,
wb_rst_i ,
wb_clk_i ,
wb_stb_i ,
wb_ack_o ,
wb_addr_i ,
wb_we_i ,
wb_dat_i ,
wb_sel_i ,
wb_dat_o ,
wb_cyc_i ,
wb_cti_i ,
 
wb_stb_i ,
wb_ack_o ,
wb_addr_i ,
wb_we_i ,
wb_dat_i ,
wb_sel_i ,
wb_dat_o ,
wb_cyc_i ,
wb_cti_i ,
 
/* Interface to SDRAMs */
sdram_clk,
sdram_pad_clk,
sdram_resetn,
sdr_cs_n,
sdr_cke,
sdr_ras_n,
sdr_cas_n,
sdr_we_n,
sdr_dqm,
sdr_ba,
sdr_addr,
pad_sdr_din,
sdr_dout,
sdr_den_n,
 
sdram_clk ,
sdram_pad_clk ,
sdram_resetn ,
sdr_cs_n ,
sdr_cke ,
sdr_ras_n ,
sdr_cas_n ,
sdr_we_n ,
sdr_dqm ,
sdr_ba ,
sdr_addr ,
pad_sdr_din ,
sdr_dout ,
sdr_den_n ,
/* Parameters */
sdr_init_done,
cfg_req_depth, //how many req. buffer should hold
cfg_sdr_en,
cfg_sdr_mode_reg,
cfg_sdr_tras_d,
cfg_sdr_trp_d,
cfg_sdr_trcd_d,
cfg_sdr_cas,
cfg_sdr_trcar_d,
cfg_sdr_twr_d,
cfg_sdr_rfsh,
cfg_sdr_rfmax);
sdr_init_done ,
cfg_req_depth , //how many req. buffer should hold
cfg_sdr_en ,
cfg_sdr_mode_reg ,
cfg_sdr_tras_d ,
cfg_sdr_trp_d ,
cfg_sdr_trcd_d ,
cfg_sdr_cas ,
cfg_sdr_trcar_d ,
cfg_sdr_twr_d ,
cfg_sdr_rfsh ,
cfg_sdr_rfmax
);
parameter APP_AW = 30; // Application Address Width
parameter APP_DW = 32; // Application Data Width
parameter APP_BW = 4; // Application Byte Width
parameter APP_RW = 9; // Application Request Width
parameter APP_AW = 30; // Application Address Width
parameter APP_DW = 32; // Application Data Width
parameter APP_BW = 4; // Application Byte Width
parameter APP_RW = 9; // Application Request Width
 
parameter SDR_DW = 16; // SDR Data Width
parameter SDR_BW = 2; // SDR Byte Width
parameter SDR_DW = 16; // SDR Data Width
parameter SDR_BW = 2; // SDR Byte Width
parameter dw = 32; // data width
parameter tw = 8; // tag id width
parameter bl = 9; // burst_lenght_width
parameter dw = 32; // data width
parameter tw = 8; // tag id width
parameter bl = 9; // burst_lenght_width
 
//-----------------------------------------------
// Global Variable
// ----------------------------------------------
input sdram_clk ; // SDRAM Clock
input sdram_pad_clk ; // SDRAM Clock from Pad, used for registering Read Data
input sdram_resetn ; // Reset Signal
input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
input sdram_clk ; // SDRAM Clock
input sdram_pad_clk ; // SDRAM Clock from Pad, used for registering Read Data
input sdram_resetn ; // Reset Signal
input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address,
// 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
 
//--------------------------------------
// Wish Bone Interface
// -------------------------------------
input wb_rst_i ;
input wb_clk_i ;
input wb_rst_i ;
input wb_clk_i ;
 
input wb_stb_i ;
output wb_ack_o ;
input [29:0] wb_addr_i ;
input wb_we_i ; // 1 - Write, 0 - Read
input [dw-1:0] wb_dat_i ;
input [dw/8-1:0]wb_sel_i ; // Byte enable
output [dw-1:0] wb_dat_o ;
input wb_cyc_i ;
input [2:0] wb_cti_i ;
input wb_stb_i ;
output wb_ack_o ;
input [29:0] wb_addr_i ;
input wb_we_i ; // 1 - Write, 0 - Read
input [dw-1:0] wb_dat_i ;
input [dw/8-1:0] wb_sel_i ; // Byte enable
output [dw-1:0] wb_dat_o ;
input wb_cyc_i ;
input [2:0] wb_cti_i ;
 
//------------------------------------------------
// Interface to SDRAMs
/trunk/rtl/wb2sdrc/wb2sdrc.v
4,7 → 4,8
http://www.opencores.org/cores/sdr_ctrl/
Description: WISHBONE to SDRAM Controller Bus Transalator
This module translate the WISHBONE protocol to custom sdram controller i/f
1. This module translate the WISHBONE protocol to custom sdram controller i/f
2. Also Handle the clock domain change from Application layer to Sdram layer
To Do:
nothing
39,35 → 40,35
 
module wb2sdrc (
// WB bus
wb_rst_i ,
wb_clk_i ,
wb_rst_i ,
wb_clk_i ,
 
wb_stb_i ,
wb_ack_o ,
wb_addr_i ,
wb_we_i ,
wb_dat_i ,
wb_sel_i ,
wb_dat_o ,
wb_cyc_i ,
wb_cti_i ,
wb_stb_i ,
wb_ack_o ,
wb_addr_i ,
wb_we_i ,
wb_dat_i ,
wb_sel_i ,
wb_dat_o ,
wb_cyc_i ,
wb_cti_i ,
 
 
//SDRAM Controller Hand-Shake Signal
sdram_clk ,
sdram_resetn ,
sdr_req ,
sdr_req_addr ,
sdr_req_len ,
sdr_req_wr_n ,
sdr_req_ack ,
sdr_busy_n ,
sdr_wr_en_n ,
sdr_wr_next ,
sdr_rd_valid ,
sdr_last_rd ,
sdr_wr_data ,
sdr_rd_data
sdram_clk ,
sdram_resetn ,
sdr_req ,
sdr_req_addr ,
sdr_req_len ,
sdr_req_wr_n ,
sdr_req_ack ,
sdr_busy_n ,
sdr_wr_en_n ,
sdr_wr_next ,
sdr_rd_valid ,
sdr_last_rd ,
sdr_wr_data ,
sdr_rd_data
 
);
 
77,18 → 78,18
//--------------------------------------
// Wish Bone Interface
// -------------------------------------
input wb_rst_i ;
input wb_clk_i ;
input wb_rst_i ;
input wb_clk_i ;
 
input wb_stb_i ;
output wb_ack_o ;
input [29:0] wb_addr_i ;
input wb_we_i ; // 1 - Write, 0 - Read
input [dw-1:0] wb_dat_i ;
input [dw/8-1:0]wb_sel_i ; // Byte enable
output [dw-1:0] wb_dat_o ;
input wb_cyc_i ;
input [2:0] wb_cti_i ;
input wb_stb_i ;
output wb_ack_o ;
input [29:0] wb_addr_i ;
input wb_we_i ; // 1 - Write , 0 - Read
input [dw-1:0] wb_dat_i ;
input [dw/8-1:0] wb_sel_i ; // Byte enable
output [dw-1:0] wb_dat_o ;
input wb_cyc_i ;
input [2:0] wb_cti_i ;
/***************************************************
The Cycle Type Idenfier [CTI_IO()] Address Tag provides
additional information about the current cycle.
108,8 → 109,8
//--------------------------------------------
// SDRAM controller Interface
//--------------------------------------------
input sdram_clk ; // sdram clock
input sdram_resetn ; // sdram reset
input sdram_clk ; // sdram clock
input sdram_resetn ; // sdram reset
output sdr_req ; // SDRAM request
output [29:0] sdr_req_addr ; // SDRAM Request Address
output [bl-1:0] sdr_req_len ;
126,19 → 127,24
//----------------------------------------------------
// Wire Decleration
// ---------------------------------------------------
wire cmdfifo_full;
wire cmdfifo_empty;
wire wrdatafifo_full;
wire wrdatafifo_empty;
wire tagfifo_full;
wire tagfifo_empty;
wire rddatafifo_empty;
wire rddatafifo_full;
wire cmdfifo_full ;
wire cmdfifo_empty ;
wire wrdatafifo_full ;
wire wrdatafifo_empty ;
wire tagfifo_full ;
wire tagfifo_empty ;
wire rddatafifo_empty ;
wire rddatafifo_full ;
 
reg pending_read;
reg pending_read ;
 
 
// Generate Address Enable only when internal fifo (Address + data are not full
//-----------------------------------------------------------------------------
// Ack Generaltion Logic
// If Write Request - Acknowledge if the command and write FIFO are not full
// If Read Request - Generate the Acknowledgment once read fifo has data
// available
//-----------------------------------------------------------------------------
 
assign wb_ack_o = (wb_stb_i && wb_cyc_i && wb_we_i) ? // Write Phase
((!cmdfifo_full) && (!wrdatafifo_full)) :
145,15 → 151,45
(wb_stb_i && wb_cyc_i && !wb_we_i) ? // Read Phase
!rddatafifo_empty : 1'b0;
 
// Accept the cmdfifo only when burst start + address enable + address
// valid is asserted
wire cmdfifo_wr = (wb_stb_i && wb_cyc_i && wb_we_i) ? wb_ack_o :
(wb_stb_i && wb_cyc_i && !wb_we_i) ? !pending_read: 1'b0 ;
//---------------------------------------------------------------------------
// Command FIFO Write Generation
// If Write Request - Generate write, when Write fifo and command fifo is
// not full
// If Read Request - Generate write, when command fifo not full and there
// is no pending read request.
//---------------------------------------------------------------------------
wire cmdfifo_wr = (wb_stb_i && wb_cyc_i && wb_we_i && (!cmdfifo_full) ) ? wb_ack_o :
(wb_stb_i && wb_cyc_i && !wb_we_i && (!cmdfifo_full)) ? !pending_read: 1'b0 ;
 
//---------------------------------------------------------------------------
// command fifo read generation
// Command FIFo read will be generated, whenever SDRAM Controller
// Acknowldge the Request
//----------------------------------------------------------------------------
 
wire cmdfifo_rd = sdr_req_ack;
 
//---------------------------------------------------------------------------
// Application layer request is generated towards the controller, whenever
// Command FIFO is not full
// --------------------------------------------------------------------------
assign sdr_req = !cmdfifo_empty;
 
//----------------------------------------------------------------------------
// Since Burst length is not known at the start of the Burst, It's assumed as
// Single Cycle Burst. We need to improvise this ...
// --------------------------------------------------------------------------
wire [bl-1:0] burst_length = 1; // 0 Mean 1 Transfer
 
//-----------------------------------------------------------------------------
// In Wish Bone Spec, For Read Request has to be acked along with data.
// We need to identify the pending read request.
// Once we accept the read request, we should not accept one more read
// request, untill we have transmitted the read data.
// Pending Read will
// set - with Read Request
// reset - with Read Request + Ack
// ----------------------------------------------------------------------------
always @(posedge wb_rst_i or posedge wb_clk_i) begin
if(wb_rst_i) begin
pending_read <= 1'b0;
162,27 → 198,31
end
end
 
//---------------------------------------------------------------------
// Async Command FIFO. This block handle the clock domain change from
// Application layer to SDRAM Controller
// ------------------------------------------------------------------
// Address + Burst Length + W/R Request
async_fifo #(.W(30+bl+1),.DP(4)) u_cmdfifo (
// Write Path Sys CLock Domain
.wr_clk (wb_clk_i),
.wr_reset_n (!wb_rst_i),
.wr_en (cmdfifo_wr),
.wr_data ({burst_length,
!wb_we_i,
wb_addr_i}),
.afull (),
.full (cmdfifo_full),
.wr_clk (wb_clk_i ),
.wr_reset_n (!wb_rst_i ),
.wr_en (cmdfifo_wr ),
.wr_data ({burst_length,
!wb_we_i,
wb_addr_i} ),
.afull ( ),
.full (cmdfifo_full ),
 
// Read Path, SDRAM clock domain
.rd_clk (sdram_clk),
.rd_reset_n (sdram_resetn),
.aempty (),
.empty (cmdfifo_empty),
.rd_en (cmdfifo_rd),
.rd_data ({sdr_req_len,
sdr_req_wr_n,
sdr_req_addr})
.rd_clk (sdram_clk ),
.rd_reset_n (sdram_resetn ),
.aempty ( ),
.empty (cmdfifo_empty ),
.rd_en (cmdfifo_rd ),
.rd_data ({sdr_req_len,
sdr_req_wr_n,
sdr_req_addr} )
);
 
// synopsys translate_off
199,31 → 239,46
end
// synopsys translate_on
 
//---------------------------------------------------------------------
// Write Data FIFO Write Generation, when ever Acked + Write Request
// Note: Ack signal generation already taking account of FIFO full condition
// ---------------------------------------------------------------------
 
wire wrdatafifo_wr = wb_ack_o & wb_we_i ;
 
//------------------------------------------------------------------------
// Write Data FIFO Read Generation, When ever Next Write request generated
// from SDRAM Controller
// ------------------------------------------------------------------------
wire wrdatafifo_rd = sdr_wr_next;
 
 
//------------------------------------------------------------------------
// Async Write Data FIFO
// This block handle the clock domain change over + Write Data + Byte mask
// From Application layer to SDRAM controller layer
//------------------------------------------------------------------------
 
// Write DATA + Data Mask FIFO
async_fifo #(.W(dw+(dw/8)), .DP(16)) u_wrdatafifo (
// Write Path , System clock domain
.wr_clk (wb_clk_i),
.wr_reset_n (!wb_rst_i),
.wr_en (wrdatafifo_wr),
.wr_data ({~wb_sel_i,
wb_dat_i}),
.afull (),
.full (wrdatafifo_full),
.wr_clk (wb_clk_i ),
.wr_reset_n (!wb_rst_i ),
.wr_en (wrdatafifo_wr ),
.wr_data ({~wb_sel_i,
wb_dat_i} ),
.afull ( ),
.full (wrdatafifo_full ),
 
 
// Read Path , SDRAM clock domain
.rd_clk (sdram_clk),
.rd_reset_n (sdram_resetn),
.aempty (),
.empty (wrdatafifo_empty),
.rd_en (wrdatafifo_rd),
.rd_data ({sdr_wr_en_n,
sdr_wr_data})
.rd_clk (sdram_clk ),
.rd_reset_n (sdram_resetn ),
.aempty ( ),
.empty (wrdatafifo_empty ),
.rd_en (wrdatafifo_rd ),
.rd_data ({sdr_wr_en_n,
sdr_wr_data} )
);
// synopsys translate_off
always @(posedge wb_clk_i) begin
243,30 → 298,47
// READ DATA FIFO
// ------------------------------------------------------------------
wire rd_eop; // last read indication
 
// Read FIFO write generation, when ever SDRAM controller issues the read
// valid signal
wire rddatafifo_wr = sdr_rd_valid;
wire rddatafifo_rd = wb_ack_o & !wb_we_i & (rddatafifo_empty == 0);
 
// READ DATA FIFO depth is kept small, assuming that Sys-CLock > SDRAM Clock
// READ DATA + EOP
// Read FIFO read generation, when ever ack is generated along with read
// request.
// Note: Ack generation is already accounted the write FIFO Not Empty
// condition
wire rddatafifo_rd = wb_ack_o & !wb_we_i;
 
//-------------------------------------------------------------------------
// Async Read FIFO
// This block handles the clock domain change over + Read data from SDRAM
// controller to Application layer.
// Note:
// 1. READ DATA FIFO depth is kept small, assuming that Sys-CLock > SDRAM Clock
// READ DATA + EOP
// 2. EOP indicate, last transfer of Burst Read Access. use-full for future
// Tag handling per burst
//
// ------------------------------------------------------------------------
async_fifo #(.W(dw+1), .DP(4)) u_rddatafifo (
// Write Path , SDRAM clock domain
.wr_clk (sdram_clk),
.wr_reset_n (sdram_resetn),
.wr_en (rddatafifo_wr),
.wr_data ({sdr_last_rd,
sdr_rd_data}),
.afull (),
.full (rddatafifo_full),
.wr_clk (sdram_clk ),
.wr_reset_n (sdram_resetn ),
.wr_en (rddatafifo_wr ),
.wr_data ({sdr_last_rd,
sdr_rd_data} ),
.afull ( ),
.full (rddatafifo_full ),
 
 
// Read Path , SYS clock domain
.rd_clk (wb_clk_i),
.rd_reset_n (!wb_rst_i),
.empty (rddatafifo_empty),
.aempty (),
.rd_en (rddatafifo_rd),
.rd_data ({rd_eop,
wb_dat_o})
.rd_clk (wb_clk_i ),
.rd_reset_n (!wb_rst_i ),
.empty (rddatafifo_empty ),
.aempty ( ),
.rd_en (rddatafifo_rd ),
.rd_data ({rd_eop,
wb_dat_o} )
);
 
// synopsys translate_off
/trunk/rtl/core/sdrc_req_gen.v
6,29 → 6,27
http://www.opencores.org/cores/sdr_ctrl/
Description: SDRAM Controller Reguest Generation
The 2Mx32 SDRAM is addressed by a 21 bit address,
each loation is 32 bits wide.
This 21 bit address is mapped as follows:
ADDR [7:0] : Column Address (256 columns)
ADDR [18:8] : Row Address (2K Rows)
ADDR [20:19] : Bank Address (2 banks)
The 4Mx16 SDRAM is addressed by a 22 bit address,
each loation is 16 bits wide.
This 22 bit address is mapped as follows:
ADDR [7:0] : Column Address (256 columns)
ADDR [21:10] : Row Address (4K Rows)
ADDR [21:20] : Bank Address (4 banks)
The 8Mx16 SDRAM is addressed by a 23 bit address,
each loation is 16 bits wide.
This 23 bit address is mapped as follows:
ADDR [8:0] : Column Address (512 columns)
ADDR [20:9] : Row Address (4K Rows)
ADDR [22:21] : Bank Address (4 banks)
 
Address Generation Based on cfg_colbits
cfg_colbits= 2'b00
Address[7:0] - Column Address
Address[9:8] - Bank Address
Address[21:10] - Row Address
cfg_colbits= 2'b01
Address[8:0] - Column Address
Address[10:9] - Bank Address
Address[22:11] - Row Address
cfg_colbits= 2'b10
Address[9:0] - Column Address
Address[11:10] - Bank Address
Address[23:12] - Row Address
cfg_colbits= 2'b11
Address[10:0] - Column Address
Address[12:11] - Bank Address
Address[24:13] - Row Address
 
The SDRAMs are operated in 4 beat burst mode.
This module takes requests from the mc,
This module takes requests from the memory controller,
chops them to page boundaries if wrap=0,
and passes the request to bank_ctl
/trunk/rtl/core/sdrc_core.v
10,7 → 10,7
This block integrate following sub modules
 
sdrc_bs_convert
convert the system side 32 bit into equvailent 16/32 SDR format
convert the system side 32 bit into equvailent 8/16/32 SDR format
sdrc_req_gen
This module takes requests from the app, chops them to burst booundaries
if wrap=0, decodes the bank and passe the request to bank_ctl
446,6 → 446,14
.rfsh_rmax (cfg_sdr_rfmax )
);
/****************************************************************************/
// Instantiate sdr_bs_convert
// This model handle the bus with transaltion from application layer to
// 8/16/32 SDRAM Memory format
// During Write Phase, this block split the data as per SDRAM Width
// During Read Phase, This block does the re-packing based on SDRAM
// Width
//---------------------------------------------------------------------------
sdrc_bs_convert #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_bs_convert (
.clk (clk ),
.reset_n (reset_n ),
/trunk/verif/run/regression_analysis
0,0 → 1,50
#!/bin/csh -f
#
# This files analysis the log files and generat the regression status
#
 
echo "###########################################"
echo " Analysis the Regression Status"
echo "############################################"
set failedm = 0;
set all_testsm = 0;
 
set sdr_tests =( top_SDR_8BIT_basic_test1 top_SDR_16BIT_basic_test1 top_SDR_32BIT_basic_test1 core_SDR_8BIT_basic_test1 core_SDR_16BIT_basic_test1 core_SDR_32BIT_basic_test1)
#set misc_tests=( )
 
 
set i = 0;
echo "###########################################"
foreach run_test ($sdr_tests)
@ i += 1;
if (`tail ../log/${run_test}.log | grep PASSED` == "") then
echo "### test ${i}: ${run_test} --> FAILED"
@ failedm += 1;
@ all_testsm += 1;
else
echo "### test ${i}: ${run_test} --> PASSED"
@ all_testsm += 1;
endif
end
echo "###########################################"
 
 
set i = 0;
echo ""
echo "###########################################"
echo "### Test Logs "
foreach run_test ($sdr_tests)
@ i += 1;
echo " test ${i}: ../log/${run_test}.log"
 
end
echo "###########################################"
 
 
echo ""
echo "###########################################"
echo "### Test Summary "
echo "### "
echo "### Failed $failedm of $all_testsm tests"
echo "###########################################"
 
trunk/verif/run/regression_analysis Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/verif/run/run_all =================================================================== --- trunk/verif/run/run_all (revision 32) +++ trunk/verif/run/run_all (revision 33) @@ -46,3 +46,5 @@ echo " INITIATING SDR 8 BIT Tests" echo ############################## ./run_modelsim top SDR_8BIT | tee ../log/top_sdr8_sim.log + +./regression_analysis

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