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/testbench/simulation.svh
0,0 → 1,93
`timescale 1ns/1ps
 
//-----------------------------------------------------------------
// assert_task
//-----------------------------------------------------------------
task automatic assert_task(input v, string file, int line, input string s);
begin
if (!v)
begin
$display("ASSERT: %s:%0d - %s", file, line, s);
$finish(1);
end
end
endtask
 
//-----------------------------------------------------------------
// ASSERT
//-----------------------------------------------------------------
`define ASSERT(v) assert_task(v, `__FILE__, `__LINE__, `"v`")
 
//-----------------------------------------------------------------
// ASSERT_ALWAYS
//-----------------------------------------------------------------
`define ASSERT_ALWAYS(condition) \
generate \
if(1) \
begin \
wire test = condition; \
always @(test)\
`ASSERT(condition); \
end \
endgenerate
 
//-----------------------------------------------------------------
// TB_TIMEOUT
//-----------------------------------------------------------------
`define TB_TIMEOUT(CLK, RST, VALID, TIMEOUT) \
integer v_timeout_cycles; \
\
always @(posedge ``RST or posedge ``CLK) \
if (``RST) \
v_timeout_cycles <= 0; \
else \
begin \
if (``VALID) \
begin \
v_timeout_cycles <= 0; \
end \
else \
begin \
v_timeout_cycles <= v_timeout_cycles + 1; \
`ASSERT(v_timeout_cycles < ``TIMEOUT); \
end \
end
 
 
//-----------------------------------------------------------------
// CLOCK_GEN
//-----------------------------------------------------------------
`define CLOCK_GEN(NAME, CYCLE) \
reg ``NAME; \
initial \
begin \
``NAME <= 0; \
forever # (``CYCLE / 2) ``NAME = ~``NAME; \
end
 
//-----------------------------------------------------------------
// RESET_GEN
//-----------------------------------------------------------------
`define RESET_GEN(NAME, DELAY) \
reg ``NAME; \
initial \
begin \
``NAME <= 1; \
# ``DELAY \
``NAME <= 0; \
end
 
//-----------------------------------------------------------------
// TB_VCD
//-----------------------------------------------------------------
`define TB_VCD(TOP, NAME) \
initial \
begin \
$dumpfile(``NAME); \
$dumpvars(0,``TOP); \
end
 
//-----------------------------------------------------------------
// TB_RUN_FOR
//-----------------------------------------------------------------
`define TB_RUN_FOR(TIME) initial #``TIME $finish;
/testbench/wb_master.sv
0,0 → 1,262
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module wb_master
(
input clk_i,
input rst_i,
 
// Wishbone I/F
output reg [31:0] addr_o,
output reg [31:0] data_o,
input [31:0] data_i,
output reg [3:0] sel_o,
output reg [2:0] cti_o,
output reg cyc_o,
output reg stb_o,
output reg we_o,
input ack_i,
input stall_i
);
 
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter MIN_ADDRESS = 0;
parameter MAX_ADDRESS = 8192;
parameter BURST_ENABLED = 1;
parameter READ_ONLY = 0;
parameter WRITE_ONLY = 0;
parameter SEQUENTIAL_ONLY = 0;
parameter RANDOM_DELAY = 1;
parameter DELAY_RATE = 3;
 
`include "simulation.svh"
 
//-----------------------------------------------------------------
// Request Queue
//-----------------------------------------------------------------
typedef struct
{
reg [31:0] address;
reg [31:0] data;
reg [3:0] sel;
reg we;
} request_t;
 
request_t requests[$];
 
//-----------------------------------------------------------------
// Memory
//-----------------------------------------------------------------
reg [31:0] mem[*];
 
//-----------------------------------------------------------------
// write
//-----------------------------------------------------------------
task automatic write(input [31:0] addr, input [31:0] data);
begin
mem[addr[31:2]] = data;
end
endtask
 
//-----------------------------------------------------------------
// read
//-----------------------------------------------------------------
task automatic read(input [31:0] addr, output [31:0] data);
begin
if (mem.exists(addr[31:2]))
data = mem[addr[31:2]];
else
data = 32'bx;
end
endtask
 
//-----------------------------------------------------------------
// write_bytes
//-----------------------------------------------------------------
task automatic write_bytes(input [31:0] addr, input [31:0] data, input [31:0] sel);
begin
reg [31:0] new_data;
 
read(addr, new_data);
 
if (sel[3])
new_data[31:24] = data[31:24];
if (sel[2])
new_data[23:16] = data[23:16];
if (sel[1])
new_data[15:8] = data[15:8];
if (sel[0])
new_data[7:0] = data[7:0];
 
write(addr, new_data);
end
endtask
 
//-----------------------------------------------------------------
// compare
//-----------------------------------------------------------------
task automatic compare(input [31:0] addr, input [31:0] data, input [31:0] sel, output match);
begin
reg [31:0] new_data;
 
read(addr, new_data);
 
match = 1;
 
if (sel[3])
if (new_data[31:24] !== data[31:24])
match = 0;
 
if (sel[2])
if (new_data[23:16] !== data[23:16])
match = 0;
 
if (sel[1])
if (new_data[15:8] !== data[15:8])
match = 0;
 
if (sel[0])
if (new_data[7:0] !== data[7:0])
match = 0;
 
if (!match)
begin
$display("ERROR: Expected %x Got %x Mask %x", new_data, data, sel);
end
end
endtask
 
//-----------------------------------------------------------------
// request
//-----------------------------------------------------------------
initial
begin
request_t req;
reg burst;
reg [2:0] burst_cnt;
 
addr_o = 32'bz;
data_o = 32'bz;
sel_o = 4'bz;
we_o = 1'bz;
stb_o = 1'b0;
cti_o = 3'bz;
burst = 1'b0;
burst_cnt = 0;
 
req.address = 0;
 
forever
begin
@(posedge clk_i);
 
// Command presented and accepted
if (stb_o && !stall_i)
begin
requests.push_back(req);
 
addr_o = 32'bz;
data_o = 32'bz;
sel_o = 4'bz;
we_o = 1'bz;
cti_o = 3'bz;
stb_o = 1'b0;
end
 
// Continuation of a burst
if (!stb_o && burst)
begin
req.address = req.address + 4;
req.data = req.we ? $urandom : 32'bz;
 
addr_o = req.address;
addr_o[1:0] = 2'b0;
data_o = req.data;
cti_o = (burst_cnt == 1) ? 3'b111 : 3'b010;
sel_o = req.sel;
we_o = req.we;
stb_o = 1'b1;
 
burst_cnt = burst_cnt - 1;
if (burst_cnt == 0)
burst = 0;
end
 
// Ready to issue a new command?
if (!stb_o)
begin
 
if (RANDOM_DELAY)
begin
repeat ($urandom_range(DELAY_RATE,0)) @(posedge clk_i);
end
 
if (SEQUENTIAL_ONLY)
req.address = req.address + 4;
else
req.address = $urandom_range(MAX_ADDRESS,MIN_ADDRESS);
 
if (READ_ONLY)
req.we = 1'b0;
else if (WRITE_ONLY)
req.we = 1'b1;
else
req.we = $urandom;
req.data = req.we ? $urandom : 32'bz;
 
if (BURST_ENABLED)
begin
burst = $urandom;
burst_cnt = 7;
end
else
burst = 0;
 
req.sel = (!burst && req.we) ? $urandom : 4'b1111;
 
addr_o = req.address;
addr_o[1:0] = 2'b0;
data_o = req.data;
sel_o = req.sel;
we_o = req.we;
cti_o = (!burst) ? 3'b111 : 3'b010;
stb_o = 1'b1;
end
end
end
 
//-----------------------------------------------------------------
// response
//-----------------------------------------------------------------
always @(posedge clk_i)
begin
request_t req;
if (ack_i)
begin
`ASSERT(requests.size() > 0);
 
req = requests.pop_front();
 
// Write
if (req.we)
begin
write_bytes(req.address, req.data, req.sel);
end
// Read
else
begin
reg match;
compare(req.address, data_i, req.sel, match);
`ASSERT(match);
end
end
end
 
always @ *
begin
cyc_o = stb_o || (requests.size() > 0);
end
 
endmodule
/testbench/makefile
0,0 → 1,36
TRACE ?= 1
MAX_ADDRESS ?= 8192
PART ?= IS42VM16400K
 
all: compile run view
# Testbench
SRC+= ./top_tb.sv wb_master.sv IS42VM16400K.v MT48LC8M16A2.v
 
# DUT
SRC+= ../rtl/sdram.v
 
SRC_FLAGS = +define+MAX_ADDRESS=$(MAX_ADDRESS)
 
ifeq ($(TRACE),1)
SRC_FLAGS += +define+TRACE=$(TRACE)
endif
 
SRC_FLAGS += +define+PART=$(PART)
 
INC_DIRS = -I.
 
compile :
vlib work
vlog $(SRC) $(SRC_FLAGS)
run : compile
vsim -c -do "run -all" top_tb
view : compile
ifeq ($(TRACE),1)
gtkwave waveform.vcd gtksettings.sav
endif
clean :
-rm -rf work waveform.vcd transcript
/testbench/IS42VM16400K.v
0,0 → 1,1731
/************************************************************************
*
* Copyright(c) ISSI Inc., 2010
*
* == 64M Low power SDRAM behavioral Model by ESC ==
*
* Address : 1940 Zanker Road San Jose,CA95112-4216,U.S.A.
* Tel : +1-408-969-6600, Fax : +1-408-969-7800
*
* Revision : Rev0.0 (2010.10.4)
*
* Running Options
* +S50 : Set AC timing parameter for -50(200MHz )
* +S60 : Set AC timing parameter for -60(166MHz )
* +S75 : Set AC timing parameter for -75(133MHz )
* +VERBOSE : Display internal operation status
*
************************************************************************/
 
`timescale 1ns / 1ps
 
`define S60
//`define VERBOSE
 
module IS42VM16400K (dq, addr, ba, clk, cke, csb, rasb, casb, web, dqm);
 
parameter no_of_bank = 2;
parameter no_of_addr = 13;
parameter no_of_data = 16;
parameter no_of_col = 9;
parameter no_of_dqm = 2;
parameter mem_sizes = 4194304;
 
 
// Timing Parameters for -50 PC200
`ifdef S50
parameter tAC3 = 5.0;
parameter tHZ3 = 5.0;
parameter tAC2 = 8.0;
parameter tHZ2 = 8.0;
parameter tOH = 2.0;
parameter tMRD = 2.0;
parameter tRAS = 40.0;
parameter tRC = 55.0;
parameter tRCD = 18.0;
parameter tRFC = 60.0;
parameter tXSR = 60.0;
parameter tRP = 15.0;
parameter tRRD = 10.0;
parameter tDPLa = 5.0;
parameter tDPLm = 12.0;
parameter tDPDX = 100000.0;
`endif
 
 
// Timing Parameters for -60 PC166
`ifdef S60
parameter tAC3 = 5.5;
parameter tHZ3 = 5.5;
parameter tAC2 = 8.0;
parameter tHZ2 = 8.0;
parameter tOH = 2.5;
parameter tMRD = 2.0;
parameter tRAS = 42.0;
parameter tRC = 60.0;
parameter tRCD = 18.0;
parameter tRFC = 66.0;
parameter tXSR = 66.0;
parameter tRP = 18.0;
parameter tRRD = 12.0;
parameter tDPLa = 6.0;
parameter tDPLm = 12.0;
parameter tDPDX = 100000.0;
`endif
 
// Timing Parameters for -75 PC133
`ifdef S75
parameter tAC3 = 6.0;
parameter tHZ3 = 6.0;
parameter tAC2 = 8.0;
parameter tHZ2 = 8.0;
parameter tOH = 2.5;
parameter tMRD = 2.0;
parameter tRAS = 45.0;
parameter tRC = 67.5;
parameter tRCD = 22.5;
parameter tRFC = 67.5;
parameter tXSR = 67.5;
parameter tRP = 22.5;
parameter tRRD = 15.0;
parameter tDPLa = 7.5;
parameter tDPLm = 15.0;
parameter tDPDX = 100000.0;
`endif
 
 
inout [no_of_data - 1 : 0] dq;
input [no_of_addr - 1 : 0] addr;
input [no_of_bank - 1 : 0] ba;
input clk;
input cke;
input csb;
input rasb;
input casb;
input web;
input [no_of_dqm - 1 : 0] dqm;
 
`protect
 
reg [no_of_data - 1 : 0] bank0 [0 : mem_sizes];
reg [no_of_data - 1 : 0] bank1 [0 : mem_sizes];
reg [no_of_data - 1 : 0] bank2 [0 : mem_sizes];
reg [no_of_data - 1 : 0] bank3 [0 : mem_sizes];
 
reg [no_of_bank - 1 : 0] bank_addr [0 : 3]; // bank address Pipeline
reg [no_of_col - 1 : 0] Col_addr [0 : 3]; // Column address Pipeline
reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline
reg [no_of_dqm - 1 : 0] dqm_reg0, dqm_reg1; // DQM Operation Pipeline
reg [no_of_dqm - 1 : 0] dqm_save [0 : 3]; // DQM Operation Pipeline
reg [no_of_addr - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
 
reg [no_of_addr - 1 : 0] Mode_reg;
reg [no_of_addr - 1 : 0] EMode_reg;
reg [no_of_data - 1 : 0] dq_reg, dq_dqm;
reg [no_of_col - 1 : 0] Col_temp, Burst_counter;
 
reg Act_b0, Act_b1, Act_b2, Act_b3; // bank Activate
reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // bank Precharge
 
reg [1 : 0] bank_precharge [0 : 3]; // Precharge Command
reg A10_precharge [0 : 3]; // addr[10] = 1 (All banks)
reg Auto_precharge [0 : 3]; // RW Auto Precharge (bank)
reg Read_precharge [0 : 3]; // R Auto Precharge
reg Write_precharge [0 : 3]; // W Auto Precharge
reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge
reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge
reg [1 : 0] RW_interrupt_bank; // RW Interrupt bank
integer RW_interrupt_counter [0 : 3]; // RW Interrupt Counter
integer Count_precharge [0 : 3]; // RW Auto Precharge Counter
 
reg Data_in_enable;
reg Data_out_enable;
 
reg [no_of_bank - 1 : 0] bank, Prev_bank;
reg [no_of_addr - 1 : 0] Row;
reg [no_of_col - 1 : 0] Col, Col_brst;
 
reg [19:0] ccc;
reg [3:0] bit;
reg [2:0] CL;
reg [8:0] BL;
reg RIW_violate;
reg Dout_Drive_Flag;
reg Pre_Dout_Drive_Flag;
reg [10:0] Count_at_Read;
reg Read_cmd_received;
reg Read_cmd_received_cke;
reg Write_cmd_received_cke;
reg state_act_pwrdn,state_pre_pwrdn,state_dpdn,state_self;
reg dpdn_check_start;
reg [10:0] Read_cmd_count;
reg [10:0] Read_cmd_count_cke;
reg [10:0] Write_cmd_count_cke;
reg [3:0] cmp_count;
// Internal system clock
reg ckeZ, Sys_clk;
 
// Commands Decode
wire Active_enable = ~csb & ~rasb & casb & web ;
wire Aref_enable = ~csb & ~rasb & ~casb & web & cke;
wire Sref_enable = ~csb & ~rasb & ~casb & web & ~cke;
wire Burst_term = ~csb & rasb & casb & ~web & cke;
wire Deep_pwrdn = ~csb & rasb & casb & ~web & ~cke;
wire Mode_reg_enable = ~csb & ~rasb & ~casb & ~web & ~ba[1] & ~ba[0];
wire EMode_reg_enable = ~csb & ~rasb & ~casb & ~web & ba[1] & ~ba[0];
wire Prech_enable = ~csb & ~rasb & casb & ~web ;
wire Read_enable = ~csb & rasb & ~casb & web ;
wire Write_enable = ~csb & rasb & ~casb & ~web ;
 
// Burst Length Decode
wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0];
wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
wire Burst_length_f = Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
 
// CAS Latency Decode
wire Cas_latency_1 = ~Mode_reg[6] & ~Mode_reg[5] & Mode_reg[4];
wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4];
wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4];
 
// Write Burst Mode
wire Write_burst_mode = Mode_reg[9];
 
`ifdef VERBOSE
wire Debug = 1'b1; // Debug messages : 1 = On
`else
wire Debug = 1'b0; // Debug messages : 1 = On
`endif
 
wire dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ
// CKE function
wire clk_suspend_write= (Act_b0 | Act_b1 | Act_b2 | Act_b3) & Write_cmd_received_cke;
wire clk_suspend_read = (Act_b0 | Act_b1 | Act_b2 | Act_b3) & Read_cmd_received_cke;
wire act_pwrdn = (Act_b0 | Act_b1 | Act_b2 | Act_b3) & (~Read_cmd_received_cke & ~Write_cmd_received_cke);
wire pch_pwrdn = (Pc_b0 & Pc_b1 & Pc_b2 & Pc_b3) & (~Read_cmd_received_cke | ~Write_cmd_received_cke);
 
assign dq = dq_reg; // DQ buffer
 
// Commands Operation
`define ACT 0
`define NOP 1
`define READ 2
`define WRITE 3
`define PRECH 4
`define A_REF 5
`define BST 6
`define LMR 7
 
// Timing Check variable
real MRD_chk;
real WR_chkm0, WR_chkm1, WR_chkm2, WR_chkm3;
real RFC_chk, RRD_chk;
real RC_chk0, RC_chk1, RC_chk2, RC_chk3 ;
real RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 ;
real RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 ;
real RP_chk0, RP_chk1, RP_chk2, RP_chk3 ;
real SELF_chk, DPDN_chk ;
 
initial begin
mem_init;
dq_reg = {no_of_data{1'bz}};
Data_in_enable = 0; Data_out_enable = 0;
Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1;
Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0;
WR_chkm0 = 0; WR_chkm1 = 0; WR_chkm2 = 0; WR_chkm3 = 0;
RW_interrupt_read[0] = 0; RW_interrupt_read[1] = 0; RW_interrupt_read[2] = 0; RW_interrupt_read[3] = 0;
RW_interrupt_write[0] = 0; RW_interrupt_write[1] = 0; RW_interrupt_write[2] = 0; RW_interrupt_write[3] = 0;
MRD_chk = 0; RFC_chk = 0; RRD_chk = 0;
RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0;
RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0;
RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0;
RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0;
SELF_chk = 0; DPDN_chk = 0;
Read_cmd_received=0;
Read_cmd_count=0;
Read_cmd_received_cke=0;
Read_cmd_count_cke=0;
Write_cmd_received_cke=0;
Write_cmd_count_cke=0;
state_act_pwrdn=0;
state_pre_pwrdn=0;
state_dpdn=0;
state_self=0;
dpdn_check_start=0;
EMode_reg=0;
Mode_reg=0;
Count_at_Read=0;
 
$timeformat (-9, 2, " ns", 12);
end
 
// System clock generator
always begin
@ (posedge clk) begin
Sys_clk = ckeZ;
ckeZ = cke;
end
@ (negedge clk) begin
Sys_clk = 1'b0;
end
end
 
always @ (posedge clk) begin
// CKE Exit
if (cke === 1'b1) begin
if (state_self === 1'b1) begin
state_self = 1'b0;
SELF_chk=$realtime;
if (Debug) $display ("Time = %t : OPERATION = SREFX : Self Refresh exit", $realtime);
end else if (state_dpdn == 1'b1) begin
state_dpdn = 1'b0;
DPDN_chk=$realtime;
if (Debug) $display ("Time = %t : OPERATION = DPDNX : Deep Powerdown exit", $realtime);
end else if (state_act_pwrdn == 1'b1) begin
state_act_pwrdn = 1'b0;
if (Debug) $display ("Time = %t : OPERATION = APDNX : Active Power down exit", $realtime);
end else if (state_pre_pwrdn == 1'b1) begin
state_pre_pwrdn = 1'b0;
if (Debug) $display ("Time = %t : OPERATION = PPDNX : Precharge Power down exit", $realtime);
end
end
end
 
 
always @ (Dout_Drive_Flag) begin
 
if(Cas_latency_2 ==1) begin
 
Pre_Dout_Drive_Flag <= #tHZ2 Dout_Drive_Flag;
 
end else if(Cas_latency_3 ==1) begin
 
Pre_Dout_Drive_Flag <= #tHZ3 Dout_Drive_Flag;
 
end
 
end
 
 
 
 
always @ (posedge Sys_clk) begin
// Internal Commamd Pipelined
Command[0] = Command[1];
Command[1] = Command[2];
Command[2] = Command[3];
Command[3] = `NOP;
 
Col_addr[0] = Col_addr[1];
Col_addr[1] = Col_addr[2];
Col_addr[2] = Col_addr[3];
Col_addr[3] = {no_of_col{1'b0}};
 
bank_addr[0] = bank_addr[1];
bank_addr[1] = bank_addr[2];
bank_addr[2] = bank_addr[3];
bank_addr[3] = 2'b00;
 
bank_precharge[0] = bank_precharge[1];
bank_precharge[1] = bank_precharge[2];
bank_precharge[2] = bank_precharge[3];
bank_precharge[3] = 2'b00;
 
A10_precharge[0] = A10_precharge[1];
A10_precharge[1] = A10_precharge[2];
A10_precharge[2] = A10_precharge[3];
A10_precharge[3] = 1'b0;
 
// dqm pipeline for Read
dqm_reg0 = dqm_reg1;
dqm_reg1 = dqm;
 
dqm_save[3]=dqm_save[2];
dqm_save[2]=dqm_save[1];
dqm_save[1]=dqm_save[0];
dqm_save[0]=dqm;
 
 
if (Read_cmd_received == 1'b1) begin
Read_cmd_count = Read_cmd_count + 1;
end
else begin
Read_cmd_count = 4'b0;
end
//if (Read_cmd_count == (BL+CL+1)) begin
if (Read_cmd_count == Count_at_Read+(BL+CL+1)) begin
Read_cmd_received = 1'b0;
end
 
// Count for CKE
if (Read_cmd_received_cke == 1'b1) begin
Read_cmd_count_cke = Read_cmd_count_cke + 1;
end
else begin
Read_cmd_count_cke = 4'b0;
end
if (Read_cmd_count_cke == (BL+CL-1)) begin
Read_cmd_received_cke = 1'b0;
end
 
// Count for CKE
if (Write_cmd_received_cke == 1'b1) begin
Write_cmd_count_cke = Write_cmd_count_cke + 1;
end
else begin
Write_cmd_count_cke = 4'b0;
end
if (Write_cmd_count_cke == BL) begin
Write_cmd_received_cke = 1'b0;
end
 
 
 
// Read or Write with Auto Precharge Counter
if (Auto_precharge[0] === 1'b1) begin
Count_precharge[0] = Count_precharge[0] + 1;
end
if (Auto_precharge[1] === 1'b1) begin
Count_precharge[1] = Count_precharge[1] + 1;
end
if (Auto_precharge[2] === 1'b1) begin
Count_precharge[2] = Count_precharge[2] + 1;
end
if (Auto_precharge[3] === 1'b1) begin
Count_precharge[3] = Count_precharge[3] + 1;
end
 
// Read or Write Interrupt Counter
if (RW_interrupt_write[0] === 1'b1) begin
RW_interrupt_counter[0] = RW_interrupt_counter[0] + 1;
end
if (RW_interrupt_write[1] === 1'b1) begin
RW_interrupt_counter[1] = RW_interrupt_counter[1] + 1;
end
if (RW_interrupt_write[2] === 1'b1) begin
RW_interrupt_counter[2] = RW_interrupt_counter[2] + 1;
end
if (RW_interrupt_write[3] === 1'b1) begin
RW_interrupt_counter[3] = RW_interrupt_counter[3] + 1;
end
 
// tMRD Counter
MRD_chk = MRD_chk + 1;
 
// Auto Refresh
if (Aref_enable === 1'b1) begin
if (Debug) begin
//$display ("%m : at time %t AREF : Auto Refresh", $realtime);
$display ("Time = %t : OPERATION = AREF : Auto Refresh", $realtime);
end
 
// DPDXN to Auto Refresh
if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
$display ("Time = %t : ERROR : Pwrup violation(DPDX to AREF)", $realtime);
end
 
// Self exit to Auto Refresh
if ($realtime - SELF_chk < tXSR) begin
$display ("Time = %t : ERROR : tXSR violation(SREFX to AREF)", $realtime);
end
 
// Auto Refresh to Auto Refresh
if ($realtime - RFC_chk < tRFC) begin
//$display ("%m : at time %t ERROR: tRFC violation during Auto Refresh", $realtime);
$display ("Time = %t : ERROR : tRFC violation(AREF to AREF)", $realtime);
end
 
// Precharge to Auto Refresh
if (($realtime - RP_chk0 < tRP)) begin
//$display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $realtime);
$display ("Time = %t : ERROR : tRP violation(PRECHARGE0 to AREF)", $realtime);
end
if (($realtime - RP_chk1 < tRP)) begin
//$display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $realtime);
$display ("Time = %t : ERROR : tRP violation(PRECHARGE1 to AREF)", $realtime);
end
if (($realtime - RP_chk2 < tRP)) begin
//$display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $realtime);
$display ("Time = %t : ERROR : tRP violation(PRECHARGE2 to AREF)", $realtime);
end
if (($realtime - RP_chk3 < tRP)) begin
//$display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $realtime);
$display ("Time = %t : ERROR : tRP violation(PRECHARGE3 to AREF)", $realtime);
end
 
 
// Precharge to Refresh
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
//$display ("%m : at time %t ERROR: All banks must be Precharge before Auto Refresh", $realtime);
$display ("Time = %t : ERROR : All banks must be Precharged before AREF", $realtime);
end
 
// Load Mode Register to Auto Refresh
if (MRD_chk < tMRD) begin
//$display ("%m : at time %t ERROR: tMRD violation during Auto Refresh", $realtime);
$display ("Time = %t : ERROR : tMRD violation(MRS to AREF)", $realtime);
end
 
// Record Current tRFC time
RFC_chk = $realtime;
end
// Load Mode Register
if (Mode_reg_enable === 1'b1) begin
// Register Mode
Mode_reg = addr;
 
// Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode
if (Debug) begin
//$display ("%m : at time %t LMR : Load Mode Register", $realtime);
$display ("Time = %t : OPERATION = MRS : Load Mode Register", $realtime);
// CAS Latency
case (addr[6 : 4])
3'b010 : $display (" CAS Latency = 2");
3'b011 : $display (" CAS Latency = 3");
default : $display (" CAS Latency = Reserved");
endcase
case (addr[6 : 4])
3'b010 : CL=2;
3'b011 : CL=3;
default : CL=3;
endcase
 
// Burst Length
case (addr[2 : 0])
3'b000 : $display (" Burst Length = 1");
3'b001 : $display (" Burst Length = 2");
3'b010 : $display (" Burst Length = 4");
3'b011 : $display (" Burst Length = 8");
3'b111 : $display (" Burst Length = Full");
default : $display (" Burst Length = Reserved");
endcase
 
case (addr[2 : 0])
3'b000 : BL=1;
3'b001 : BL=2;
3'b010 : BL=4;
3'b011 : BL=8;
3'b111 : BL=512;
default : BL=4;
endcase
 
 
// Burst Type
if (addr[3] === 1'b0) begin
$display (" Burst Type = Sequential");
end else if (addr[3] === 1'b1) begin
$display (" Burst Type = Interleaved");
end else begin
$display (" Burst Type = Reserved");
end
 
// Write Burst Mode
if (addr[9] === 1'b0) begin
$display (" Write Burst Mode = Programmed Burst Length");
end else if (addr[9] === 1'b1) begin
$display (" Write Burst Mode = Single Location Access");
end else begin
$display (" Write Burst Mode = Reserved");
end
end
 
// Precharge to Load Mode Register
if (Pc_b0 === 1'b0 && Pc_b1 === 1'b0 && Pc_b2 === 1'b0 && Pc_b3 === 1'b0 ) begin
//$display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $realtime);
$display ("Time = %t : ERROR : all banks must be Precharge before Load Mode Register", $realtime);
end
 
// Precharge to Load Mode Register
if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin
//$display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $realtime);
$display ("Time = %t : ERROR : tRP violation(PRECHARGE to MRS)", $realtime);
end
 
// Auto Refresh to Load Mode Register
if ($realtime - RFC_chk < tRFC) begin
//$display ("%m : at time %t ERROR: tRFC violation during Load Mode Register", $realtime);
$display ("Time = %t : ERROR : tRFC violation(AREF to MRS)", $realtime);
end
 
// Load Mode Register to Load Mode Register
if (MRD_chk < tMRD) begin
//$display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $realtime);
$display ("Time = %t : ERROR : tMRD violation(MRS to MRS)", $realtime);
end
 
// Reset MRD Counter
MRD_chk = 0;
end
 
// Load Extended Mode Register
if (EMode_reg_enable === 1'b1) begin
// Register Mode
EMode_reg = addr;
 
// Decode Driver Strength, Maximum Case Temp, Self Refresh Coverage
if (Debug) begin
//$display ("%m : at time %t LMR : Load Mode Register", $realtime);
$display ("Time = %t : OPERATION = EMRS : Load Extended Mode Register", $realtime);
// Driver Strength
case (addr[6 : 5])
2'b00 : $display (" Driver Strength = Full");
2'b01 : $display (" Driver Strength = 1/2");
2'b10 : $display (" Driver Strength = 1/4");
2'b11 : $display (" Driver Strength = 1/8");
default : $display (" Driver Strength = Reserved");
endcase
 
// Self Refresh Coverage
case (addr[2 : 0])
3'b000 : $display (" Self Refresh Coverage = All Banks");
3'b001 : $display (" Self Refresh Coverage = TWO Bank");
3'b010 : $display (" Self Refresh Coverage = One Bank");
3'b101 : $display (" Self Refresh Coverage = Half of one Banks");
3'b110 : $display (" Self Refresh Coverage = Quater of one Banks");
default : $display (" Self Refresh Coverage = Reserved");
endcase
 
end
 
// Precharge to Load Mode Register
if (Pc_b0 === 1'b0 && Pc_b1 === 1'b0 && Pc_b2 === 1'b0 && Pc_b3 === 1'b0) begin
//$display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $realtime);
$display ("Time = %t : ERROR : all banks must be Precharge before Load Mode Register", $realtime);
end
 
// Precharge to Load Mode Register
if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin
//$display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $realtime);
$display ("Time = %t : ERROR : tRP violation(PRECHARGE to EMRS)", $realtime);
end
 
// Auto Refresh to Load Mode Register
if ($realtime - RFC_chk < tRFC) begin
//$display ("%m : at time %t ERROR: tRFC violation during Load Mode Register", $realtime);
$display ("Time = %t : ERROR : tRFC violation(AREF to EMRS)", $realtime);
end
 
// Load Mode Register to Load Mode Register
if (MRD_chk < tMRD) begin
//$display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $realtime);
$display ("Time = %t : ERROR : tMRD violation(MRS to EMRS)", $realtime);
end
 
// Reset MRD Counter
MRD_chk = 0;
end
// Active Block (Latch bank address and Row address)
if (Active_enable === 1'b1) begin
// Activate an open bank can corrupt data
if ((ba === 2'b00 && Act_b0 === 1'b1) || (ba === 2'b01 && Act_b1 === 1'b1) ||
(ba === 2'b10 && Act_b2 === 1'b1) || (ba === 2'b11 && Act_b3 === 1'b1)) begin
//$display ("%m : at time %t ERROR: bank already activated -- data can be corrupted", $realtime);
$display ("Time = %t : ERROR : bank already activated -- data could be corrupted", $realtime);
// $display ("Time = %t : Bank = %d, Act_b0 = %d, Act_b2 = %d", $realtime, ba, Act_b0, Act_b2);
end
 
// Activate bank 0
if (ba === 2'b00 && Pc_b0 === 1'b1) begin
// Debug Message
if (Debug) begin
//$display ("%m : at time %t ACT : bank = 0 Row = %d", $realtime, addr);
$display ("Time = %t : OPERATION = ACT : bank = 0 Row = 'h%h", $realtime, addr);
end
 
// Self exit to ACTIVE
if ($realtime - SELF_chk < tXSR) begin
$display ("Time = %t : ERROR : tXSR violation(SREFX to ACT0)", $realtime);
end
 
// DPDXN to Precharge
if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
$display ("Time = %t : ERROR : Pwrup violation(DPDX to ACT0)", $realtime);
end
 
// ACTIVE to ACTIVE command period
if ($realtime - RC_chk0 < tRC) begin
//$display ("%m : at time %t ERROR: tRC violation during Activate bank 0", $realtime);
$display ("Time = %t : ERROR : tRC violation (ACT0 to ACT0) ", $realtime);
end
 
// Precharge to Activate bank 0
if ($realtime - RP_chk0 < tRP) begin
//$display ("%m : at time %t ERROR: tRP violation during Activate bank 0", $realtime);
$display ("Time = %t : ERROR : tRP violation (PRECHARGE0 to PRECHARGE0) ", $realtime);
end
 
// Record variables
Act_b0 = 1'b1;
Pc_b0 = 1'b0;
B0_row_addr = addr [no_of_addr - 1 : 0];
RAS_chk0 = $realtime;
RC_chk0 = $realtime;
RCD_chk0 = $realtime;
end
 
// Activate bank 1
if (ba === 2'b01 && Pc_b1 === 1'b1) begin
// Debug Message
if (Debug) begin
//$display ("%m : at time %t ACT : bank = 1 Row = %d", $realtime, addr);
$display ("Time = %t : OPERATION = ACT : bank = 1 Row = 'h%h", $realtime, addr);
end
 
// DPDXN to Precharge
if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
$display ("Time = %t : ERROR : Pwrup violation(DPDX to ACT1)", $realtime);
end
 
// Self exit to ACTIVE
if ($realtime - SELF_chk < tXSR) begin
$display ("Time = %t : ERROR : tXSR violation(SREFX to ACT1)", $realtime);
end
 
// ACTIVE to ACTIVE command period
if ($realtime - RC_chk1 < tRC) begin
//$display ("%m : at time %t ERROR: tRC violation during Activate bank 1", $realtime);
$display ("Time = %t : ERROR : tRC violation (ACT1 to ACT1) ", $realtime);
end
 
// Precharge to Activate bank 1
if ($realtime - RP_chk1 < tRP) begin
//$display ("%m : at time %t ERROR: tRP violation during Activate bank 1", $realtime);
$display ("Time = %t : ERROR : tRP violation (PRECHARGE1 to PRECHARGE1) ", $realtime);
end
 
// Record variables
Act_b1 = 1'b1;
Pc_b1 = 1'b0;
B1_row_addr = addr [no_of_addr - 1 : 0];
RAS_chk1 = $realtime;
RC_chk1 = $realtime;
RCD_chk1 = $realtime;
end
 
// Activate bank 2
if (ba === 2'b10 && Pc_b2 === 1'b1) begin
// Debug Message
if (Debug) begin
//$display ("%m : at time %t ACT : bank = 2 Row = %d", $realtime, addr);
$display ("Time = %t : OPERATION = ACT : bank = 2 Row = 'h%h", $realtime, addr);
end
 
// DPDXN to Precharge
if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
$display ("Time = %t : ERROR : Pwrup violation(DPDX to ACT2)", $realtime);
end
 
// Self exit to ACTIVE
if ($realtime - SELF_chk < tXSR) begin
$display ("Time = %t : ERROR : tXSR violation(SREFX to ACT2)", $realtime);
end
 
// ACTIVE to ACTIVE command period
if ($realtime - RC_chk2 < tRC) begin
//$display ("%m : at time %t ERROR: tRC violation during Activate bank 2", $realtime);
$display ("Time = %t : ERROR : tRC violation (ACT2 to ACT2) ", $realtime);
end
 
// Precharge to Activate bank 2
if ($realtime - RP_chk2 < tRP) begin
//$display ("%m : at time %t ERROR: tRP violation during Activate bank 2", $realtime);
$display ("Time = %t : ERROR : tRP violation (PRECHARGE2 to PRECHARGE2) ", $realtime);
end
 
// Record variables
Act_b2 = 1'b1;
Pc_b2 = 1'b0;
B2_row_addr = addr [no_of_addr - 1 : 0];
RAS_chk2 = $realtime;
RC_chk2 = $realtime;
RCD_chk2 = $realtime;
end
 
// Activate bank 3
if (ba === 2'b11 && Pc_b3 === 1'b1) begin
// Debug Message
if (Debug) begin
//$display ("%m : at time %t ACT : bank = 3 Row = %d", $realtime, addr);
$display ("Time = %t : OPERATION = ACT : bank = 3 Row = 'h%h", $realtime, addr);
end
 
// DPDXN to Precharge
if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
$display ("Time = %t : ERROR : Pwrup violation(DPDX to ACT3)", $realtime);
end
 
// Self exit to ACTIVE
if ($realtime - SELF_chk < tXSR) begin
$display ("Time = %t : ERROR : tXSR violation(SREFX to ACT3)", $realtime);
end
 
// ACTIVE to ACTIVE command period
if ($realtime - RC_chk3 < tRC) begin
//$display ("%m : at time %t ERROR: tRC violation during Activate bank 3", $realtime);
$display ("Time = %t : ERROR : tRC violation (ACT1 to ACT3) ", $realtime);
end
 
// Precharge to Activate bank 3
if ($realtime - RP_chk3 < tRP) begin
//$display ("%m : at time %t ERROR: tRP violation during Activate bank 3", $realtime);
$display ("Time = %t : ERROR : tRP violation (PRECHARGE3 to PRECHARGE3) ", $realtime);
end
 
// Record variables
Act_b3 = 1'b1;
Pc_b3 = 1'b0;
B3_row_addr = addr [no_of_addr - 1 : 0];
RAS_chk3 = $realtime;
RC_chk3 = $realtime;
RCD_chk3 = $realtime;
end
 
// Active other bank to Active bank A
if ((Prev_bank != ba) && ($realtime - RRD_chk < tRRD) && (ba === 2'b00)) begin
//$display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $realtime, ba);
$display ("Time = %t : ERROR : tRRD violation(ACT Others to ACT0) ", $realtime);
end
 
// Active other bank to Active bank B
if ((Prev_bank != ba) && ($realtime - RRD_chk < tRRD) && (ba === 2'b01)) begin
//$display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $realtime, ba);
$display ("Time = %t : ERROR : tRRD violation(ACT Others to ACT1) ", $realtime);
end
 
// Active other bank to Active bank C
if ((Prev_bank != ba) && ($realtime - RRD_chk < tRRD) && (ba === 2'b10)) begin
//$display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $realtime, ba);
$display ("Time = %t : ERROR : tRRD violation(ACT Others to ACT2) ", $realtime);
end
 
// Active other bank to Active bank D
if ((Prev_bank != ba) && ($realtime - RRD_chk < tRRD) && (ba === 2'b11)) begin
//$display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $realtime, ba);
$display ("Time = %t : ERROR : tRRD violation(ACT Others to ACT3) ", $realtime);
end
 
// Auto Refresh to Activate
if ($realtime - RFC_chk < tRFC) begin
//$display ("%m : at time %t ERROR: tRFC violation during Activate bank = %d", $realtime, ba);
$display ("Time = %t : ERROR : tRFC violation(AREF to ACT)", $realtime);
end
 
// Load Mode Register to Active
if (MRD_chk < tMRD ) begin
//$display ("%m : at time %t ERROR: tMRD violation during Activate bank = %d", $realtime, ba);
$display ("Time = %t : ERROR : tMRD violation(MRS to ACT)", $realtime);
end
 
// Record variables for checking violation
RRD_chk = $realtime;
Prev_bank = ba;
end
// Precharge Block
if (Prech_enable == 1'b1) begin
// Load Mode Register to Precharge
if ($realtime - MRD_chk < tMRD) begin
//$display ("%m : at time %t ERROR: tMRD violaiton during Precharge", $realtime);
$display ("Time = %t : ERROR : tMRD violation(MRS to PRECHARGE)", $realtime);
end
 
//Precharge bank 0
 
if ((addr[10] === 1'b1 || (addr[10] === 1'b0 && ba === 2'b00)) && Act_b0 === 1'b1) begin
Act_b0 = 1'b0;
Pc_b0 = 1'b1;
RP_chk0 = $realtime;
 
if (Debug) begin
//$display ("%m : at time %t ACT : bank = 0 Row = %d", $realtime, addr);
$display ("Time = %t : OPERATION = PCHG : bank = 0 ", $realtime);
end
 
// DPDXN to Precharge
if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
$display ("Time = %t : ERROR : Pwrup violation(DPDX to PRECHARGE0)", $realtime);
end
 
// Activate to Precharge
if ($realtime - RAS_chk0 < tRAS) begin
//$display ("%m : at time %t ERROR: tRAS violation during Precharge", $realtime);
$display ("Time = %t : ERROR : tRAS violation(ACT0 to PRECHARGE0)", $realtime);
end
 
// tWR violation check for write
if ($realtime - WR_chkm0 < tDPLm) begin
//$display ("%m : at time %t ERROR: tWR violation during Precharge", $realtime);
$display ("Time = %t : ERROR : tDPL violation(LAST DATA to PRECHARGE0)", $realtime);
end
end
 
// Precharge bank 1
 
if ((addr[10] === 1'b1 || (addr[10] === 1'b0 && ba === 2'b01)) && Act_b1 === 1'b1) begin
Act_b1 = 1'b0;
Pc_b1 = 1'b1;
RP_chk1 = $realtime;
 
if (Debug) begin
//$display ("%m : at time %t ACT : bank = 1 Row = %d", $realtime, addr);
$display ("Time = %t : OPERATION = PCHG : bank = 1 ", $realtime);
end
 
// DPDXN to Precharge
if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
$display ("Time = %t : ERROR : Pwrup violation(DPDX to PRECHARGE1)", $realtime);
end
 
// Activate to Precharge
if ($realtime - RAS_chk1 < tRAS) begin
//$display ("%m : at time %t ERROR: tRAS violation during Precharge", $realtime);
$display ("Time = %t : ERROR : tRAS violation(ACT1 to PRECHARGE1)", $realtime);
end
 
// tWR violation check for write
if ($realtime - WR_chkm1 < tDPLm) begin
//$display ("%m : at time %t ERROR: tWR violation during Precharge", $realtime);
$display ("Time = %t : ERROR : tDPL violation(LAST DATA to PRECHARGE1)", $realtime);
end
end
 
// Precharge bank 2
 
if ((addr[10] === 1'b1 || (addr[10] === 1'b0 && ba === 2'b10)) && Act_b2 === 1'b1) begin
Act_b2 = 1'b0;
Pc_b2 = 1'b1;
RP_chk2 = $realtime;
 
if (Debug) begin
//$display ("%m : at time %t ACT : bank = 2 Row = %d", $realtime, addr);
$display ("Time = %t : OPERATION = PCHG : bank = 2 ", $realtime);
end
 
// DPDXN to Precharge
if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
$display ("Time = %t : ERROR : Pwrup violation(DPDX to PRECHARGE2)", $realtime);
end
 
// Activate to Precharge
if ($realtime - RAS_chk2 < tRAS) begin
//$display ("%m : at time %t ERROR: tRAS violation during Precharge", $realtime);
$display ("Time = %t : ERROR : tRAS violation(ACT2 to PRECHARGE2)", $realtime);
end
 
// tWR violation check for write
if ($realtime - WR_chkm2 < tDPLm) begin
//$display ("%m : at time %t ERROR: tWR violation during Precharge", $realtime);
$display ("Time = %t : ERROR : tDPL violation(LAST DATA to PRECHARGE2)", $realtime);
end
end
 
// Precharge bank 3
 
if ((addr[10] === 1'b1 || (addr[10] === 1'b0 && ba === 2'b11)) && Act_b3 === 1'b1) begin
Act_b3 = 1'b0;
Pc_b3 = 1'b1;
RP_chk3 = $realtime;
 
if (Debug) begin
//$display ("%m : at time %t ACT : bank = 3 Row = %d", $realtime, addr);
$display ("Time = %t : OPERATION = PCHG : bank = 3 ", $realtime);
end
 
// DPDXN to Precharge
if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
$display ("Time = %t : ERROR : Pwrup violation(DPDX to PRECHARGE3)", $realtime);
end
 
// Activate to Precharge
if ($realtime - RAS_chk3 < tRAS) begin
//$display ("%m : at time %t ERROR: tRAS violation during Precharge", $realtime);
$display ("Time = %t : ERROR : tRAS violation(ACT3 to PRECHARGE3)", $realtime);
end
 
// tWR violation check for write
if ($realtime - WR_chkm3 < tDPLm) begin
//$display ("%m : at time %t ERROR: tWR violation during Precharge", $realtime);
$display ("Time = %t : ERROR : tDPL violation(LAST DATA to PRECHARGE3)", $realtime);
end
end
 
 
// Terminate a Write Immediately (if same bank or all banks)
if (Data_in_enable === 1'b1 && (bank === ba || addr[10] === 1'b1)) begin
Data_in_enable = 1'b0;
end
 
// Precharge Command Pipeline for Read
if (Cas_latency_3 === 1'b1) begin
Command[2] = `PRECH;
bank_precharge[2] = ba;
A10_precharge[2] = addr[10];
end else if (Cas_latency_2 === 1'b1) begin
Command[1] = `PRECH;
bank_precharge[1] = ba;
A10_precharge[1] = addr[10];
end
end
// Burst terminate
if (Burst_term === 1'b1) begin
// Terminate a Write Immediately
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
end
 
// Terminate a Read Depend on CAS Latency
if (Cas_latency_3 === 1'b1) begin
Command[2] = `BST;
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `BST;
end
 
// Display debug message
if (Debug) begin
//$display ("%m : at time %t BST : Burst Terminate",$realtime);
$display ("Time = %t : OPERATION = BST : Burst Stop", $realtime);
end
end
// Read, Write, Column Latch
if (Read_enable === 1'b1) begin
 
Read_cmd_received = 1'b1;
Read_cmd_received_cke = 1'b1;
//Read_cmd_count = 0;
Count_at_Read = Read_cmd_count;
Read_cmd_count_cke = 0;
Write_cmd_received_cke = 1'b0;
 
// Check to see if bank is open (ACT)
if ((ba == 2'b00 && Pc_b0 == 1'b1) || (ba == 2'b01 && Pc_b1 == 1'b1) ||
(ba == 2'b10 && Pc_b2 == 1'b1) || (ba == 2'b11 && Pc_b3 == 1'b1)) begin
//$display("%m : at time %t ERROR: bank is not Activated for Read", $realtime);
$display ("Time = %t : ERROR : bank is not Activated for Read", $realtime);
end
 
// Activate to Read or Write
if ((ba == 2'b00) && ($realtime - RCD_chk0 < tRCD) ||
(ba == 2'b01) && ($realtime - RCD_chk1 < tRCD) ||
(ba == 2'b10) && ($realtime - RCD_chk2 < tRCD) ||
(ba == 2'b11) && ($realtime - RCD_chk3 < tRCD)) begin
//$display("%m : at time %t ERROR: tRCD violation during Read", $realtime);
$display ("Time = %t : ERROR : tRCD violation(ACT to READ)", $realtime);
end
 
// CAS Latency pipeline
if (Cas_latency_3 == 1'b1) begin
Command[2] = `READ;
Col_addr[2] = addr;
bank_addr[2] = ba;
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `READ;
Col_addr[1] = addr;
bank_addr[1] = ba;
end
 
// Read interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
 
// Interrupting a Write with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_write[RW_interrupt_bank] = 1'b1;
RW_interrupt_counter[RW_interrupt_bank] = 0;
 
// Display debug message
if (Debug) begin
//$display ("%m : at time %t NOTE : Read interrupt Write with Autoprecharge", $realtime);
$display ("Time = %t : OPERATION = Read interrupt Write with Autoprecharge", $realtime);
end
end
end
 
// Read with Auto Precharge
if (addr[10] == 1'b1) begin
Auto_precharge[ba] = 1'b1;
Count_precharge[ba] = 0;
RW_interrupt_bank = ba;
Read_precharge[ba] = 1'b1;
end
end
 
// Write Command
if (Write_enable == 1'b1) begin
 
RIW_violate=1'b0;
if ((Pre_Dout_Drive_Flag == 1'b1) || (Dout_Drive_Flag == 1'b1)) begin
$display ("Time = %t : ERROR : Read and Write Data collision", $realtime);
end
else if ((Data_out_enable == 1'b1) && (&(dqm_save[1]) != 1'b1)) begin
$display ("Time = %t : ERROR : Read and Write Data collision", $realtime);
end
 
 
Write_cmd_received_cke=1'b1;
Read_cmd_received=1'b0;
Read_cmd_received_cke=1'b0;
Write_cmd_count_cke=1'b0;
 
// Activate to Write
if ((ba == 2'b00 && Pc_b0 == 1'b1) || (ba == 2'b01 && Pc_b1 == 1'b1) ||
(ba == 2'b10 && Pc_b2 == 1'b1) || (ba == 2'b11 && Pc_b3 == 1'b1)) begin
//$display("%m : at time %t ERROR: bank is not Activated for Write", $realtime);
$display ("Time = %t : ERROR : bank is not Activated for Write", $realtime);
end
 
if ((ba == 2'b00) && ($realtime - RCD_chk0 < tRCD)) begin
$display ("Time = %t : ERROR = %t, %t: tRCD violation(ACT0 to WRITE)", $realtime, RCD_chk0,$realtime-RCD_chk0);
end
if ((ba == 2'b01) && ($realtime - RCD_chk1 < tRCD)) begin
$display ("Time = %t : ERROR = %t, %t: tRCD violation(ACT1 to WRITE)", $realtime, RCD_chk1,$realtime-RCD_chk1);
end
if ((ba == 2'b10) && ($realtime - RCD_chk2 < tRCD)) begin
$display ("Time = %t : ERROR = %t, %t: tRCD violation(ACT2 to WRITE)", $realtime, RCD_chk2,$realtime-RCD_chk2);
end
if ((ba == 2'b11) && ($realtime - RCD_chk3 < tRCD)) begin
$display ("Time = %t : ERROR = %t, %t: tRCD violation(ACT3 to WRITE)", $realtime, RCD_chk3,$realtime-RCD_chk3);
end
 
 
// Latch Write command, bank, and Column
Command[0] = `WRITE;
Command[1] = `NOP;
Col_addr[0] = addr;
bank_addr[0] = ba;
 
// Write interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
 
// Interrupting a Write with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_write[RW_interrupt_bank] = 1'b1;
 
// Display debug message
if (Debug) begin
//$display ("%m : at time %t NOTE : Read bank %d interrupt Write bank %d with Autoprecharge", $realtime, ba, RW_interrupt_bank);
$display ("Time = %t : OPERATION = Write bank %d interrupt Write bank %d with Autoprecharge", $realtime, ba, RW_interrupt_bank);
 
end
end
end
 
// Write interrupt Read (terminate Read immediately)
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
// Interrupting a Read with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Read_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_read[RW_interrupt_bank] = 1'b1;
 
// Display debug message
if (Debug) begin
//$display ("%m : at time %t NOTE : Write bank %d interrupt Read bank %d with Autoprecharge", $realtime, ba, RW_interrupt_bank);
$display ("Time = %t : OPERATION = Write bank %d interrupt Read bank %d with Autoprecharge", $realtime, ba, RW_interrupt_bank);
end
end
end
 
// Write with Auto Precharge
if (addr[10] == 1'b1) begin
Auto_precharge[ba] = 1'b1;
Count_precharge[ba] = 0;
RW_interrupt_bank = ba;
Write_precharge[ba] = 1'b1;
end
end
 
/*
Write with Auto Precharge Calculation
The device start internal precharge when:
1. Meet minimum tRAS requirement
and 2. tWR cycle(s) after last valid data
or 3. Interrupt by a Read or Write (with or without Auto Precharge)
 
Note: Model is starting the internal precharge 1 cycle after they meet all the
requirement but tRP will be compensate for the time after the 1 cycle.
*/
if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin
if ((($realtime - RAS_chk0 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) ||
(RW_interrupt_write[0] == 1'b1 && RW_interrupt_counter[0] >= 1)) begin // Case 3
Auto_precharge[0] = 1'b0;
Write_precharge[0] = 1'b0;
RW_interrupt_write[0] = 1'b0;
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $realtime + tDPLa;
if (Debug) begin
//$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 0", $realtime);
$display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 0", $realtime+tDPLa);
end
end
end
if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin
if ((($realtime - RAS_chk1 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) ||
(RW_interrupt_write[1] == 1'b1 && RW_interrupt_counter[1] >= 1)) begin // Case 3
Auto_precharge[1] = 1'b0;
Write_precharge[1] = 1'b0;
RW_interrupt_write[1] = 1'b0;
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $realtime + tDPLa;
if (Debug) begin
//$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 1", $realtime);
$display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 1", $realtime+tDPLa);
end
end
end
if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin
if ((($realtime - RAS_chk2 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) ||
(RW_interrupt_write[2] == 1'b1 && RW_interrupt_counter[2] >= 1)) begin // Case 3
Auto_precharge[2] = 1'b0;
Write_precharge[2] = 1'b0;
RW_interrupt_write[2] = 1'b0;
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $realtime + tDPLa;
if (Debug) begin
//$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 2", $realtime);
$display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 2", $realtime+tDPLa);
end
end
end
if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin
if ((($realtime - RAS_chk3 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) ||
(RW_interrupt_write[3] == 1'b1 && RW_interrupt_counter[3] >= 1)) begin // Case 3
Auto_precharge[3] = 1'b0;
Write_precharge[3] = 1'b0;
RW_interrupt_write[3] = 1'b0;
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $realtime + tDPLa;
if (Debug) begin
//$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 3", $realtime);
$display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 3", $realtime+tDPLa);
end
end
end
 
// Read with Auto Precharge Calculation
// The device start internal precharge:
// 1. Meet minimum tRAS requirement
// and 2. CAS Latency - 1 cycles before last burst
// or 3. Interrupt by a Read or Write (with or without AutoPrecharge)
if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin
if ((($realtime - RAS_chk0 >= tRAS) && // Case 1
((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
(RW_interrupt_read[0] == 1'b1)) begin // Case 3
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $realtime;
Auto_precharge[0] = 1'b0;
Read_precharge[0] = 1'b0;
RW_interrupt_read[0] = 1'b0;
if (Debug) begin
//$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 0", $realtime);
$display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 0", $realtime);
end
end
end
if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin
if ((($realtime - RAS_chk1 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
(RW_interrupt_read[1] == 1'b1)) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $realtime;
Auto_precharge[1] = 1'b0;
Read_precharge[1] = 1'b0;
RW_interrupt_read[1] = 1'b0;
if (Debug) begin
//$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 1", $realtime);
$display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 1", $realtime);
end
end
end
if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin
if ((($realtime - RAS_chk2 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
(RW_interrupt_read[2] == 1'b1)) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $realtime;
Auto_precharge[2] = 1'b0;
Read_precharge[2] = 1'b0;
RW_interrupt_read[2] = 1'b0;
if (Debug) begin
//$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 2", $realtime);
$display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 2", $realtime);
end
end
end
if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin
if ((($realtime - RAS_chk3 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
(RW_interrupt_read[3] == 1'b1)) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $realtime;
Auto_precharge[3] = 1'b0;
Read_precharge[3] = 1'b0;
RW_interrupt_read[3] = 1'b0;
if (Debug) begin
//$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 3", $realtime);
$display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 3", $realtime);
end
end
end
 
// CKE Function
if (cke === 1'b0) begin
if (Sref_enable === 1'b1) begin
state_self = 1'b1;
if (Debug) begin
$display ("Time = %t : OPERATION = SREF : Self Refresh", $realtime);
if (EMode_reg[2:0]==3'b000) $display (" Refresh Full Bank");
 
if (EMode_reg[2:0]==3'b001) begin
$display (" Refresh Only TWO Bank");
abbank_init;
end
 
if (EMode_reg[2:0]==3'b010) begin
$display (" Refresh Only One Bank(BANK A)");
bbank_init;
end
if (EMode_reg[2:0]==3'b101) begin
$display (" Refresh Only half of one Bank(BANK A, A10=0)");
half_init;
end
if (EMode_reg[2:0]==3'b110) begin
$display (" Refresh Only Quarter of one Bank(BANK A, A10=0)");
quat_init;
end
end
 
// Precharge to Auto Refresh
if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP))
$display ("Time = %t : ERROR : tRP violation(PRECHARGE to SREF)", $realtime);
 
// Precharge to Refresh
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0)
$display ("Time = %t : ERROR : All banks must be Precharged before SREF", $realtime);
 
// Load Mode Register to Self Refresh
if (MRD_chk < tMRD)
$display ("Time = %t : ERROR : tMRD violation(MRS to SREF)", $realtime);
 
end else if (Deep_pwrdn == 1'b1) begin
state_dpdn = 1'b1;
dpdn_check_start = 1'b1;
Act_b0 = 0; Act_b1 = 0; Act_b2 = 0; Act_b3 = 0;
Pc_b0 = 1; Pc_b1 = 1; Pc_b2 = 1; Pc_b3 = 1;
mem_init;
if (Debug) $display ("Time = %t : OPERATION = DPDN : Deep Powerdown", $realtime);
 
// Precharge to Auto Refresh
if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP))
$display ("Time = %t : ERROR : tRP violation(PRECHARGE to DPDN)", $realtime);
 
// Precharge to Refresh
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0)
$display ("Time = %t : ERROR : All banks must be Precharged before DPDN", $realtime);
 
end else if (act_pwrdn == 1'b1) begin
state_act_pwrdn = 1'b1;
if (Debug) $display ("Time = %t : OPERATION = APDN : Active Power down", $realtime);
end else if (pch_pwrdn == 1'b1) begin
state_pre_pwrdn = 1'b1;
if (Debug) $display ("Time = %t : OPERATION = PPDN : Precharge Power down", $realtime);
end else if (clk_suspend_write == 1'b1) begin
if (Debug) $display ("Time = %t : OPERATION = CKSW : Clock Suspend during Write", $realtime);
end else if (clk_suspend_read == 1'b1) begin
if (Debug) $display ("Time = %t : OPERATION = CKSR : Clock Suspend during Read", $realtime);
end
end
 
// Internal Precharge or Bst
if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks
if (bank_precharge[0] == bank || A10_precharge[0] == 1'b1) begin
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
end else if (Command[0] == `BST) begin // BST terminate a read to current bank
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
 
if (Data_out_enable == 1'b0) begin
dq_reg <= #tOH {no_of_data{1'bz}};
Dout_Drive_Flag <= #tOH 1'b0;
end
 
// Detect Read or Write command
if (Command[0] == `READ) begin
bank = bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
case (bank_addr[0])
2'b00 : Row = B0_row_addr;
2'b01 : Row = B1_row_addr;
2'b10 : Row = B2_row_addr;
2'b11 : Row = B3_row_addr;
 
endcase
Burst_counter = 0;
Data_in_enable = 1'b0;
Data_out_enable = 1'b1;
end else if (Command[0] == `WRITE) begin
bank = bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
case (bank_addr[0])
2'b00 : Row = B0_row_addr;
2'b01 : Row = B1_row_addr;
2'b10 : Row = B2_row_addr;
2'b11 : Row = B3_row_addr;
endcase
Burst_counter = 0;
Data_in_enable = 1'b1;
Data_out_enable = 1'b0;
end
 
// DQ buffer (Driver/Receiver)
if (Data_in_enable == 1'b1) begin // Writing Data to Memory
// Array buffer
case (bank)
2'b00 : dq_dqm = bank0 [{Row, Col}];
2'b01 : dq_dqm = bank1 [{Row, Col}];
2'b10 : dq_dqm = bank2 [{Row, Col}];
2'b11 : dq_dqm = bank3 [{Row, Col}];
endcase
 
// dqm operation
if (dqm[0] == 1'b0) begin
dq_dqm [ 7 : 0] = dq [ 7 : 0 ] & dq [ 7 : 0 ];
end
if (dqm[1] == 1'b0) begin
dq_dqm [15 : 8] = dq [15 : 8] & dq [15 : 8];
end
 
// Write to memory
case (bank)
2'b00 : bank0 [{Row, Col}] = dq_dqm;
2'b01 : bank1 [{Row, Col}] = dq_dqm;
2'b10 : bank2 [{Row, Col}] = dq_dqm;
2'b11 : bank3 [{Row, Col}] = dq_dqm;
endcase
 
// Display debug message
if (dqm !== 2'b11) begin
// Record tWR for manual precharge
if (bank == 2'b00) WR_chkm0 = $realtime;
if (bank == 2'b01) WR_chkm1 = $realtime;
if (bank == 2'b10) WR_chkm2 = $realtime;
if (bank == 2'b11) WR_chkm3 = $realtime;
 
if (Debug) begin
//$display("%m : at time %t WRITE: bank = %d Row = %d, Col = %d, Data = %d", $realtime, bank, Row, Col, dq_dqm);
$display ("Time = %t : OPERATION = WRITE : bank = %d Row = 'h%h, Col = 'h%h, Data = 'h%h", $realtime, bank, Row, Col, dq_dqm);
end
end else begin
if (Debug) begin
//$display("%m : at time %t WRITE: bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $realtime, bank, Row, Col);
$display ("Time = %t : OPERATION = WRITE : bank = %d Row = 'h%h, Col = 'h%h, Data = Hi-Z due to DQM", $realtime, bank, Row, Col);
end
end
 
// Advance burst counter subroutine
 
if(Cas_latency_2 == 1) begin
 
#tHZ2 Burst_decode;
 
end else if(Cas_latency_3 == 1) begin
 
#tHZ3 Burst_decode;
 
end
 
 
end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory
// Array buffer
case (bank)
2'b00 : dq_dqm = bank0[{Row, Col}];
2'b01 : dq_dqm = bank1[{Row, Col}];
2'b10 : dq_dqm = bank2[{Row, Col}];
2'b11 : dq_dqm = bank3[{Row, Col}];
endcase
 
 
// dqm operation
if (dqm_reg0 [0] == 1'b1) begin
dq_dqm [ 7 : 0] = 8'bz;
end
if (dqm_reg0 [1] == 1'b1) begin
dq_dqm [15 : 8] = 8'bz;
end
 
if(Cas_latency_2 ==1) begin
 
// Display debug message
if ( &(dqm_reg0) != 1'b1) begin
dq_reg = #tAC2 dq_dqm;
Dout_Drive_Flag = 1'b1;
if (Debug) begin
//$display("%m : at time %t READ : bank = %d Row = %d, Col = %d, Data = %d", $realtime, bank, Row, Col, dq_reg);
$display ("Time = %t : OPERATION = READ : bank = %d Row = 'h%h, Col = 'h%h, Data = 'h%h", $realtime, bank, Row, Col, dq_reg);
end
end else begin
dq_reg = #tHZ2 {no_of_data{1'bz}};
Dout_Drive_Flag = 1'b0;
if (Debug) begin
//$display("%m : at time %t READ : bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $realtime, bank, Row, Col);
$display ("Time = %t : OPERATION = READ : bank = %d Row = 'h%h, Col = 'h%h, Data = Hi-Z due to DQM", $realtime, bank, Row, Col);
 
end
end
 
end else if(Cas_latency_3 ==1) begin
 
// Display debug message
if ( &(dqm_reg0) != 1'b1) begin
dq_reg = #tAC3 dq_dqm;
Dout_Drive_Flag = 1'b1;
if (Debug) begin
//$display("%m : at time %t READ : bank = %d Row = %d, Col = %d, Data = %d", $realtime, bank, Row, Col, dq_reg);
$display ("Time = %t : OPERATION = READ : bank = %d Row = 'h%h, Col = 'h%h, Data = 'h%h", $realtime, bank, Row, Col, dq_reg);
end
end else begin
dq_reg = #tHZ3 {no_of_data{1'bz}};
Dout_Drive_Flag = 1'b0;
if (Debug) begin
//$display("%m : at time %t READ : bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $realtime, bank, Row, Col);
$display ("Time = %t : OPERATION = READ : bank = %d Row = 'h%h, Col = 'h%h, Data = Hi-Z due to DQM", $realtime, bank, Row, Col);
 
end
end
 
end
// Advance burst counter subroutine
Burst_decode;
end
end
 
// Burst counter decode
task Burst_decode;
begin
// Advance Burst Counter
Burst_counter = Burst_counter + 1;
 
// Burst Type
if (Mode_reg[3] == 1'b0) begin // Sequential Burst
Col_temp = Col + 1;
end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst
Col_temp[2] = Burst_counter[2] ^ Col_brst[2];
Col_temp[1] = Burst_counter[1] ^ Col_brst[1];
Col_temp[0] = Burst_counter[0] ^ Col_brst[0];
end
 
// Burst Length
if (Burst_length_2) begin // Burst Length = 2
Col [0] = Col_temp [0];
end else if (Burst_length_4) begin // Burst Length = 4
Col [1 : 0] = Col_temp [1 : 0];
end else if (Burst_length_8) begin // Burst Length = 8
Col [2 : 0] = Col_temp [2 : 0];
end else begin // Burst Length = FULL
Col = Col_temp;
end
 
// Burst Read Single Write
if (Write_burst_mode == 1'b1) begin
Data_in_enable = 1'b0;
end
 
// Data Counter
if (Burst_length_1 == 1'b1) begin
if (Burst_counter >= 1) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_2 == 1'b1) begin
if (Burst_counter >= 2) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_4 == 1'b1) begin
if (Burst_counter >= 4) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_8 == 1'b1) begin
if (Burst_counter >= 8) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end
end
endtask
 
task mem_init;
begin
for (ccc=0;ccc<'b1000_0000_0000_0000_0000;ccc=ccc+1)
begin
bank0[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
bank1[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
bank2[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
bank3[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
//bank0[ccc]=16'b1111_1111_1111_1111;
//bank1[ccc]=16'b1111_1111_1111_1111;
end
end
endtask
 
task abbank_init;
begin
for (ccc=0;ccc<'b1000_0000_0000_0000_0000;ccc=ccc+1)
begin
bank0[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
bank1[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
end
end
endtask
 
 
task bbank_init;
begin
for (ccc=0;ccc<'b1000_0000_0000_0000_0000;ccc=ccc+1)
begin
bank1[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
end
end
endtask
 
task half_init;
begin
bbank_init;
for (ccc='b0100_0000_0000_0000_0000;ccc<'b1000_0000_0000_0000_0000;ccc=ccc+1)
begin
bank0[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
end
end
endtask
 
task quat_init;
begin
bbank_init;
for (ccc='b0010_0000_0000_0000_0000;ccc<'b1000_0000_0000_0000_0000;ccc=ccc+1)
begin
bank0[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
end
end
endtask
`endprotect
 
// Timing Parameters
specify
specparam
`ifdef S50
tAH = 1.0, // addr, ba Hold Time
tAS = 1.5, // addr, ba Setup Time
tCH = 2.5, // Clock High-Level Width
tCL = 2.5, // Clock Low-Level Width
tCK = 5.0, // Clock Cycle Time
tDH = 1.0, // Data-in Hold Time
tDS = 1.5, // Data-in Setup Time
tCKH = 1.0, // CKE Hold Time
tCKS = 1.5, // CKE Setup Time
tCMH = 1.0, // CSB, RASB, CASB, WEB, DQMB Hold Time
tCMS = 1.5; // CSB, RASB, CASB, WEB, DQMB Setup Time
`endif
 
`ifdef S60
tAH = 1.0, // addr, ba Hold Time
tAS = 1.5, // addr, ba Setup Time
tCH = 2.5, // Clock High-Level Width
tCL = 2.5, // Clock Low-Level Width
tCK = 6.0, // Clock Cycle Time
tDH = 1.0, // Data-in Hold Time
tDS = 1.5, // Data-in Setup Time
tCKH = 1.0, // CKE Hold Time
tCKS = 1.5, // CKE Setup Time
tCMH = 1.0, // CSB, RASB, CASB, WEB, DQMB Hold Time
tCMS = 1.5; // CSB, RASB, CASB, WEB, DQMB Setup Time
`endif
 
`ifdef S75
tAH = 1.0, // addr, ba Hold Time
tAS = 2.0, // addr, ba Setup Time
tCH = 2.5, // Clock High-Level Width
tCL = 2.5, // Clock Low-Level Width
tCK = 7.5, // Clock Cycle Time
tDH = 1.0, // Data-in Hold Time
tDS = 2.0, // Data-in Setup Time
tCKH = 1.0, // CKE Hold Time
tCKS = 2.0, // CKE Setup Time
tCMH = 1.0, // CSB, RASB, CASB, WEB, DQMB Hold Time
tCMS = 2.0; // CSB, RASB, CASB, WEB, DQMB Setup Time
`endif
 
 
$width (posedge clk, tCH);
$width (negedge clk, tCL);
$period (negedge clk, tCK);
$period (posedge clk, tCK);
$setuphold(posedge clk, cke, tCKS, tCKH);
$setuphold(posedge clk, csb, tCMS, tCMH);
$setuphold(posedge clk, casb, tCMS, tCMH);
$setuphold(posedge clk, rasb, tCMS, tCMH);
$setuphold(posedge clk, web, tCMS, tCMH);
$setuphold(posedge clk, addr, tAS, tAH);
$setuphold(posedge clk, ba, tAS, tAH);
$setuphold(posedge clk, dqm, tCMS, tCMH);
$setuphold(posedge dq_chk, dq, tDS, tDH);
endspecify
 
 
endmodule
/testbench/MT48LC8M16A2.v
0,0 → 1,963
/****************************************************************************************
*
* File Name: MT48LC8M16A2.V
* Version: 0.0f
* Date: July 8th, 1999
* Model: BUS Functional
* Simulator: Model Technology (PC version 5.2e PE)
*
* Dependencies: None
*
* Author: Son P. Huynh
* Email: sphuynh@micron.com
* Phone: (208) 368-3825
* Company: Micron Technology, Inc.
* Model: MT48LC8M16A2 (2Meg x 16 x 4 Banks)
*
* Description: Micron 128Mb SDRAM Verilog model
*
* Limitation: - Doesn't check for 4096 cycle refresh
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set Debug = 0 to disable $display messages
*
* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
*
* Copyright � 1998 Micron Semiconductor Products, Inc.
* All rights researved
*
* Rev Author Phone Date Changes
* ---- ---------------------------- ---------- ---------------------------------------
* 0.0f Son Huynh 208-368-3825 07/08/1999 - Fix tWR = 1 clk + 7.5 ns (Auto)
* Micron Technology Inc. - Fix tWR = 15 ns (Manual)
* - Fix tRP (Autoprecharge to AutoRefresh)
*
* 0.0a Son Huynh 208-368-3825 05/13/1998 - First Release (from 64Mb rev 0.0e)
* Micron Technology Inc.
****************************************************************************************/
`timescale 1ns / 100ps
module MT48LC8M16A2 (dq, addr, ba, clk, cke, csb, rasb, casb, web, dqm);
 
parameter addr_bits = 13;
parameter data_bits = 16;
parameter col_bits = 9;
parameter mem_sizes = 2097151; // 2 Meg
inout [data_bits - 1 : 0] dq;
input [addr_bits - 1 : 0] addr;
input [1 : 0] ba;
input clk;
input cke;
input csb;
input rasb;
input casb;
input web;
input [1 : 0] dqm;
reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline
reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline
reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline
reg [1 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline
reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
reg [addr_bits - 1 : 0] Mode_reg;
reg [data_bits - 1 : 0] Dq_reg, Dq_dqm;
reg [col_bits - 1 : 0] Col_temp, Burst_counter;
reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate
reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge
reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command
reg A10_precharge [0 : 3]; // addr[10] = 1 (All banks)
reg Auto_precharge [0 : 3]; // RW AutoPrecharge (Bank)
reg Read_precharge [0 : 3]; // R AutoPrecharge
reg Write_precharge [0 : 3]; // W AutoPrecharge
integer Count_precharge [0 : 3]; // RW AutoPrecharge (Counter)
reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge
reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge
reg Data_in_enable;
reg Data_out_enable;
reg [1 : 0] Bank, Previous_bank;
reg [addr_bits - 1 : 0] Row;
reg [col_bits - 1 : 0] Col, Col_brst;
// Internal system clock
reg CkeZ, Sys_clk;
// Commands Decode
wire Active_enable = ~csb & ~rasb & casb & web;
wire Aref_enable = ~csb & ~rasb & ~casb & web;
wire Burst_term = ~csb & rasb & casb & ~web;
wire Mode_reg_enable = ~csb & ~rasb & ~casb & ~web;
wire Prech_enable = ~csb & ~rasb & casb & ~web;
wire Read_enable = ~csb & rasb & ~casb & web;
wire Write_enable = ~csb & rasb & ~casb & ~web;
// Burst Length Decode
wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0];
wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
// CAS Latency Decode
wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4];
wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4];
// Write Burst Mode
wire Write_burst_mode = Mode_reg[9];
reg Debug; // Debug messages : 1 = On
wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ
assign dq = Dq_reg; // DQ buffer
// Commands Operation
`define ACT 0
`define NOP 1
`define READ 2
`define READ_A 3
`define WRITE 4
`define WRITE_A 5
`define PRECH 6
`define A_REF 7
`define BST 8
`define LMR 9
// Timing Parameters for -75 (PC133) and CAS Latency = 2
parameter tAC = 6.0;
parameter tHZ = 7.0;
parameter tOH = 2.7;
parameter tMRD = 2.0; // 2 clk Cycles
parameter tRAS = 44.0;
parameter tRC = 66.0;
parameter tRCD = 20.0;
parameter tRP = 20.0;
parameter tRRD = 15.0;
parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 clk + 7.5 ns)
parameter tWRp = 15.0; // A2 Version - Precharge mode only (15 ns)
// Timing Check variable
integer MRD_chk;
integer WR_counter [0 : 3];
time WR_chk [0 : 3];
time RC_chk, RRD_chk;
time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
initial begin
Debug = 1'b0;
Dq_reg = {data_bits{1'bz}};
{Data_in_enable, Data_out_enable} = 0;
{Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000;
{Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
{WR_chk[0], WR_chk[1], WR_chk[2], WR_chk[3]} = 0;
{WR_counter[0], WR_counter[1], WR_counter[2], WR_counter[3]} = 0;
{RW_interrupt_read[0], RW_interrupt_read[1], RW_interrupt_read[2], RW_interrupt_read[3]} = 0;
{RW_interrupt_write[0], RW_interrupt_write[1], RW_interrupt_write[2], RW_interrupt_write[3]} = 0;
{MRD_chk, RC_chk, RRD_chk} = 0;
{RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0;
{RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0;
{RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0;
$timeformat (-9, 0, " ns", 12);
//$readmemh("bank0.txt", Bank0);
//$readmemh("bank1.txt", Bank1);
//$readmemh("bank2.txt", Bank2);
//$readmemh("bank3.txt", Bank3);
end
// System clock generator
always begin
@ (posedge clk) begin
Sys_clk = CkeZ;
CkeZ = cke;
end
@ (negedge clk) begin
Sys_clk = 1'b0;
end
end
always @ (posedge Sys_clk) begin
// Internal Commamd Pipelined
Command[0] = Command[1];
Command[1] = Command[2];
Command[2] = Command[3];
Command[3] = `NOP;
Col_addr[0] = Col_addr[1];
Col_addr[1] = Col_addr[2];
Col_addr[2] = Col_addr[3];
Col_addr[3] = {col_bits{1'b0}};
Bank_addr[0] = Bank_addr[1];
Bank_addr[1] = Bank_addr[2];
Bank_addr[2] = Bank_addr[3];
Bank_addr[3] = 2'b0;
Bank_precharge[0] = Bank_precharge[1];
Bank_precharge[1] = Bank_precharge[2];
Bank_precharge[2] = Bank_precharge[3];
Bank_precharge[3] = 2'b0;
A10_precharge[0] = A10_precharge[1];
A10_precharge[1] = A10_precharge[2];
A10_precharge[2] = A10_precharge[3];
A10_precharge[3] = 1'b0;
// dqm pipeline for Read
Dqm_reg0 = Dqm_reg1;
Dqm_reg1 = dqm;
// Read or Write with Auto Precharge Counter
if (Auto_precharge[0] == 1'b1) begin
Count_precharge[0] = Count_precharge[0] + 1;
end
if (Auto_precharge[1] == 1'b1) begin
Count_precharge[1] = Count_precharge[1] + 1;
end
if (Auto_precharge[2] == 1'b1) begin
Count_precharge[2] = Count_precharge[2] + 1;
end
if (Auto_precharge[3] == 1'b1) begin
Count_precharge[3] = Count_precharge[3] + 1;
end
// tMRD Counter
MRD_chk = MRD_chk + 1;
// tWR Counter for Write
WR_counter[0] = WR_counter[0] + 1;
WR_counter[1] = WR_counter[1] + 1;
WR_counter[2] = WR_counter[2] + 1;
WR_counter[3] = WR_counter[3] + 1;
// Auto Refresh
if (Aref_enable == 1'b1) begin
if (Debug) $display ("at time %t AREF : Auto Refresh", $time);
// Auto Refresh to Auto Refresh
if ($time - RC_chk < tRC) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: tRC violation during Auto Refresh", $time);
end
// Precharge to Auto Refresh
if ($time - RP_chk0 < tRP || $time - RP_chk1 < tRP || $time - RP_chk2 < tRP || $time - RP_chk3 < tRP) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: tRP violation during Auto Refresh", $time);
end
// Precharge to Refresh
if (Pc_b0 == 1'b0 || Pc_b1 == 1'b0 || Pc_b2 == 1'b0 || Pc_b3 == 1'b0) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: All banks must be Precharge before Auto Refresh", $time);
end
// Record Current tRC time
RC_chk = $time;
end
// Load Mode Register
if (Mode_reg_enable == 1'b1) begin
// Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode
if (Pc_b0 == 1'b1 && Pc_b1 == 1'b1 && Pc_b2 == 1'b1 && Pc_b3 == 1'b1) begin
Mode_reg = addr;
if (Debug) begin
$display ("at time %t LMR : Load Mode Register", $time);
// CAS Latency
if (addr[6 : 4] == 3'b010)
$display (" CAS Latency = 2");
else if (addr[6 : 4] == 3'b011)
$display (" CAS Latency = 3");
else
$display (" CAS Latency = Reserved");
// Burst Length
if (addr[2 : 0] == 3'b000)
$display (" Burst Length = 1");
else if (addr[2 : 0] == 3'b001)
$display (" Burst Length = 2");
else if (addr[2 : 0] == 3'b010)
$display (" Burst Length = 4");
else if (addr[2 : 0] == 3'b011)
$display (" Burst Length = 8");
else if (addr[3 : 0] == 4'b0111)
$display (" Burst Length = Full");
else
$display (" Burst Length = Reserved");
// Burst Type
if (addr[3] == 1'b0)
$display (" Burst Type = Sequential");
else if (addr[3] == 1'b1)
$display (" Burst Type = Interleaved");
else
$display (" Burst Type = Reserved");
// Write Burst Mode
if (addr[9] == 1'b0)
$display (" Write Burst Mode = Programmed Burst Length");
else if (addr[9] == 1'b1)
$display (" Write Burst Mode = Single Location Access");
else
$display (" Write Burst Mode = Reserved");
end
end else begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: all banks must be Precharge before Load Mode Register", $time);
end
// REF to LMR
if ($time - RC_chk < tRC) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: tRC violation during Load Mode Register", $time);
end
// LMR to LMR
if (MRD_chk < tMRD) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: tMRD violation during Load Mode Register", $time);
end
MRD_chk = 0;
end
// Active Block (Latch Bank Address and Row Address)
if (Active_enable == 1'b1) begin
if (ba == 2'b00 && Pc_b0 == 1'b1) begin
{Act_b0, Pc_b0} = 2'b10;
B0_row_addr = addr [addr_bits - 1 : 0];
RCD_chk0 = $time;
RAS_chk0 = $time;
if (Debug) $display ("at time %t ACT : Bank = 0 Row = %d", $time, addr);
// Precharge to Activate Bank 0
if ($time - RP_chk0 < tRP) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: tRP violation during Activate bank 0", $time);
end
end else if (ba == 2'b01 && Pc_b1 == 1'b1) begin
{Act_b1, Pc_b1} = 2'b10;
B1_row_addr = addr [addr_bits - 1 : 0];
RCD_chk1 = $time;
RAS_chk1 = $time;
if (Debug) $display ("at time %t ACT : Bank = 1 Row = %d", $time, addr);
// Precharge to Activate Bank 1
if ($time - RP_chk1 < tRP) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: tRP violation during Activate bank 1", $time);
end
end else if (ba == 2'b10 && Pc_b2 == 1'b1) begin
{Act_b2, Pc_b2} = 2'b10;
B2_row_addr = addr [addr_bits - 1 : 0];
RCD_chk2 = $time;
RAS_chk2 = $time;
if (Debug) $display ("at time %t ACT : Bank = 2 Row = %d", $time, addr);
// Precharge to Activate Bank 2
if ($time - RP_chk2 < tRP) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: tRP violation during Activate bank 2", $time);
end
end else if (ba == 2'b11 && Pc_b3 == 1'b1) begin
{Act_b3, Pc_b3} = 2'b10;
B3_row_addr = addr [addr_bits - 1 : 0];
RCD_chk3 = $time;
RAS_chk3 = $time;
if (Debug) $display ("at time %t ACT : Bank = 3 Row = %d", $time, addr);
// Precharge to Activate Bank 3
if ($time - RP_chk3 < tRP) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: tRP violation during Activate bank 3", $time);
end
end else if (ba == 2'b00 && Pc_b0 == 1'b0) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: Bank 0 is not Precharged.", $time);
end else if (ba == 2'b01 && Pc_b1 == 1'b0) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: Bank 1 is not Precharged.", $time);
end else if (ba == 2'b10 && Pc_b2 == 1'b0) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: Bank 2 is not Precharged.", $time);
end else if (ba == 2'b11 && Pc_b3 == 1'b0) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: Bank 3 is not Precharged.", $time);
end
// Active Bank A to Active Bank B
if ((Previous_bank != ba) && ($time - RRD_chk < tRRD)) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: tRRD violation during Activate bank = %d", $time, ba);
end
// Load Mode Register to Active
if (MRD_chk < tMRD ) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: tMRD violation during Activate bank = %d", $time, ba);
end
// Auto Refresh to Activate
if ($time - RC_chk < tRC) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: tRC violation during Activate bank = %d", $time, ba);
end
// Record variables for checking violation
RRD_chk = $time;
Previous_bank = ba;
end
// Precharge Block
if (Prech_enable == 1'b1) begin
if (addr[10] == 1'b1) begin
{Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b1111;
{Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000;
RP_chk0 = $time;
RP_chk1 = $time;
RP_chk2 = $time;
RP_chk3 = $time;
if (Debug) $display ("at time %t PRE : Bank = ALL",$time);
// Activate to Precharge all banks
if (($time - RAS_chk0 < tRAS) || ($time - RAS_chk1 < tRAS) ||
($time - RAS_chk2 < tRAS) || ($time - RAS_chk3 < tRAS)) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: tRAS violation during Precharge all bank", $time);
end
// tWR violation check for write
if (($time - WR_chk[0] < tWRp) || ($time - WR_chk[1] < tWRp) ||
($time - WR_chk[2] < tWRp) || ($time - WR_chk[3] < tWRp)) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: tWR violation during Precharge all bank", $time);
end
end else if (addr[10] == 1'b0) begin
if (ba == 2'b00) begin
{Pc_b0, Act_b0} = 2'b10;
RP_chk0 = $time;
if (Debug) $display ("at time %t PRE : Bank = 0",$time);
// Activate to Precharge Bank 0
if ($time - RAS_chk0 < tRAS) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: tRAS violation during Precharge bank 0", $time);
end
end else if (ba == 2'b01) begin
{Pc_b1, Act_b1} = 2'b10;
RP_chk1 = $time;
if (Debug) $display ("at time %t PRE : Bank = 1",$time);
// Activate to Precharge Bank 1
if ($time - RAS_chk1 < tRAS) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: tRAS violation during Precharge bank 1", $time);
end
end else if (ba == 2'b10) begin
{Pc_b2, Act_b2} = 2'b10;
RP_chk2 = $time;
if (Debug) $display ("at time %t PRE : Bank = 2",$time);
// Activate to Precharge Bank 2
if ($time - RAS_chk2 < tRAS) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: tRAS violation during Precharge bank 2", $time);
end
end else if (ba == 2'b11) begin
{Pc_b3, Act_b3} = 2'b10;
RP_chk3 = $time;
if (Debug) $display ("at time %t PRE : Bank = 3",$time);
// Activate to Precharge Bank 3
if ($time - RAS_chk3 < tRAS) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: tRAS violation during Precharge bank 3", $time);
end
end
// tWR violation check for write
if ($time - WR_chk[ba] < tWRp) begin
//->tb.test_control.error_detected;
$display ("at time %t ERROR: tWR violation during Precharge bank %d", $time, ba);
end
end
// Terminate a Write Immediately (if same bank or all banks)
if (Data_in_enable == 1'b1 && (Bank == ba || addr[10] == 1'b1)) begin
Data_in_enable = 1'b0;
end
// Precharge Command Pipeline for Read
if (Cas_latency_3 == 1'b1) begin
Command[2] = `PRECH;
Bank_precharge[2] = ba;
A10_precharge[2] = addr[10];
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `PRECH;
Bank_precharge[1] = ba;
A10_precharge[1] = addr[10];
end
end
// Burst terminate
if (Burst_term == 1'b1) begin
// Terminate a Write Immediately
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
end
// Terminate a Read Depend on CAS Latency
if (Cas_latency_3 == 1'b1) begin
Command[2] = `BST;
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `BST;
end
if (Debug) $display ("at time %t BST : Burst Terminate",$time);
end
// Read, Write, Column Latch
if (Read_enable == 1'b1 || Write_enable == 1'b1) begin
// Check to see if bank is open (ACT)
if ((ba == 2'b00 && Pc_b0 == 1'b1) || (ba == 2'b01 && Pc_b1 == 1'b1) ||
(ba == 2'b10 && Pc_b2 == 1'b1) || (ba == 2'b11 && Pc_b3 == 1'b1)) begin
//->tb.test_control.error_detected;
$display("at time %t ERROR: Cannot Read or Write - Bank %d is not Activated", $time, ba);
end
// Activate to Read or Write
if ((ba == 2'b00) && ($time - RCD_chk0 < tRCD))
begin
//->tb.test_control.error_detected;
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 0", $time);
end
if ((ba == 2'b01) && ($time - RCD_chk1 < tRCD))
begin
//->tb.test_control.error_detected;
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 1", $time);
end
if ((ba == 2'b10) && ($time - RCD_chk2 < tRCD))
begin
//->tb.test_control.error_detected;
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 2", $time);
end
if ((ba == 2'b11) && ($time - RCD_chk3 < tRCD))
begin
//->tb.test_control.error_detected;
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 3", $time);
end
// Read Command
if (Read_enable == 1'b1) begin
// CAS Latency pipeline
if (Cas_latency_3 == 1'b1) begin
if (addr[10] == 1'b1) begin
Command[2] = `READ_A;
end else begin
Command[2] = `READ;
end
Col_addr[2] = addr;
Bank_addr[2] = ba;
end else if (Cas_latency_2 == 1'b1) begin
if (addr[10] == 1'b1) begin
Command[1] = `READ_A;
end else begin
Command[1] = `READ;
end
Col_addr[1] = addr;
Bank_addr[1] = ba;
end
// Read interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
end
// Write Command
end else if (Write_enable == 1'b1) begin
if (addr[10] == 1'b1) begin
Command[0] = `WRITE_A;
end else begin
Command[0] = `WRITE;
end
Col_addr[0] = addr;
Bank_addr[0] = ba;
// Write interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
end
// Write interrupt Read (terminate Read immediately)
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
// Interrupting a Write with Autoprecharge
if (Auto_precharge[Bank] == 1'b1 && Write_precharge[Bank] == 1'b1) begin
RW_interrupt_write[Bank] = 1'b1;
if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Write Bank %d with Autoprecharge", $time, ba, Bank);
end
// Interrupting a Read with Autoprecharge
if (Auto_precharge[Bank] == 1'b1 && Read_precharge[Bank] == 1'b1) begin
RW_interrupt_read[Bank] = 1'b1;
if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, ba, Bank);
end
// Read or Write with Auto Precharge
if (addr[10] == 1'b1) begin
Auto_precharge[ba] = 1'b1;
Count_precharge[ba] = 0;
if (Read_enable == 1'b1) begin
Read_precharge[ba] = 1'b1;
end else if (Write_enable == 1'b1) begin
Write_precharge[ba] = 1'b1;
end
end
end
// Read with Auto Precharge Calculation
// The device start internal precharge:
// 1. CAS Latency - 1 cycles before last burst
// and 2. Meet minimum tRAS requirement
// or 3. Interrupt by a Read or Write (with or without AutoPrecharge)
if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin
if ((($time - RAS_chk0 >= tRAS) && // Case 2
((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 1
(Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
(RW_interrupt_read[0] == 1'b1)) begin // Case 3
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
Auto_precharge[0] = 1'b0;
Read_precharge[0] = 1'b0;
RW_interrupt_read[0] = 1'b0;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
end
end
if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin
if ((($time - RAS_chk1 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
(RW_interrupt_read[1] == 1'b1)) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
Auto_precharge[1] = 1'b0;
Read_precharge[1] = 1'b0;
RW_interrupt_read[1] = 1'b0;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
end
end
if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin
if ((($time - RAS_chk2 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
(RW_interrupt_read[2] == 1'b1)) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
Auto_precharge[2] = 1'b0;
Read_precharge[2] = 1'b0;
RW_interrupt_read[2] = 1'b0;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
end
end
if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin
if ((($time - RAS_chk3 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
(RW_interrupt_read[3] == 1'b1)) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
Auto_precharge[3] = 1'b0;
Read_precharge[3] = 1'b0;
RW_interrupt_read[3] = 1'b0;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
end
end
// Internal Precharge or Bst
if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks
if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
end else if (Command[0] == `BST) begin // BST terminate a read to current bank
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
if (Data_out_enable == 1'b0) begin
Dq_reg <= #tOH {data_bits{1'bz}};
end
// Detect Read or Write command
if (Command[0] == `READ || Command[0] == `READ_A) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
if (Bank_addr[0] == 2'b00) begin
Row = B0_row_addr;
end else if (Bank_addr[0] == 2'b01) begin
Row = B1_row_addr;
end else if (Bank_addr[0] == 2'b10) begin
Row = B2_row_addr;
end else if (Bank_addr[0] == 2'b11) begin
Row = B3_row_addr;
end
Burst_counter = 0;
Data_in_enable = 1'b0;
Data_out_enable = 1'b1;
end else if (Command[0] == `WRITE || Command[0] == `WRITE_A) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
if (Bank_addr[0] == 2'b00) begin
Row = B0_row_addr;
end else if (Bank_addr[0] == 2'b01) begin
Row = B1_row_addr;
end else if (Bank_addr[0] == 2'b10) begin
Row = B2_row_addr;
end else if (Bank_addr[0] == 2'b11) begin
Row = B3_row_addr;
end
Burst_counter = 0;
Data_in_enable = 1'b1;
Data_out_enable = 1'b0;
end
// DQ buffer (Driver/Receiver)
if (Data_in_enable == 1'b1) begin // Writing Data to Memory
// Array buffer
if (Bank == 2'b00) Dq_dqm [15 : 0] = Bank0 [{Row, Col}];
if (Bank == 2'b01) Dq_dqm [15 : 0] = Bank1 [{Row, Col}];
if (Bank == 2'b10) Dq_dqm [15 : 0] = Bank2 [{Row, Col}];
if (Bank == 2'b11) Dq_dqm [15 : 0] = Bank3 [{Row, Col}];
// dqm operation
if (dqm[0] == 1'b0) Dq_dqm [ 7 : 0] = dq [ 7 : 0];
if (dqm[1] == 1'b0) Dq_dqm [15 : 8] = dq [15 : 8];
// Write to memory
if (Bank == 2'b00) Bank0 [{Row, Col}] = Dq_dqm [15 : 0];
if (Bank == 2'b01) Bank1 [{Row, Col}] = Dq_dqm [15 : 0];
if (Bank == 2'b10) Bank2 [{Row, Col}] = Dq_dqm [15 : 0];
if (Bank == 2'b11) Bank3 [{Row, Col}] = Dq_dqm [15 : 0];
// Output result
if (dqm == 2'b11) begin
if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
end else begin
if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %h, dqm = %b", $time, Bank, Row, Col, Dq_dqm, dqm);
// Record tWR time and reset counter
WR_chk [Bank] = $time;
WR_counter [Bank] = 0;
end
// Advance burst counter subroutine
#tHZ Burst;
end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory
// Array buffer
if (Bank == 2'b00) Dq_dqm [15 : 0] = Bank0 [{Row, Col}];
if (Bank == 2'b01) Dq_dqm [15 : 0] = Bank1 [{Row, Col}];
if (Bank == 2'b10) Dq_dqm [15 : 0] = Bank2 [{Row, Col}];
if (Bank == 2'b11) Dq_dqm [15 : 0] = Bank3 [{Row, Col}];
// dqm operation
if (Dqm_reg0[0] == 1'b1) Dq_dqm [ 7 : 0] = 8'bz;
if (Dqm_reg0[1] == 1'b1) Dq_dqm [15 : 8] = 8'bz;
// Display result
Dq_reg [15 : 0] = #tAC Dq_dqm [15 : 0];
if (Dqm_reg0 == 2'b11) begin
if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
end else begin
if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = %h, dqm = %b", $time, Bank, Row, Col, Dq_reg, Dqm_reg0);
end
// Advance burst counter subroutine
Burst;
end
end
// Write with Auto Precharge Calculation
// The device start internal precharge:
// 1. tWR Clock after last burst
// and 2. Meet minimum tRAS requirement
// or 3. Interrupt by a Read or Write (with or without AutoPrecharge)
always @ (WR_counter[0]) begin
if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin
if ((($time - RAS_chk0 >= tRAS) && // Case 2
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 1
(Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) ||
(RW_interrupt_write[0] == 1'b1 && WR_counter[0] >= 2)) begin // Case 3 (stop count when interrupt)
Auto_precharge[0] = 1'b0;
Write_precharge[0] = 1'b0;
RW_interrupt_write[0] = 1'b0;
#tWRa; // Wait for tWR
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
end
end
end
always @ (WR_counter[1]) begin
if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin
if ((($time - RAS_chk1 >= tRAS) &&
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) ||
(RW_interrupt_write[1] == 1'b1 && WR_counter[1] >= 2)) begin
Auto_precharge[1] = 1'b0;
Write_precharge[1] = 1'b0;
RW_interrupt_write[1] = 1'b0;
#tWRa; // Wait for tWR
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
end
end
end
always @ (WR_counter[2]) begin
if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin
if ((($time - RAS_chk2 >= tRAS) &&
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) ||
(RW_interrupt_write[2] == 1'b1 && WR_counter[2] >= 2)) begin
Auto_precharge[2] = 1'b0;
Write_precharge[2] = 1'b0;
RW_interrupt_write[2] = 1'b0;
#tWRa; // Wait for tWR
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
end
end
end
always @ (WR_counter[3]) begin
if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin
if ((($time - RAS_chk3 >= tRAS) &&
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) ||
(RW_interrupt_write[3] == 1'b1 && WR_counter[3] >= 2)) begin
Auto_precharge[3] = 1'b0;
Write_precharge[3] = 1'b0;
RW_interrupt_write[3] = 1'b0;
#tWRa; // Wait for tWR
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
end
end
end
task Burst;
begin
// Advance Burst Counter
Burst_counter = Burst_counter + 1;
// Burst Type
if (Mode_reg[3] == 1'b0) begin // Sequential Burst
Col_temp = Col + 1;
end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst
Col_temp[2] = Burst_counter[2] ^ Col_brst[2];
Col_temp[1] = Burst_counter[1] ^ Col_brst[1];
Col_temp[0] = Burst_counter[0] ^ Col_brst[0];
end
// Burst Length
if (Burst_length_2) begin // Burst Length = 2
Col [0] = Col_temp [0];
end else if (Burst_length_4) begin // Burst Length = 4
Col [1 : 0] = Col_temp [1 : 0];
end else if (Burst_length_8) begin // Burst Length = 8
Col [2 : 0] = Col_temp [2 : 0];
end else begin // Burst Length = FULL
Col = Col_temp;
end
// Burst Read Single Write
if (Write_burst_mode == 1'b1) begin
Data_in_enable = 1'b0;
end
// Data Counter
if (Burst_length_1 == 1'b1) begin
if (Burst_counter >= 1) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_2 == 1'b1) begin
if (Burst_counter >= 2) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_4 == 1'b1) begin
if (Burst_counter >= 4) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_8 == 1'b1) begin
if (Burst_counter >= 8) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end
end
endtask
// Timing Parameters for -75 (PC133) and CAS Latency = 2
specify
specparam
tAH = 0.8, // addr, ba Hold Time
tAS = 1.5, // addr, ba Setup Time
tCH = 2.5, // Clock High-Level Width
tCL = 2.5, // Clock Low-Level Width
tCK = 10, // Clock Cycle Time
tDH = 0.8, // Data-in Hold Time
tDS = 1.5, // Data-in Setup Time
tCKH = 0.8, // CKE Hold Time
tCKS = 1.5, // CKE Setup Time
tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time
tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time
$width (posedge clk, tCH);
$width (negedge clk, tCL);
$period (negedge clk, tCK);
$period (posedge clk, tCK);
$setuphold(posedge clk, cke, tCKS, tCKH);
$setuphold(posedge clk, csb, tCMS, tCMH);
$setuphold(posedge clk, casb, tCMS, tCMH);
$setuphold(posedge clk, rasb, tCMS, tCMH);
$setuphold(posedge clk, web, tCMS, tCMH);
$setuphold(posedge clk, addr, tAS, tAH);
$setuphold(posedge clk, ba, tAS, tAH);
$setuphold(posedge clk, dqm, tCMS, tCMH);
$setuphold(posedge Dq_chk, dq, tDS, tDH);
endspecify
endmodule
/testbench/gtksettings.sav
0,0 → 1,36
@28
top_tb.clk
top_tb.rst
@200
-
-DUT
@22
#{top_tb.addr[31:0]} top_tb.addr[31] top_tb.addr[30] top_tb.addr[29] top_tb.addr[28] top_tb.addr[27] top_tb.addr[26] top_tb.addr[25] top_tb.addr[24] top_tb.addr[23] top_tb.addr[22] top_tb.addr[21] top_tb.addr[20] top_tb.addr[19] top_tb.addr[18] top_tb.addr[17] top_tb.addr[16] top_tb.addr[15] top_tb.addr[14] top_tb.addr[13] top_tb.addr[12] top_tb.addr[11] top_tb.addr[10] top_tb.addr[9] top_tb.addr[8] top_tb.addr[7] top_tb.addr[6] top_tb.addr[5] top_tb.addr[4] top_tb.addr[3] top_tb.addr[2] top_tb.addr[1] top_tb.addr[0]
#{top_tb.data_w[31:0]} top_tb.data_w[31] top_tb.data_w[30] top_tb.data_w[29] top_tb.data_w[28] top_tb.data_w[27] top_tb.data_w[26] top_tb.data_w[25] top_tb.data_w[24] top_tb.data_w[23] top_tb.data_w[22] top_tb.data_w[21] top_tb.data_w[20] top_tb.data_w[19] top_tb.data_w[18] top_tb.data_w[17] top_tb.data_w[16] top_tb.data_w[15] top_tb.data_w[14] top_tb.data_w[13] top_tb.data_w[12] top_tb.data_w[11] top_tb.data_w[10] top_tb.data_w[9] top_tb.data_w[8] top_tb.data_w[7] top_tb.data_w[6] top_tb.data_w[5] top_tb.data_w[4] top_tb.data_w[3] top_tb.data_w[2] top_tb.data_w[1] top_tb.data_w[0]
#{top_tb.data_r[31:0]} top_tb.data_r[31] top_tb.data_r[30] top_tb.data_r[29] top_tb.data_r[28] top_tb.data_r[27] top_tb.data_r[26] top_tb.data_r[25] top_tb.data_r[24] top_tb.data_r[23] top_tb.data_r[22] top_tb.data_r[21] top_tb.data_r[20] top_tb.data_r[19] top_tb.data_r[18] top_tb.data_r[17] top_tb.data_r[16] top_tb.data_r[15] top_tb.data_r[14] top_tb.data_r[13] top_tb.data_r[12] top_tb.data_r[11] top_tb.data_r[10] top_tb.data_r[9] top_tb.data_r[8] top_tb.data_r[7] top_tb.data_r[6] top_tb.data_r[5] top_tb.data_r[4] top_tb.data_r[3] top_tb.data_r[2] top_tb.data_r[1] top_tb.data_r[0]
#{top_tb.sel[3:0]} top_tb.sel[3] top_tb.sel[2] top_tb.sel[1] top_tb.sel[0]
@28
top_tb.we
top_tb.stb
top_tb.cyc
top_tb.stall
top_tb.ack
@200
-
@28
top_tb.sdram_clk
top_tb.sdram_cke
@22
#{top_tb.sdram_addr[12:0]} top_tb.sdram_addr[12] top_tb.sdram_addr[11] top_tb.sdram_addr[10] top_tb.sdram_addr[9] top_tb.sdram_addr[8] top_tb.sdram_addr[7] top_tb.sdram_addr[6] top_tb.sdram_addr[5] top_tb.sdram_addr[4] top_tb.sdram_addr[3] top_tb.sdram_addr[2] top_tb.sdram_addr[1] top_tb.sdram_addr[0]
@28
#{top_tb.sdram_ba[1:0]} top_tb.sdram_ba[1] top_tb.sdram_ba[0]
top_tb.sdram_cas
top_tb.sdram_cs
@22
#{top_tb.sdram_data[15:0]} top_tb.sdram_data[15] top_tb.sdram_data[14] top_tb.sdram_data[13] top_tb.sdram_data[12] top_tb.sdram_data[11] top_tb.sdram_data[10] top_tb.sdram_data[9] top_tb.sdram_data[8] top_tb.sdram_data[7] top_tb.sdram_data[6] top_tb.sdram_data[5] top_tb.sdram_data[4] top_tb.sdram_data[3] top_tb.sdram_data[2] top_tb.sdram_data[1] top_tb.sdram_data[0]
@28
#{top_tb.sdram_dqm[1:0]} top_tb.sdram_dqm[1] top_tb.sdram_dqm[0]
top_tb.sdram_ras
top_tb.sdram_we
[pattern_trace] 1
[pattern_trace] 0
/testbench/top_tb.sv
0,0 → 1,160
`timescale 100ps/100ps
 
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module top_tb ;
 
//-----------------------------------------------------------------
// Simulation
//-----------------------------------------------------------------
`include "simulation.svh"
 
`CLOCK_GEN(clk, 200)
`RESET_GEN(rst, 200)
 
`ifdef TRACE
`TB_VCD(top_tb, "waveform.vcd")
`endif
 
`TB_RUN_FOR(10ms)
 
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire [31:0] addr;
wire [31:0] data_w;
wire [31:0] data_r;
wire [3:0] sel;
wire [2:0] cti;
wire stb;
wire cyc;
wire we;
wire stall;
wire ack;
 
// SDRAM Interface
wire sdram_clk;
wire sdram_cke;
wire sdram_cs;
wire sdram_ras;
wire sdram_cas;
wire sdram_we;
wire [1:0] sdram_dqm;
wire [12:0] sdram_addr;
wire [1:0] sdram_ba;
wire [15:0] sdram_data;
 
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
 
// Wishbone master
wb_master
#(
.MIN_ADDRESS(0),
.MAX_ADDRESS(`MAX_ADDRESS),
.BURST_ENABLED(1),
.READ_ONLY(0)
)
u_master
(
.clk_i(clk),
.rst_i(rst),
 
// Wishbone I/F
.addr_o(addr),
.data_o(data_w),
.data_i(data_r),
.stb_o(stb),
.sel_o(sel),
.cyc_o(cyc),
.cti_o(cti),
.we_o(we),
.stall_i(stall),
.ack_i(ack)
);
 
// SDRAM Controller
sdram
#(
.SDRAM_START_DELAY(1000),
.SDRAM_TARGET("SIMULATION")
)
u_dut
(
.clk_i(clk),
.rst_i(rst),
 
// Wishbone I/F
.addr_i(addr),
.data_i(data_w),
.data_o(data_r),
.stb_i(stb),
.sel_i(sel),
.cyc_i(cyc),
.we_i(we),
.stall_o(stall),
.ack_o(ack),
 
// SDRAM Interface
.sdram_clk_o(sdram_clk),
.sdram_cke_o(sdram_cke),
.sdram_cs_o(sdram_cs),
.sdram_ras_o(sdram_ras),
.sdram_cas_o(sdram_cas),
.sdram_we_o(sdram_we),
.sdram_dqm_o(sdram_dqm),
.sdram_addr_o(sdram_addr),
.sdram_ba_o(sdram_ba),
.sdram_data_io(sdram_data)
);
 
// SDRAM
`PART
u_ram
(
.dq(sdram_data),
.addr(sdram_addr),
.ba(sdram_ba),
.clk(sdram_clk),
.cke(sdram_cke),
.csb(sdram_cs),
.rasb(sdram_ras),
.casb(sdram_cas),
.web(sdram_we),
.dqm(sdram_dqm)
);
 
//-------------------------------------------------------------------
// Debug
//-------------------------------------------------------------------
integer perf_cycles;
integer perf_resps;
 
initial
begin
perf_cycles = 0;
perf_resps = 0;
end
 
always @ (posedge clk)
begin
perf_cycles = perf_cycles + 1;
if (ack)
perf_resps = perf_resps + 1;
 
if (perf_cycles == 50000)
begin
$display("Transfer Rate = %dMB/s\n", ((perf_resps * 4) * 1000) / 1048576);
perf_resps = 0;
perf_cycles = 0;
end
end
 
//-----------------------------------------------------------------
// Test bench timeout
//-----------------------------------------------------------------
`TB_TIMEOUT(clk, rst, stb && !stall, 100000)
 
endmodule
/rtl/sdram.v
0,0 → 1,741
//-----------------------------------------------------------------
// Simple SDRAM Controller
// V0.1
// Ultra-Embedded.com
// Copyright 2015
//
// Email: admin@ultra-embedded.com
//
// License: GPL
// If you would like a version with a more permissive license for
// use in closed source commercial applications please contact me
// for details.
//-----------------------------------------------------------------
//
// This file is open source HDL; you can redistribute it and/or
// modify it under the terms of the GNU General Public License as
// published by the Free Software Foundation; either version 2 of
// the License, or (at your option) any later version.
//
// This file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this file; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
// USA
//-----------------------------------------------------------------
module sdram
 
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter SDRAM_MHZ = 50,
parameter SDRAM_ADDR_W = 24,
parameter SDRAM_COL_W = 9,
parameter SDRAM_BANK_W = 2,
parameter SDRAM_DQM_W = 2,
parameter SDRAM_BANKS = 2 ** SDRAM_BANK_W,
parameter SDRAM_ROW_W = SDRAM_ADDR_W - SDRAM_COL_W - SDRAM_BANK_W,
parameter SDRAM_REFRESH_CNT = 2 ** SDRAM_ROW_W,
parameter SDRAM_START_DELAY = 100000 / (1000 / SDRAM_MHZ), // 100uS
parameter SDRAM_REFRESH_CYCLES = (64000*SDRAM_MHZ) / SDRAM_REFRESH_CNT-1,
parameter SDRAM_READ_LATENCY = 2,
parameter SDRAM_TARGET = "XILINX"
)
 
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input clk_i,
input rst_i,
 
// Wishbone Interface
input stb_i,
input we_i,
input [3:0] sel_i,
input cyc_i,
input [31:0] addr_i,
input [31:0] data_i,
output [31:0] data_o,
output stall_o,
output ack_o,
// SDRAM Interface
output sdram_clk_o,
output sdram_cke_o,
output sdram_cs_o,
output sdram_ras_o,
output sdram_cas_o,
output sdram_we_o,
output [1:0] sdram_dqm_o,
output [12:0] sdram_addr_o,
output [1:0] sdram_ba_o,
inout [15:0] sdram_data_io
);
 
//-----------------------------------------------------------------
// Defines / Local params
//-----------------------------------------------------------------
localparam CMD_W = 4;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE = 4'b0000;
 
// Mode: Burst Length = 4 bytes, CAS=2
localparam MODE_REG = {3'b000,1'b0,2'b00,3'b010,1'b0,3'b001};
 
// SM states
localparam STATE_W = 4;
localparam STATE_INIT = 4'd0;
localparam STATE_DELAY = 4'd1;
localparam STATE_IDLE = 4'd2;
localparam STATE_ACTIVATE = 4'd3;
localparam STATE_READ = 4'd4;
localparam STATE_READ_WAIT = 4'd5;
localparam STATE_WRITE0 = 4'd6;
localparam STATE_WRITE1 = 4'd7;
localparam STATE_PRECHARGE = 4'd8;
localparam STATE_REFRESH = 4'd9;
 
localparam AUTO_PRECHARGE = 10;
localparam ALL_BANKS = 10;
 
localparam SDRAM_DATA_W = 16;
 
localparam CYCLE_TIME_NS = 1000 / SDRAM_MHZ;
 
// SDRAM timing
localparam SDRAM_TRCD_CYCLES = (20 + (CYCLE_TIME_NS-1)) / CYCLE_TIME_NS;
localparam SDRAM_TRP_CYCLES = (20 + (CYCLE_TIME_NS-1)) / CYCLE_TIME_NS;
localparam SDRAM_TRFC_CYCLES = (60 + (CYCLE_TIME_NS-1)) / CYCLE_TIME_NS;
 
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
 
// Xilinx placement pragmas:
//synthesis attribute IOB of command_q is "TRUE"
//synthesis attribute IOB of addr_q is "TRUE"
//synthesis attribute IOB of dqm_q is "TRUE"
//synthesis attribute IOB of cke_q is "TRUE"
//synthesis attribute IOB of bank_q is "TRUE"
//synthesis attribute IOB of data_q is "TRUE"
 
reg [CMD_W-1:0] command_q;
reg [SDRAM_ROW_W-1:0] addr_q;
reg [SDRAM_DATA_W-1:0] data_q;
reg data_rd_en_q;
reg [SDRAM_DQM_W-1:0] dqm_q;
reg cke_q;
reg [SDRAM_BANK_W-1:0] bank_q;
 
// Buffer half word during read and write commands
reg [SDRAM_DATA_W-1:0] data_buffer_q;
reg [SDRAM_DQM_W-1:0] dqm_buffer_q;
 
wire [SDRAM_DATA_W-1:0] sdram_data_in_w;
 
reg refresh_q;
 
reg [SDRAM_BANKS-1:0] row_open_q;
reg [SDRAM_ROW_W-1:0] active_row_q[0:SDRAM_BANKS-1];
 
reg [STATE_W-1:0] state_q;
reg [STATE_W-1:0] next_state_r;
reg [STATE_W-1:0] target_state_r;
reg [STATE_W-1:0] target_state_q;
reg [STATE_W-1:0] delay_state_q;
 
// Address bits
wire [SDRAM_ROW_W-1:0] addr_col_w = {{(SDRAM_ROW_W-SDRAM_COL_W){1'b0}}, addr_i[SDRAM_COL_W:2], 1'b0};
wire [SDRAM_ROW_W-1:0] addr_row_w = addr_i[SDRAM_ADDR_W:SDRAM_COL_W+2+1];
wire [SDRAM_BANK_W-1:0] addr_bank_w = addr_i[SDRAM_COL_W+2:SDRAM_COL_W+2-1];
 
//-----------------------------------------------------------------
// SDRAM State Machine
//-----------------------------------------------------------------
always @ *
begin
next_state_r = state_q;
target_state_r = target_state_q;
 
case (state_q)
//-----------------------------------------
// STATE_INIT
//-----------------------------------------
STATE_INIT :
begin
if (refresh_q)
next_state_r = STATE_IDLE;
end
//-----------------------------------------
// STATE_IDLE
//-----------------------------------------
STATE_IDLE :
begin
// Pending refresh
// Note: tRAS (open row time) cannot be exceeded due to periodic
// auto refreshes.
if (refresh_q)
begin
// Close open rows, then refresh
if (|row_open_q)
next_state_r = STATE_PRECHARGE;
else
next_state_r = STATE_REFRESH;
 
target_state_r = STATE_REFRESH;
end
// Access request
else if (stb_i && cyc_i)
begin
// Open row hit
if (row_open_q[addr_bank_w] && addr_row_w == active_row_q[addr_bank_w])
begin
if (we_i)
next_state_r = STATE_WRITE0;
else
next_state_r = STATE_READ;
end
// Row miss, close row, open new row
else if (row_open_q[addr_bank_w])
begin
next_state_r = STATE_PRECHARGE;
 
if (we_i)
target_state_r = STATE_WRITE0;
else
target_state_r = STATE_READ;
end
// No open row, open row
else
begin
next_state_r = STATE_ACTIVATE;
 
if (we_i)
target_state_r = STATE_WRITE0;
else
target_state_r = STATE_READ;
end
end
end
//-----------------------------------------
// STATE_ACTIVATE
//-----------------------------------------
STATE_ACTIVATE :
begin
// Proceed to read or write state
next_state_r = target_state_r;
end
//-----------------------------------------
// STATE_READ
//-----------------------------------------
STATE_READ :
begin
next_state_r = STATE_READ_WAIT;
end
//-----------------------------------------
// STATE_READ_WAIT
//-----------------------------------------
STATE_READ_WAIT :
begin
next_state_r = STATE_IDLE;
 
// Another pending read request (with no refresh pending)
if (!refresh_q && stb_i && cyc_i && !we_i)
begin
// Open row hit
if (row_open_q[addr_bank_w] && addr_row_w == active_row_q[addr_bank_w])
next_state_r = STATE_READ;
end
end
//-----------------------------------------
// STATE_WRITE0
//-----------------------------------------
STATE_WRITE0 :
begin
next_state_r = STATE_WRITE1;
end
//-----------------------------------------
// STATE_WRITE1
//-----------------------------------------
STATE_WRITE1 :
begin
next_state_r = STATE_IDLE;
 
// Another pending write request (with no refresh pending)
if (!refresh_q && stb_i && cyc_i && we_i)
begin
// Open row hit
if (row_open_q[addr_bank_w] && addr_row_w == active_row_q[addr_bank_w])
next_state_r = STATE_WRITE0;
end
end
//-----------------------------------------
// STATE_PRECHARGE
//-----------------------------------------
STATE_PRECHARGE :
begin
// Closing row to perform refresh
if (target_state_r == STATE_REFRESH)
next_state_r = STATE_REFRESH;
// Must be closing row to open another
else
next_state_r = STATE_ACTIVATE;
end
//-----------------------------------------
// STATE_REFRESH
//-----------------------------------------
STATE_REFRESH :
begin
next_state_r = STATE_IDLE;
end
//-----------------------------------------
// STATE_DELAY
//-----------------------------------------
STATE_DELAY :
begin
next_state_r = delay_state_q;
end
default:
;
endcase
end
 
//-----------------------------------------------------------------
// Delays
//-----------------------------------------------------------------
localparam DELAY_W = 4;
 
reg [DELAY_W-1:0] delay_q;
reg [DELAY_W-1:0] delay_r;
 
/* verilator lint_off WIDTH */
 
always @ *
begin
case (state_q)
//-----------------------------------------
// STATE_ACTIVATE
//-----------------------------------------
STATE_ACTIVATE :
begin
// tRCD (ACTIVATE -> READ / WRITE)
delay_r = SDRAM_TRCD_CYCLES;
end
//-----------------------------------------
// STATE_READ_WAIT
//-----------------------------------------
STATE_READ_WAIT :
begin
delay_r = SDRAM_READ_LATENCY;
 
// Another pending read request (with no refresh pending)
if (!refresh_q && stb_i && cyc_i && !we_i)
begin
// Open row hit
if (row_open_q[addr_bank_w] && addr_row_w == active_row_q[addr_bank_w])
delay_r = 4'd0;
end
end
//-----------------------------------------
// STATE_PRECHARGE
//-----------------------------------------
STATE_PRECHARGE :
begin
// tRP (PRECHARGE -> ACTIVATE)
delay_r = SDRAM_TRP_CYCLES;
end
//-----------------------------------------
// STATE_REFRESH
//-----------------------------------------
STATE_REFRESH :
begin
// tRFC
delay_r = SDRAM_TRFC_CYCLES;
end
//-----------------------------------------
// STATE_DELAY
//-----------------------------------------
STATE_DELAY:
begin
delay_r = delay_q - 4'd1;
end
//-----------------------------------------
// Others
//-----------------------------------------
default:
begin
delay_r = {DELAY_W{1'b0}};
end
endcase
end
/* verilator lint_on WIDTH */
 
// Record target state
always @ (posedge rst_i or posedge clk_i)
if (rst_i)
target_state_q <= STATE_IDLE;
else
target_state_q <= target_state_r;
 
// Record delayed state
always @ (posedge rst_i or posedge clk_i)
if (rst_i)
delay_state_q <= STATE_IDLE;
// On entering into delay state, record intended next state
else if (state_q != STATE_DELAY && delay_r != {DELAY_W{1'b0}})
delay_state_q <= next_state_r;
 
// Update actual state
always @ (posedge rst_i or posedge clk_i)
if (rst_i)
state_q <= STATE_INIT;
// Delaying...
else if (delay_r != {DELAY_W{1'b0}})
state_q <= STATE_DELAY;
else
state_q <= next_state_r;
 
// Update delay flops
always @ (posedge rst_i or posedge clk_i)
if (rst_i)
delay_q <= {DELAY_W{1'b0}};
else
delay_q <= delay_r;
 
//-----------------------------------------------------------------
// Refresh counter
//-----------------------------------------------------------------
localparam REFRESH_CNT_W = 17;
 
reg [REFRESH_CNT_W-1:0] refresh_timer_q;
always @ (posedge rst_i or posedge clk_i)
if (rst_i)
refresh_timer_q <= SDRAM_START_DELAY + 100;
else if (refresh_timer_q == {REFRESH_CNT_W{1'b0}})
refresh_timer_q <= SDRAM_REFRESH_CYCLES;
else
refresh_timer_q <= refresh_timer_q - 1;
 
always @ (posedge rst_i or posedge clk_i)
if (rst_i)
refresh_q <= 1'b0;
else if (refresh_timer_q == {REFRESH_CNT_W{1'b0}})
refresh_q <= 1'b1;
else if (state_q == STATE_REFRESH)
refresh_q <= 1'b0;
 
//-----------------------------------------------------------------
// Input sampling
//-----------------------------------------------------------------
 
reg [SDRAM_DATA_W-1:0] sample_data0_q;
always @ (posedge rst_i or posedge clk_i)
if (rst_i)
sample_data0_q <= {SDRAM_DATA_W{1'b0}};
else
sample_data0_q <= sdram_data_in_w;
 
reg [SDRAM_DATA_W-1:0] sample_data_q;
always @ (posedge rst_i or posedge clk_i)
if (rst_i)
sample_data_q <= {SDRAM_DATA_W{1'b0}};
else
sample_data_q <= sample_data0_q;
 
//-----------------------------------------------------------------
// Command Output
//-----------------------------------------------------------------
integer idx;
 
always @ (posedge rst_i or posedge clk_i)
if (rst_i)
begin
command_q <= CMD_NOP;
data_q <= 16'b0;
addr_q <= {SDRAM_ROW_W{1'b0}};
bank_q <= {SDRAM_BANK_W{1'b0}};
cke_q <= 1'b0;
dqm_q <= {SDRAM_DQM_W{1'b0}};
data_rd_en_q <= 1'b1;
dqm_buffer_q <= {SDRAM_DQM_W{1'b0}};
 
for (idx=0;idx<SDRAM_BANKS;idx=idx+1)
active_row_q[idx] <= {SDRAM_ROW_W{1'b0}};
 
row_open_q <= {SDRAM_BANKS{1'b0}};
end
else
begin
case (state_q)
//-----------------------------------------
// STATE_IDLE / Default (delays)
//-----------------------------------------
default:
begin
// Default
command_q <= CMD_NOP;
addr_q <= {SDRAM_ROW_W{1'b0}};
bank_q <= {SDRAM_BANK_W{1'b0}};
data_rd_en_q <= 1'b1;
end
//-----------------------------------------
// STATE_INIT
//-----------------------------------------
STATE_INIT:
begin
// Assert CKE
if (refresh_timer_q == 50)
begin
// Assert CKE after 100uS
cke_q <= 1'b1;
end
// PRECHARGE
else if (refresh_timer_q == 40)
begin
// Precharge all banks
command_q <= CMD_PRECHARGE;
addr_q[ALL_BANKS] <= 1'b1;
end
// 2 x REFRESH (with at least tREF wait)
else if (refresh_timer_q == 20 || refresh_timer_q == 30)
begin
command_q <= CMD_REFRESH;
end
// Load mode register
else if (refresh_timer_q == 10)
begin
command_q <= CMD_LOAD_MODE;
addr_q <= MODE_REG;
end
// Other cycles during init - just NOP
else
begin
command_q <= CMD_NOP;
addr_q <= {SDRAM_ROW_W{1'b0}};
bank_q <= {SDRAM_BANK_W{1'b0}};
end
end
//-----------------------------------------
// STATE_ACTIVATE
//-----------------------------------------
STATE_ACTIVATE :
begin
// Select a row and activate it
command_q <= CMD_ACTIVE;
addr_q <= addr_row_w;
bank_q <= addr_bank_w;
 
active_row_q[addr_bank_w] <= addr_row_w;
row_open_q[addr_bank_w] <= 1'b1;
end
//-----------------------------------------
// STATE_PRECHARGE
//-----------------------------------------
STATE_PRECHARGE :
begin
// Precharge due to refresh, close all banks
if (target_state_r == STATE_REFRESH)
begin
// Precharge all banks
command_q <= CMD_PRECHARGE;
addr_q[ALL_BANKS] <= 1'b1;
row_open_q <= {SDRAM_BANKS{1'b0}};
end
else
begin
// Precharge specific banks
command_q <= CMD_PRECHARGE;
addr_q[ALL_BANKS] <= 1'b0;
bank_q <= addr_bank_w;
 
row_open_q[addr_bank_w] <= 1'b0;
end
end
//-----------------------------------------
// STATE_REFRESH
//-----------------------------------------
STATE_REFRESH :
begin
// Auto refresh
command_q <= CMD_REFRESH;
addr_q <= {SDRAM_ROW_W{1'b0}};
bank_q <= {SDRAM_BANK_W{1'b0}};
end
//-----------------------------------------
// STATE_READ
//-----------------------------------------
STATE_READ :
begin
command_q <= CMD_READ;
addr_q <= addr_col_w;
bank_q <= addr_bank_w;
 
// Disable auto precharge (auto close of row)
addr_q[AUTO_PRECHARGE] <= 1'b0;
 
// Read mask (all bytes in burst)
dqm_q <= {SDRAM_DQM_W{1'b0}};
end
//-----------------------------------------
// STATE_WRITE0
//-----------------------------------------
STATE_WRITE0 :
begin
command_q <= CMD_WRITE;
addr_q <= addr_col_w;
bank_q <= addr_bank_w;
data_q <= data_i[15:0];
 
// Disable auto precharge (auto close of row)
addr_q[AUTO_PRECHARGE] <= 1'b0;
 
// Write mask
dqm_q <= ~sel_i[1:0];
dqm_buffer_q <= ~sel_i[3:2];
 
data_rd_en_q <= 1'b0;
end
//-----------------------------------------
// STATE_WRITE1
//-----------------------------------------
STATE_WRITE1 :
begin
// Burst continuation
command_q <= CMD_NOP;
 
data_q <= data_buffer_q;
 
// Disable auto precharge (auto close of row)
addr_q[AUTO_PRECHARGE] <= 1'b0;
 
// Write mask
dqm_q <= dqm_buffer_q;
end
endcase
end
 
//-----------------------------------------------------------------
// Record read events
//-----------------------------------------------------------------
reg [SDRAM_READ_LATENCY+1:0] rd_q;
 
always @ (posedge rst_i or posedge clk_i)
if (rst_i)
rd_q <= {(SDRAM_READ_LATENCY+2){1'b0}};
else
rd_q <= {rd_q[SDRAM_READ_LATENCY:0], (state_q == STATE_READ)};
 
//-----------------------------------------------------------------
// Data Buffer
//-----------------------------------------------------------------
 
// Buffer upper 16-bits of write data so write command can be accepted
// in WRITE0. Also buffer lower 16-bits of read data.
always @ (posedge rst_i or posedge clk_i)
if (rst_i)
data_buffer_q <= 16'b0;
else if (state_q == STATE_WRITE0)
data_buffer_q <= data_i[31:16];
else if (rd_q[SDRAM_READ_LATENCY+1])
data_buffer_q <= sample_data_q;
 
// Read data output
assign data_o = {sample_data_q, data_buffer_q};
 
//-----------------------------------------------------------------
// Wishbone ACK
//-----------------------------------------------------------------
reg ack_q;
 
always @ (posedge rst_i or posedge clk_i)
if (rst_i)
ack_q <= 1'b0;
else
begin
if (state_q == STATE_WRITE1)
ack_q <= 1'b1;
else if (rd_q[SDRAM_READ_LATENCY+1])
ack_q <= 1'b1;
else
ack_q <= 1'b0;
end
 
assign ack_o = ack_q;
 
// Accept wishbone command in READ or WRITE0 states
assign stall_o = ~(state_q == STATE_READ || state_q == STATE_WRITE0);
 
//-----------------------------------------------------------------
// SDRAM I/O
//-----------------------------------------------------------------
genvar i;
 
generate
if (SDRAM_TARGET == "XILINX")
begin
// 180 degree phase delayed sdram clock output
ODDR2
#(
.DDR_ALIGNMENT("NONE"),
.INIT(1'b0),
.SRTYPE("SYNC")
)
u_clock_delay
(
.Q(sdram_clk_o),
.C0(clk_i),
.C1(~clk_i),
.CE(1'b1),
.R(1'b0),
.S(1'b0),
.D0(1'b0),
.D1(1'b1)
);
 
for (i=0; i < 16; i = i + 1)
begin
IOBUF
#(
.DRIVE(12),
.IOSTANDARD("LVTTL"),
.SLEW("FAST")
)
u_data_buf
(
.O(sdram_data_in_w[i]),
.IO(sdram_data_io[i]),
.I(data_q[i]),
.T(data_rd_en_q)
);
end
end
else
begin
assign sdram_clk_o = ~clk_i;
assign sdram_data_io = data_rd_en_q ? 16'bz : data_q;
assign sdram_data_in_w = sdram_data_io;
end
endgenerate
 
assign sdram_cke_o = cke_q;
assign sdram_cs_o = command_q[3];
assign sdram_ras_o = command_q[2];
assign sdram_cas_o = command_q[1];
assign sdram_we_o = command_q[0];
assign sdram_dqm_o = dqm_q;
assign sdram_ba_o = bank_q;
assign sdram_addr_o = addr_q;
 
endmodule

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