OpenCores
URL https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk

Subversion Repositories spacewire_light

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Rev 2 → Rev 3

/spacewire_light/trunk/bench/vhdl/streamtest_tb.vhd
28,6 → 28,7
component streamtest is
generic (
sysfreq: real;
txclkfreq: real;
tickdiv: integer range 12 to 24 := 20;
rximpl: spw_implementation_type := impl_generic;
rxchunk: integer range 1 to 4 := 1;
84,6 → 85,7
streamtest_inst: streamtest
generic map (
sysfreq => sys_clock_freq,
txclkfreq => sys_clock_freq,
tickdiv => 16,
rximpl => impl_generic,
rxchunk => 1,
/spacewire_light/trunk/rtl/vhdl/spwstream.vhd
11,7 → 11,7
--
-- The SpaceWire standard requires that each transceiver use an initial
-- signalling rate of 10 Mbit/s. This implies that the system clock frequency
-- must be a multiple of 10 MHz. See the datasheet for further details on
-- must be a multiple of 10 MHz. See the manual for further details on
-- bitrates and clocking.
--
 
26,9 → 26,14
-- System clock frequency in Hz.
-- This must be set to the frequency of "clk". It is used to setup
-- counters for reset timing, disconnect timeout and to transmit
-- at 10 Mbit/s during the handshake.
-- at 10 Mbit/s during the link handshake.
sysfreq: real;
 
-- Transmit clock frequency in Hz (only if tximpl = impl_fast).
-- This must be set to the frequency of "txclk". It is used to
-- transmit at 10 Mbit/s during the link handshake.
txclkfreq: real := 0.0;
 
-- Selection of a receiver front-end implementation.
rximpl: spw_implementation_type := impl_generic;
 
67,12 → 72,13
-- Without autostart or linkstart, the link remains in state Ready.
linkstart: in std_logic;
 
-- Do not start link (overrides linkstart and autostart) and/or disconnect
-- if the link is in state Run.
-- Do not start link (overrides linkstart and autostart) and/or
-- disconnect a running link.
linkdis: in std_logic;
 
-- Scaling factor minus 1, used to scale the system clock into the transmission
-- signalling rate. The system clock is divided by (unsigned(divcnt) + 1).
-- Scaling factor minus 1, used to scale the transmit base clock into
-- the transmission bit rate. The system clock (for impl_generic) or
-- the txclk (for impl_fast) is divided by (unsigned(txdivcnt) + 1).
-- Changing this signal will immediately change the transmission rate.
-- During link setup, the transmission rate is always 10 Mbit/s.
txdivcnt: in std_logic_vector(7 downto 0);
193,8 → 199,12
constant disconnect_time: integer := integer(sysfreq * 850.0e-9);
 
-- Initial tx clock scaler (10 Mbit).
type impl_to_real_type is array(spw_implementation_type) of real;
constant tximpl_to_txclk_freq: impl_to_real_type :=
(impl_generic => sysfreq, impl_fast => txclkfreq);
constant effective_txclk_freq: real := tximpl_to_txclk_freq(tximpl);
constant default_divcnt: std_logic_vector(7 downto 0) :=
std_logic_vector(to_unsigned(integer(sysfreq / 10.0e6 - 1.0), 8));
std_logic_vector(to_unsigned(integer(effective_txclk_freq / 10.0e6 - 1.0), 8));
 
-- Registers.
type regs_type is record
/spacewire_light/trunk/rtl/vhdl/spwxmit_fast.vhd
122,7 → 122,7
-- no problem there.
--
-- This is different when the data stream includes 4-bit tokens.
-- See the datasheet for an analysis of that case.
-- See the manual for further comments.
--
-- Implementation guidelines
-- -------------------------
200,6 → 200,7
type token_type is record
tick: std_ulogic; -- send time code
fct: std_ulogic; -- send FCT
fctpiggy: std_ulogic; -- send FCT and N-char
flag: std_ulogic; -- send EOP or EEP
char: std_logic_vector(7 downto 0); -- character or time code
end record;
220,6 → 221,7
b_token: token_type;
-- stage C
c_update: std_ulogic;
c_busy: std_ulogic;
c_esc: std_ulogic;
c_fct: std_ulogic;
c_bits: std_logic_vector(8 downto 0);
277,6 → 279,12
end record;
 
-- Initial state of system clock domain
constant token_reset: token_type := (
tick => '0',
fct => '0',
fctpiggy => '0',
flag => '0',
char => (others => '0') );
constant regs_reset: regs_type := (
txenreg => '0',
txdivreg => (others => '0'),
285,8 → 293,8
txdivsafe => '0',
sysflip0 => '0',
sysflip1 => '0',
token0 => ( tick => '0', fct => '0', flag => '0', char => (others => '0') ),
token1 => ( tick => '0', fct => '0', flag => '0', char => (others => '0') ),
token0 => token_reset,
token1 => token_reset,
tokmux => '0',
txflip0 => "00",
txflip1 => "00",
336,7 → 344,7
vtx := rtx;
v_needtoken := '0';
v_havetoken := '0';
v_token := ( tick => '0', fct => '0', flag => '0', char => (others => '0') );
v_token := token_reset;
 
-- ---- FAST CLOCK DOMAIN ----
 
349,9 → 357,9
-- Stage B: Multiplex tokens from system clock domain.
-- Update stage B three bit periods after updating stage C
-- (i.e. in time for the next update of stage C).
-- Do not update stage B if the last token from stage C was ESC;
-- stage C already knows what token to put after the ESC.
vtx.b_update := rtx.txclken and rtx.e_count(0) and (not rtx.c_esc);
-- Do not update stage B if stage C is indicating that it needs to
-- send a second token to complete its task.
vtx.b_update := rtx.txclken and rtx.e_count(0) and (not rtx.c_busy);
if rtx.b_mux = '0' then
vtx.b_txflip := rtx.txflip0;
else
380,11 → 388,26
-- Stage C: Prepare to transmit EOP, EEP or a data character.
vtx.c_update := rtx.txclken and rtx.e_count(3);
if rtx.c_update = '1' then
-- NULL is broken into two tokens: ESC + FCT
-- time codes are broken into two tokens: ESC + char
 
-- NULL is broken into two tokens: ESC + FCT.
-- Time-codes are broken into two tokens: ESC + char.
 
-- Enable c_esc on the first pass of a NULL or a time-code.
vtx.c_esc := (rtx.b_token.tick or (not rtx.b_valid)) and
(not rtx.c_esc);
vtx.c_fct := rtx.b_token.fct or (not rtx.b_valid);
 
-- Enable c_fct on the first pass of an FCT and on
-- the second pass of a NULL (also the first pass, but c_esc
-- is stronger than c_fct).
vtx.c_fct := (rtx.b_token.fct and (not rtx.c_busy)) or
(not rtx.b_valid);
 
-- Enable c_busy on the first pass of a NULL or a time-code
-- or a piggy-backed FCT. This will tell stage B that we are
-- not done yet.
vtx.c_busy := (rtx.b_token.tick or (not rtx.b_valid) or
rtx.b_token.fctpiggy) and (not rtx.c_busy);
 
if rtx.b_token.flag = '1' then
if rtx.b_token.char(0) = '0' then
-- prepare to send EOP
493,6 → 516,7
vtx.b_mux := '0';
vtx.b_valid := '0';
vtx.c_update := '0';
vtx.c_busy := '1';
vtx.c_esc := '1'; -- need to send 2nd part of NULL
vtx.c_fct := '1';
vtx.d_bits := "000000111"; -- ESC = P111
584,6 → 608,7
-- prepare to send time code
v_token.tick := '1';
v_token.fct := '0';
v_token.fctpiggy := '0';
v_token.flag := '0';
v_token.char := r.pend_time;
v_havetoken := '1';
590,25 → 615,27
if v_needtoken = '1' then
v.pend_tick := '0';
end if;
elsif r.allow_fct = '1' and (xmiti.fct_in = '1' or r.pend_fct = '1') then
-- prepare to send FCT
v_token.tick := '0';
v_token.fct := '1';
v_token.flag := '0';
v_havetoken := '1';
if v_needtoken = '1' then
v.pend_fct := '0';
v.sent_fct := '1';
else
if r.allow_fct = '1' and (xmiti.fct_in = '1' or r.pend_fct = '1') then
-- prepare to send FCT
v_token.fct := '1';
v_havetoken := '1';
if v_needtoken = '1' then
v.pend_fct := '0';
v.sent_fct := '1';
end if;
end if;
elsif r.allow_char = '1' and r.pend_char = '1' then
-- prepare to send N-Char
v_token.tick := '0';
v_token.fct := '0';
v_token.flag := r.pend_data(8);
v_token.char := r.pend_data(7 downto 0);
v_havetoken := '1';
if v_needtoken = '1' then
v.pend_char := '0';
if r.allow_char = '1' and r.pend_char = '1' then
-- prepare to send N-Char
-- Note: it is possible to send an FCT and an N-Char
-- together by enabling the fctpiggy flag.
v_token.fctpiggy := v_token.fct;
v_token.flag := r.pend_data(8);
v_token.char := r.pend_data(7 downto 0);
v_havetoken := '1';
if v_needtoken = '1' then
v.pend_char := '0';
end if;
end if;
end if;
 
/spacewire_light/trunk/rtl/vhdl/spwpkg.vhd
232,6 → 232,7
component spwstream is
generic (
sysfreq: real; -- clk freq in Hz
txclkfreq: real := 0.0; -- txclk freq in Hz
rximpl: spw_implementation_type := impl_generic;
rxchunk: integer range 1 to 4 := 1; -- max bits per clk
tximpl: spw_implementation_type := impl_generic;
/spacewire_light/trunk/rtl/vhdl/streamtest.vhd
31,6 → 31,9
-- System clock frequency in Hz.
sysfreq: real;
 
-- txclk frequency in Hz (if tximpl = impl_fast).
txclkfreq: real;
 
-- 2-log of division factor from system clock freq to timecode freq.
tickdiv: integer range 12 to 24 := 20;
 
209,6 → 212,7
spwstream_inst: spwstream
generic map (
sysfreq => sysfreq,
txclkfreq => txclkfreq,
rximpl => rximpl,
rxchunk => rxchunk,
tximpl => tximpl,
/spacewire_light/trunk/doc/timing_diagram.py
0,0 → 1,224
#!/usr/bin/env python
# timing_diagram.py, Joris van Rantwijk, Jul 2010.
 
"""
Generate timing diagrams for SpaceWire Light manual.
"""
 
from pyx import *
 
riseWidth = 0.15
clockWidth = 1.0
lowLevel = 0
highLevel = 0.5
midLevel = 0.25
 
def drawGrid(x, y1, y2, tstart, nclk):
 
for i in xrange(nclk):
x0 = x + clockWidth * (tstart + i)
c.stroke(path.line(x0, y1, x0, y2), [ style.linewidth.Thin, color.gray(0.5) ])
 
def drawSignal(x, y, events):
 
for i in xrange(len(events)-1):
(t, v) = events[i]
(tnext, vnext) = events[i+1]
 
firstevt = (i == 0)
lastevt = (i == len(events) - 2)
 
x0 = x + clockWidth * t
x1 = x + clockWidth * t + 0.5 * riseWidth
x2 = x + clockWidth * tnext - 0.5 * riseWidth
x3 = x + clockWidth * tnext
 
# fill
if v.lower() == 'x':
p = path.path(path.moveto(x1, y + lowLevel))
if not firstevt:
p.append(path.lineto(x0, y + midLevel))
p.append(path.lineto(x1, y + highLevel))
p.append(path.lineto(x2, y + highLevel))
if not lastevt:
p.append(path.lineto(x3, y + midLevel))
p.append(path.lineto(x2, y + lowLevel))
p.append(path.lineto(x1, y + lowLevel))
c.fill(p, [ color.gray(0.5) ])
 
lineStyle = [ ]
if v.lower() != 'x':
lineStyle.append(style.linewidth.Thick)
 
# draw low part of signal
if v.lower() in '0vx':
p = path.path()
if firstevt:
p.append(path.moveto(x1, y + lowLevel))
else:
p.append(path.moveto(x0, y + midLevel))
p.append(path.lineto(x1, y + lowLevel))
p.append(path.lineto(x2, y + lowLevel))
if not lastevt:
p.append(path.lineto(x3, y + midLevel))
c.stroke(p, lineStyle)
 
# draw high part of signal
if v.lower() in '1vx':
p = path.path()
if firstevt:
p.append(path.moveto(x1, y + highLevel))
else:
p.append(path.moveto(x0, y + midLevel))
p.append(path.lineto(x1, y + highLevel))
p.append(path.lineto(x2, y + highLevel))
if not lastevt:
p.append(path.lineto(x3, y + midLevel))
c.stroke(p, lineStyle)
 
# draw center part of signal
if v.lower() == 'z':
p = path.path()
if firstevt:
p.append(path.moveto(x1, y + midLevel))
else:
p.append(path.moveto(x0, y + midLevel))
if lastevt:
p.append(path.lineto(x2, y + midLevel))
else:
p.append(path.lineto(x3, y + midLevel))
c.stroke(p, lineStyle)
 
 
th = 0.3 # an appearance of "hold time" in diagram
xstart = 1.2
 
text.set(mode='latex')
 
#### Read timing
 
c = canvas.canvas()
 
drawGrid(xstart, 0.9, 5.5, 1, 9)
 
c.text(0, 5, '\\textsf{\\textbf{CLK}}')
drawSignal(xstart, 5,
[ (0.5+i/2.0, str(i%2)) for i in range(20) ])
 
c.text(0, 4, '\\textsf{\\textbf{RXVALID}}')
drawSignal(xstart, 4,
[ (0.5, '0'), (2+th, '1'), (7+th, '0'), (10, '') ])
 
c.text(0, 3, '\\textsf{\\textbf{RXFLAG}}')
drawSignal(xstart, 3,
[ (0.5, 'x'), (2+th, 'v'), (4+th, 'v'), (6+th, 'v'), (7+th, 'x'), (10, '') ])
 
c.text(0, 2, '\\textsf{\\textbf{RXDATA}}')
drawSignal(xstart, 2,
[ (0.5, 'x'), (2+th, 'v'), (4+th, 'v'), (6+th, 'v'), (7+th, 'x'), (10, '') ])
 
c.text(0, 1, '\\textsf{\\textbf{RXREAD}}')
drawSignal(xstart, 1,
[ (0.5, '0'), (3+th, '1'), (4+th, '0'), (5+th, '1'), (8+th, '0'), (10, '') ])
 
c.stroke(path.line(xstart+4*clockWidth, 0.4, xstart+4*clockWidth, 0.8), [ deco.arrow() ])
c.stroke(path.line(xstart+6*clockWidth, 0.4, xstart+6*clockWidth, 0.8), [ deco.arrow() ])
c.stroke(path.line(xstart+7*clockWidth, 0.4, xstart+7*clockWidth, 0.8), [ deco.arrow() ])
 
c.writeEPSfile('timing_read.eps')
 
#### Write timing
 
c = canvas.canvas()
 
drawGrid(xstart, 0.9, 5.5, 1, 9)
 
c.text(0, 5, '\\textsf{\\textbf{CLK}}')
drawSignal(xstart, 5,
[ (0.5+i/2.0, str(i%2)) for i in range(20) ])
 
c.text(0, 4, '\\textsf{\\textbf{TXRDY}}')
drawSignal(xstart, 4,
[ (0.5, '1'), (5+th, '0'), (6+th, '1'), (9+th, '0'), (10, '') ])
 
c.text(0, 3, '\\textsf{\\textbf{TXWRITE}}')
drawSignal(xstart, 3,
[ (0.5, '0'), (2+th, '1'), (3+th, '0'), (4+th, '1'), (8+th, '0'), (10, '') ])
 
c.text(0, 2, '\\textsf{\\textbf{TXFLAG}}')
drawSignal(xstart, 2,
[ (0.5, 'x'), (2+th, 'v'), (3+th, 'x'), (4+th, 'v'), (5+th, 'v'),
(7+th, 'v'), (8+th, 'x'), (10, '') ])
 
c.text(0, 1, '\\textsf{\\textbf{TXDATA}}')
drawSignal(xstart, 1,
[ (0.5, 'x'), (2+th, 'v'), (3+th, 'x'), (4+th, 'v'), (5+th, 'v'),
(7+th, 'v'), (8+th, 'x'), (10, '') ])
 
c.stroke(path.line(xstart+3*clockWidth, 0.4, xstart+3*clockWidth, 0.8), [ deco.arrow() ])
c.stroke(path.line(xstart+5*clockWidth, 0.4, xstart+5*clockWidth, 0.8), [ deco.arrow() ])
c.stroke(path.line(xstart+7*clockWidth, 0.4, xstart+7*clockWidth, 0.8), [ deco.arrow() ])
c.stroke(path.line(xstart+8*clockWidth, 0.4, xstart+8*clockWidth, 0.8), [ deco.arrow() ])
 
c.writeEPSfile('timing_write.eps')
 
#### Time codes
 
c = canvas.canvas()
 
xstart = 1.4
 
drawGrid(xstart, 0, 6.5, 1, 9)
 
c.text(0, 6, '\\textsf{\\textbf{CLK}}')
drawSignal(xstart, 6,
[ (0.5+i/2.0, str(i%2)) for i in range(20) ])
 
c.text(0, 5, '\\textsf{\\textbf{TICK\_OUT}}')
drawSignal(xstart, 5,
[ (0.5, '0'), (2+th, '1'), (3+th, '0'), (5+th, '1'), (6+th, '0'), (10, '') ])
 
c.text(0, 4, '\\textsf{\\textbf{CTRL\_OUT}}')
drawSignal(xstart, 4, [ (0.5, 'x'), (2+th, 'v'), (5+th, 'v'), (10, '') ])
 
c.text(0, 3, '\\textsf{\\textbf{TIME\_OUT}}')
drawSignal(xstart, 3, [ (0.5, 'x'), (2+th, 'v'), (5+th, 'v'), (10, '') ])
 
c.text(0, 2, '\\textsf{\\textbf{TICK\_IN}}')
drawSignal(xstart, 2, [ (0.5, '0'), (7+th, '1'), (8+th, '0'), (10, '') ])
 
c.text(0, 1, '\\textsf{\\textbf{CTRL\_IN}}')
drawSignal(xstart, 1, [ (0.5, 'x'), (7+th, 'v'), (8+th, 'x'), (10, '') ])
 
c.text(0, 0, '\\textsf{\\textbf{TIME\_IN}}')
drawSignal(xstart, 0, [ (0.5, 'x'), (7+th, 'v'), (8+th, 'x'), (10, '') ])
 
c.writeEPSfile('timing_timecode.eps')
 
#### Link status
 
c = canvas.canvas()
 
clockWidth = 0.8
xstart = 1.6
 
c.text(0, 5, '\\textsf{\\textbf{LINKSTART}}')
drawSignal(xstart, 5, [ (1, '0'), (2, '1'), (10, '0'), (19, '') ])
 
c.text(0, 4, '\\textsf{\\textbf{STARTED}}')
drawSignal(xstart, 4, [ (1, '0'), (4, '1'), (6, '0'), (19, '') ])
 
c.text(0, 3, '\\textsf{\\textbf{CONNECTING}}')
drawSignal(xstart, 3, [ (1, '0'), (6, '1'), (8, '0'), (19, '') ])
 
c.text(0, 2, '\\textsf{\\textbf{RUNNING}}')
drawSignal(xstart, 2, [ (1, '0'), (8, '1'), (16, '0'), (19, '') ])
 
c.text(0, 1, '\\textsf{\\textbf{ERRPAR}}')
drawSignal(xstart, 1, [ (1, '0'), (15.5, '1'), (16.5, '0'), (19, '') ])
 
c.stroke(path.line(xstart+6*clockWidth, 4.8, xstart+6*clockWidth, 2.6), [ style.linewidth.Thin ])
c.stroke(path.line(xstart+8*clockWidth, 3.8, xstart+8*clockWidth, 1.6), [ style.linewidth.Thin ])
 
c.writeEPSfile('timing_link.eps')
 
/spacewire_light/trunk/doc/Manual.odt Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
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spacewire_light/trunk/syn/spwstream_gr-xc3s1500/spwstream_top.vhd (revision 2) +++ spacewire_light/trunk/syn/spwstream_gr-xc3s1500/spwstream_top.vhd (revision 3) @@ -50,6 +50,7 @@ spwstream_inst: spwstream generic map ( sysfreq => 60.0e6, + txclkfreq => 240.0e6, rximpl => impl_fast, rxchunk => 4, tximpl => impl_fast, Index: spacewire_light/trunk/syn/spwstream_gr-xc3s1500/Makefile =================================================================== --- spacewire_light/trunk/syn/spwstream_gr-xc3s1500/Makefile (revision 2) +++ spacewire_light/trunk/syn/spwstream_gr-xc3s1500/Makefile (revision 3) @@ -60,7 +60,7 @@ $(RM) $(PROJ).twx $(PROJ).twr $(RM) $(PROJ).pcf $(PROJ)_map.mrp $(PROJ)_map.ncd $(PROJ)_map.ngm $(RM) $(PROJ).ncd $(PROJ).pad $(PROJ).par $(PROJ).xpi $(PROJ)_pad.csv $(PROJ)_pad.txt - $(RM) $(PROJ).bit $(PROJ).bgn $(PROJ).drca + $(RM) $(PROJ).bit $(PROJ).bgn $(PROJ).drc $(RM) $(PROJ).ptwx $(PROJ).unroutes *.xrpt $(PROJ)_summary.xml $(PROJ)_usage.xml $(PROJ)_map.map bitfile : $(PROJ).bit
/spacewire_light/trunk/syn/streamtest_gr-xc3s1500/streamtest.ucf
0,0 → 1,46
# Constraints for Pender GR-XC3S-1500 board (either revision).
 
# Board clock, 50 MHz = 20 ns nominal, - 2 ns margin = 18 ns
NET "clk" TNM_NET = "clk" ;
TIMESPEC "TS_clk" = PERIOD "clk" 18.0 ns ;
 
# Paths between fastclk and sysclk must be constrained to fastclk period.
# fastclk = 200 MHz = 5 ns nominal, - 1 ns margin = 4 ns
NET "sysclk" TNM_NET = "sysclk" ;
NET "fastclk" TNM_NET = "fastclk" ;
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 4 ns ;
TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 4 ns ;
 
# Board clock
NET "clk" LOC = "aa12" | IOSTANDARD = LVTTL;
 
# Note: LEDs use inverted logic
NET "led(0)" LOC = "f11" | IOSTANDARD = LVTTL;
NET "led(1)" LOC = "e11" | IOSTANDARD = LVTTL;
NET "led(2)" LOC = "d11" | IOSTANDARD = LVTTL;
NET "led(3)" LOC = "c11" | IOSTANDARD = LVTTL;
 
NET "btn_reset" LOC = "D19" | IOSTANDARD = LVTTL;
NET "btn_clear" LOC = "D21" | IOSTANDARD = LVTTL;
 
NET "switch(0)" LOC = "f16" | IOSTANDARD = LVTTL;
NET "switch(1)" LOC = "f13" | IOSTANDARD = LVTTL;
NET "switch(2)" LOC = "f12" | IOSTANDARD = LVTTL;
NET "switch(3)" LOC = "e16" | IOSTANDARD = LVTTL;
NET "switch(4)" LOC = "c22" | IOSTANDARD = LVTTL;
NET "switch(5)" LOC = "c20" | IOSTANDARD = LVTTL;
NET "switch(6)" LOC = "c21" | IOSTANDARD = LVTTL;
NET "switch(7)" LOC = "d20" | IOSTANDARD = LVTTL;
 
NET "spw_rxdp" LOC = "m1";# | IOSTANDARD = LVDS_25;
NET "spw_rxdn" LOC = "m2";# | IOSTANDARD = LVDS_25;
NET "spw_rxsp" LOC = "m3";# | IOSTANDARD = LVDS_25;
NET "spw_rxsn" LOC = "m4";# | IOSTANDARD = LVDS_25;
NET "spw_txdp" LOC = "n1";# | IOSTANDARD = LVDS_25;
NET "spw_txdn" LOC = "n2";# | IOSTANDARD = LVDS_25;
NET "spw_txsp" LOC = "n3";# | IOSTANDARD = LVDS_25;
NET "spw_txsn" LOC = "n4";# | IOSTANDARD = LVDS_25;
 
CONFIG PROHIBIT = "aa14"; #"fpgadata"
CONFIG PROHIBIT = "w12"; #"fpgainit"
 
/spacewire_light/trunk/syn/streamtest_gr-xc3s1500/Makefile
0,0 → 1,298
 
###############################################################################
## ##
## project-dependent variables ##
## ##
###############################################################################
 
# The project name. The bit-file that is generated in the end will be named
# "$(PROJ).bit"
 
PROJ = streamtest
 
# The top-level entity to be instantiated
 
TOPLEVEL = streamtest_top
 
# The VHDL sources that need to be compiled during synthesis
 
RTLDIR = ../../rtl/vhdl
VHDL_SOURCES = streamtest_top.vhd \
$(RTLDIR)/streamtest.vhd \
$(RTLDIR)/spwpkg.vhd \
$(RTLDIR)/spwstream.vhd \
$(RTLDIR)/spwlink.vhd \
$(RTLDIR)/spwram.vhd \
$(RTLDIR)/spwrecv.vhd \
$(RTLDIR)/spwxmit.vhd \
$(RTLDIR)/spwxmit_fast.vhd \
$(RTLDIR)/spwrecvfront_generic.vhd \
$(RTLDIR)/spwrecvfront_fast.vhd
 
# For Pender XC3S1500 board
FPGA_TYPE = xc3s1500-fg456-4
 
## For Pender XC3S2000 rev2 board
#FPGA_TYPE = xc3s2000-fg456-4
 
# The default target; recommended targets: "bitfile" or "upload"
 
default : bitfile
 
UCFFILE = streamtest.ucf
 
###############################################################################
## ##
## miscellaneous project-independent variables & rules ##
## ##
###############################################################################
 
# use this to make most tools quieter
OPT_INTSTYLE = -intstyle ise
 
# Phony (non file creating) targets
 
.PHONY : default clean bitfile
 
clean :
$(RM) -rf *~ work dump.xst _ngo 'file graph' xlnx_auto_0_xdb
$(RM) $(PROJ).xst-script
$(RM) $(PROJ).lso $(PROJ).prj
$(RM) $(PROJ).ngc $(PROJ).xst.log $(PROJ).syr $(PROJ).srp $(PROJ).ngr
$(RM) $(PROJ).ngd $(PROJ).bld
$(RM) $(PROJ).twx $(PROJ).twr
$(RM) $(PROJ).pcf $(PROJ)_map.mrp $(PROJ)_map.ncd $(PROJ)_map.ngm
$(RM) $(PROJ).ncd $(PROJ).pad $(PROJ).par $(PROJ).xpi $(PROJ)_pad.csv $(PROJ)_pad.txt
$(RM) $(PROJ).bit $(PROJ).bgn $(PROJ).drc
$(RM) $(PROJ).ptwx $(PROJ).unroutes *.xrpt $(PROJ)_summary.xml $(PROJ)_usage.xml $(PROJ)_map.map
 
bitfile : $(PROJ).bit
 
###############################################################################
# #
# STAGE 1: "xst" (Xilinx Synthesis Tool) #
# needs: #
# #
# $(PROJ).vhdl #
# $(PROJ).prj - Project file (created below) #
# $(PROJ).lso - Library Search Order file (created below) #
# #
# created files: #
# #
# $(PROJ).ngc - netlist #
# $(PROJ).ngr - XILINX-XDB 0.1 STUB 0.1 ASCII / XILINX-XDM V1.2e #
# (optional, depending on the '-rtlview' option) #
# $(PROJ).xst.log - human-readable synthesis report #
# (AKA .syr, .srp) #
# #
# created directories: #
# #
# work #
# dump.xst #
# #
###############################################################################
 
# Generate a "Library Search Order" file, containing just "work" for now.
 
$(PROJ).lso :
@echo "work" > $@
 
# Generate a "Project" file, consisting of lines containing each of the
# VHDL_SOURCES, preceded by "vhdl work".
 
$(PROJ).prj :
$(shell echo -n $(VHDL_SOURCES) | \
sed 's/\([^ ]\+\) */vhdl work \1\n/g' > $@)
 
$(PROJ).xst-script :
@echo "set -tmpdir /tmp" > $@
@echo "set -xsthdpdir ." >> $@
@echo "run" >> $@
@echo "-ifn $(PROJ).prj" >> $@
@echo "-ifmt mixed" >> $@
@echo "-ofn $(PROJ)" >> $@
@echo "-ofmt ngc" >> $@
@echo "-p $(FPGA_TYPE)" >> $@
@echo "-top $(TOPLEVEL)" >> $@
@echo "-opt_mode speed" >> $@
@echo "-opt_level 1" >> $@
@echo "-iuc no" >> $@
@echo "-lso $(PROJ).lso" >> $@
@echo "-keep_hierarchy no" >> $@
@echo "-glob_opt AllClockNets" >> $@
@echo "-rtlview no" >> $@
@echo "-read_cores yes" >> $@
# Note: write_timing_constraints is non-standard
@echo "-write_timing_constraints yes" >> $@
@echo "-cross_clock_analysis no" >> $@
# @echo "-hierarchy_separator _" >> $@
@echo "-bus_delimiter <>" >> $@
@echo "-case maintain" >> $@
@echo "-slice_utilization_ratio 100" >> $@
# @echo "-verilog2001 yes" >> $@
# @echo "-vlgincdir" >> $@
@echo "-fsm_extract yes" >> $@
@echo "-fsm_encoding auto" >> $@
@echo "-fsm_style lut" >> $@
# Note: safe_implementation is non-standard
@echo "-safe_implementation yes" >> $@
@echo "-ram_extract yes" >> $@
@echo "-ram_style auto" >> $@
@echo "-rom_extract yes" >> $@
@echo "-rom_style auto" >> $@
@echo "-mux_extract yes" >> $@
@echo "-mux_style auto" >> $@
@echo "-decoder_extract yes" >> $@
@echo "-priority_extract yes" >> $@
@echo "-shreg_extract yes" >> $@
@echo "-shift_extract yes" >> $@
@echo "-xor_collapse yes" >> $@
@echo "-resource_sharing yes" >> $@
@echo "-mult_style auto" >> $@
@echo "-iobuf yes" >> $@
@echo "-max_fanout 500" >> $@
@echo "-bufg 8" >> $@
@echo "-register_duplication yes" >> $@
@echo "-equivalent_register_removal yes" >> $@
@echo "-register_balancing no" >> $@
@echo "-slice_packing yes" >> $@
@echo "-optimize_primitives no" >> $@
@echo "-iob auto" >> $@
 
$(PROJ).ngc $(PROJ).xst.log : $(VHDL_SOURCES) $(PROJ).prj $(PROJ).lso $(PROJ).xst-script
rm -rf work dump.xst
xst $(OPT_INTSTYLE) -ifn $(PROJ).xst-script -ofn $(PROJ).xst.log
rm -rf work dump.xst
 
###############################################################################
# #
# STAGE 2: ngdbuild #
# needs: #
# #
# $(PROJ).ngc #
# #
# created files: #
# #
# $(PROJ).bld - human-readable build log #
# $(PROJ).ngd - XILINX-XDB 0.1 STUB 0.1 ASCII / XILINX-XDM V1.2e #
# #
# created dir: #
# _ngo #
# #
###############################################################################
 
$(PROJ).ngd $(PROJ).bld: $(PROJ).ngc $(UCFFILE)
rm -rf _ngo
ngdbuild $(OPT_INTSTYLE) -dd _ngo -aul -p $(FPGA_TYPE) $(if $(UCFFILE),-uc $(UCFFILE)) $(PROJ).ngc $(PROJ).ngd
rm -rf _ngo
 
###############################################################################
# #
# STAGE 3: Mapper #
# needs: #
# #
# $(PROJ).ngd #
# #
# created files: #
# #
# $(PROJ).pcf - ASCII file #
# $(PROJ)_map.mrp - human-readable mapping report #
# $(PROJ)_map.ncd - binary format #
# $(PROJ)_map.ngm - XILINX-XDB 0.1 STUB 0.1 ASCII / XILINX-XDM V1.2e #
# #
# NOTE: #
# #
# In order to prevent the make process from terminating on these spurious #
# problems, we precede the "map" invocation with a hyphen, instructing #
# make to ignore the return code from "map". #
# #
###############################################################################
 
$(PROJ).pcf $(PROJ)_map.mrp $(PROJ)_map.ncd $(PROJ)_map.ngm: $(PROJ).ngd
map $(OPT_INTSTYLE) -p $(FPGA_TYPE) -cm area -pr b -c 100 -o $(PROJ)_map.ncd $(PROJ).ngd $(PROJ).pcf
 
###############################################################################
# #
# STAGE 4: Place-and-Route #
# needs: #
# #
# $(PROJ).pcf #
# $(PROJ)_map.ncd #
# #
# created files: #
# #
# $(PROJ).ncd - binary file #
# $(PROJ).pad - ASCII file for import in spreadsheet #
# $(PROJ).par - human-readable place-and-route report #
# $(PROJ).xpi - ASCII file #
# $(PROJ)_pad.csv - human-readable CVS file #
# $(PROJ)_pad.txt - human-readable file #
# #
###############################################################################
 
$(PROJ).ncd $(PROJ).pad $(PROJ).par $(PROJ).xpi $(PROJ)_pad.csv $(PROJ)_pad.txt: $(PROJ).pcf $(PROJ)_map.ncd
par -w $(OPT_INTSTYLE) -t 1 $(PROJ)_map.ncd $(PROJ).ncd $(PROJ).pcf
 
###############################################################################
# #
# STAGE 4.5 (optional): trace #
# needs: #
# #
# created files: #
# #
###############################################################################
 
$(PROJ).twr $(PROJ).twx : $(PROJ).ncd $(PROJ).pcf
trce $(OPT_INTSTYLE) -e 5 -l 5 -u 5 -xml $(PROJ) $(PROJ).ncd -o $(PROJ).twr $(PROJ).pcf
 
###############################################################################
# #
# STAGE 5: Generate BIT-file #
# needs: #
# #
# $(PROJ).ncd #
# #
# created files: $(PROJ).bgn $(PROJ).bit $(PROJ).drc #
# #
# $(PROJ).bgn - human-readable BitGen report #
# $(PROJ).drc - human readable DRC report #
# $(PROJ).bit - binary image file #
# #
###############################################################################
 
# We omit "-g StartUpClk:JtagClk" ; this doesn't work if the image is loaded
# from a PROM.
 
# Note: LCK_cycle:3 is non-standard
OPT_BITGEN = -w \
-g DebugBitstream:No \
-g Binary:no \
-g CRC:Enable \
-g ConfigRate:6 \
-g CclkPin:PullUp \
-g M0Pin:PullUp \
-g M1Pin:PullUp \
-g M2Pin:PullUp \
-g ProgPin:PullUp \
-g DonePin:PullUp \
-g TckPin:PullUp \
-g TdiPin:PullUp \
-g TdoPin:PullUp \
-g TmsPin:PullUp \
-g UnusedPin:PullDown \
-g UserID:0xFFFFFFFF \
-g DCMShutDown:Disable \
-g DONE_cycle:4 \
-g GTS_cycle:5 \
-g GWE_cycle:6 \
-g LCK_cycle:3 \
-g Match_cycle:Auto \
-g Security:None \
-g DonePipe:No \
-g DriveDone:No
 
$(PROJ).bit $(PROJ).bgn $(PROJ).drc: $(PROJ).ncd
bitgen $(OPT_INTSTYLE) $(OPT_BITGEN) $(PROJ).ncd
 
###############################################################################
 
/spacewire_light/trunk/syn/streamtest_gr-xc3s1500/streamtest_top.vhd
0,0 → 1,259
--
-- Test of spwstream on Pender GR-XC3S-1500 board.
-- 60 MHz system clock; 200 MHz receive clock and transmit clock.
--
-- LED 0 = link run
-- LED 1 = link error (sticky until clear button)
-- LED 2 = gotdata
-- LED 3 = data/timecode error (sticky until reset)
--
-- Button S2 = reset
-- Button S3 = clear LED 1
--
-- Switch 0 = link start
-- Switch 1 = link disable
-- Switch 2 = send data
-- Switch 3 = send time codes
-- Switch 4-7 = bits 0-3 of tx bit rate scale factor
--
-- SpaceWire signals on expansion connector J12:
-- Data In pos,neg = m1,m2 = pin 3,2
-- Strobe In pos,neg = m3,m4 = pin 6,5
-- Data Out pos,neg = n1,n2 = pin 9,8
-- Strobe Out pos,neg = n3,n4 = pin 12,11
--
-- To get proper LVDS signals from connector J12, the voltage on I/O bank 6
-- must be set to 2.5V. This is the default on GR-XC3S-1500-rev2, but on
-- GR-XC3S-1500-rev1 a change is required on the board (described in
-- the board manual).
--
-- To terminate the incoming LVDS signals, 100 Ohm termination resistors
-- must be installed on the board in positions R120 and R121.
--
-- The SpaceWire port should be looped back to itself, either directly
-- or via an other SpaceWire device. For a direct loopback, place 4 wires
-- from the output pins to the corresponding input pins. For an indirect
-- loopback, connect the SpaceWire signals to an additional SpaceWire device
-- which is programmed to echo everything it receives (characters, packets,
-- time codes). See the datasheet for a wiring diagram from J12 to MDM9.
--
 
library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
use work.spwpkg.all;
 
entity streamtest_top is
 
port (
clk: in std_logic;
btn_reset: in std_logic;
btn_clear: in std_logic;
switch: in std_logic_vector(7 downto 0);
led: out std_logic_vector(3 downto 0);
spw_rxdp: in std_logic;
spw_rxdn: in std_logic;
spw_rxsp: in std_logic;
spw_rxsn: in std_logic;
spw_txdp: out std_logic;
spw_txdn: out std_logic;
spw_txsp: out std_logic;
spw_txsn: out std_logic );
 
end entity streamtest_top;
 
architecture streamtest_top_arch of streamtest_top is
 
-- Clock generation.
signal boardclk: std_logic;
signal sysclk: std_logic;
signal fastclk: std_logic;
 
-- Synchronize buttons
signal s_resetbtn: std_logic := '0';
signal s_clearbtn: std_logic := '0';
 
-- Sticky LED
signal s_linkerrorled: std_logic := '0';
 
-- Interface signals.
signal s_rst: std_logic := '1';
signal s_linkstart: std_logic := '0';
signal s_autostart: std_logic := '0';
signal s_linkdisable: std_logic := '0';
signal s_senddata: std_logic := '0';
signal s_sendtick: std_logic := '0';
signal s_txdivcnt: std_logic_vector(7 downto 0) := "00000000";
signal s_linkstarted: std_logic;
signal s_linkconnecting: std_logic;
signal s_linkrun: std_logic;
signal s_linkerror: std_logic;
signal s_gotdata: std_logic;
signal s_dataerror: std_logic;
signal s_tickerror: std_logic;
signal s_spwdi: std_logic;
signal s_spwsi: std_logic;
signal s_spwdo: std_logic;
signal s_spwso: std_logic;
 
-- Make clock nets visible to UCF file.
attribute KEEP: string;
attribute KEEP of sysclk: signal is "SOFT";
attribute KEEP of fastclk: signal is "SOFT";
 
component streamtest is
generic (
sysfreq: real;
txclkfreq: real;
tickdiv: integer range 12 to 24 := 20;
rximpl: spw_implementation_type := impl_generic;
rxchunk: integer range 1 to 4 := 1;
tximpl: spw_implementation_type := impl_generic;
rxfifosize_bits: integer range 6 to 14 := 11;
txfifosize_bits: integer range 2 to 14 := 11 );
port (
clk: in std_logic;
rxclk: in std_logic;
txclk: in std_logic;
rst: in std_logic;
linkstart: in std_logic;
autostart: in std_logic;
linkdisable: in std_logic;
senddata: in std_logic;
sendtick: in std_logic;
txdivcnt: in std_logic_vector(7 downto 0);
linkstarted: out std_logic;
linkconnecting: out std_logic;
linkrun: out std_logic;
linkerror: out std_logic;
gotdata: out std_logic;
dataerror: out std_logic;
tickerror: out std_logic;
spw_di: in std_logic;
spw_si: in std_logic;
spw_do: out std_logic;
spw_so: out std_logic );
end component;
 
begin
 
-- Buffer incoming clock.
bufg0: BUFG port map ( I => clk, O => boardclk );
 
-- Generate 60 MHz system clock.
dcm0: DCM
generic map (
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 6,
CLK_FEEDBACK => "NONE",
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
STARTUP_WAIT => true )
port map (
CLKIN => boardclk,
RST => '0',
CLKFX => sysclk );
 
-- Generate 200 MHz fast clock.
dcm1: DCM
generic map (
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLK_FEEDBACK => "NONE",
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
STARTUP_WAIT => true )
port map (
CLKIN => boardclk,
RST => '0',
CLKFX => fastclk );
 
-- Streamtest instance
streamtest_inst: streamtest
generic map (
sysfreq => 60.0e6,
txclkfreq => 200.0e6,
tickdiv => 22,
rximpl => impl_fast,
rxchunk => 4,
tximpl => impl_fast,
rxfifosize_bits => 11,
txfifosize_bits => 10 )
port map (
clk => sysclk,
rxclk => fastclk,
txclk => fastclk,
rst => s_rst,
linkstart => s_linkstart,
autostart => s_autostart,
linkdisable => s_linkdisable,
senddata => s_senddata,
sendtick => s_sendtick,
txdivcnt => s_txdivcnt,
linkstarted => s_linkstarted,
linkconnecting => s_linkconnecting,
linkrun => s_linkrun,
linkerror => s_linkerror,
gotdata => s_gotdata,
dataerror => s_dataerror,
tickerror => s_tickerror,
spw_di => s_spwdi,
spw_si => s_spwsi,
spw_do => s_spwdo,
spw_so => s_spwso );
 
-- LVDS buffers
spwdi_pad: IBUFDS
generic map ( IOSTANDARD => "LVDS_25" )
port map ( O => s_spwdi, I => spw_rxdp, IB => spw_rxdn );
spwsi_pad: IBUFDS
generic map ( IOSTANDARD => "LVDS_25" )
port map ( O => s_spwsi, I => spw_rxsp, IB => spw_rxsn );
spwdo_pad: OBUFDS
generic map ( IOSTANDARD => "LVDS_25" )
port map ( O => spw_txdp, OB => spw_txdn, I => s_spwdo );
spwso_pad: OBUFDS
generic map ( IOSTANDARD => "LVDS_25" )
port map ( O => spw_txsp, OB => spw_txsn, I => s_spwso );
 
process (sysclk) is
begin
if rising_edge(sysclk) then
 
-- Synchronize buttons
s_resetbtn <= btn_reset;
s_rst <= s_resetbtn;
s_clearbtn <= btn_clear;
 
-- Synchronize switch settings
s_autostart <= '0';
s_linkstart <= switch(0);
s_linkdisable <= switch(1);
s_senddata <= switch(2);
s_sendtick <= switch(3);
s_txdivcnt(3 downto 0) <= switch(7 downto 4);
 
-- Sticky link error LED
s_linkerrorled <= (s_linkerrorled or s_linkerror) and
(not s_clearbtn) and
(not s_resetbtn);
 
-- Drive LEDs (inverted logic)
led(0) <= not s_linkrun;
led(1) <= not s_linkerrorled;
led(2) <= not s_gotdata;
led(3) <= not (s_dataerror or s_tickerror);
 
end if;
end process;
 
end architecture streamtest_top_arch;
/spacewire_light/trunk/syn/streamtest_digilent-xc3s200/streamtest_top.vhd
1,5 → 1,6
--
-- Test of spwstream on Digilent XC3S200 board.
-- 60 MHz system clock, 200 MHz receive clock and transmit clock.
--
-- LED 0 = link started
-- LED 1 = link connecting
98,6 → 99,7
component streamtest is
generic (
sysfreq: real;
txclkfreq: real;
tickdiv: integer range 12 to 24 := 20;
rximpl: spw_implementation_type := impl_generic;
rxchunk: integer range 1 to 4 := 1;
173,6 → 175,7
streamtest_inst: streamtest
generic map (
sysfreq => 60.0e6,
txclkfreq => 200.0e6,
tickdiv => 22,
rximpl => impl_fast,
rxchunk => 4,
/spacewire_light/trunk/README.txt
30,19 → 30,11
The core is "light" in the sense that it does not provide additional
features such as RMAP, routing etc.
 
This core would be very suitable for application in lab environments,
to add a SpaceWire interface to a custom FPGA design, and for interfacing
between existing SpaceWire equipment and a computer.
See doc/Manual.pdf for more information.
 
The project is currently very much in alpha phase. Most importantly,
there is no proper documentation. I WILL PROVIDE DOCUMENTATION SOON.
 
Short term plan:
* more testing
* documentation
 
Long term plan:
Future plans:
* add AMBA bus interface
* try to run on Virtex
 
 
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