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/spacewire_light/trunk/doc/Manual.odt

spacewire_light/trunk/doc/Manual.odt Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: spacewire_light/trunk/doc/timing_diagram.py =================================================================== --- spacewire_light/trunk/doc/timing_diagram.py (revision 3) +++ spacewire_light/trunk/doc/timing_diagram.py (nonexistent) @@ -1,224 +0,0 @@ -#!/usr/bin/env python -# timing_diagram.py, Joris van Rantwijk, Jul 2010. - -""" -Generate timing diagrams for SpaceWire Light manual. -""" - -from pyx import * - -riseWidth = 0.15 -clockWidth = 1.0 -lowLevel = 0 -highLevel = 0.5 -midLevel = 0.25 - -def drawGrid(x, y1, y2, tstart, nclk): - - for i in xrange(nclk): - x0 = x + clockWidth * (tstart + i) - c.stroke(path.line(x0, y1, x0, y2), [ style.linewidth.Thin, color.gray(0.5) ]) - -def drawSignal(x, y, events): - - for i in xrange(len(events)-1): - (t, v) = events[i] - (tnext, vnext) = events[i+1] - - firstevt = (i == 0) - lastevt = (i == len(events) - 2) - - x0 = x + clockWidth * t - x1 = x + clockWidth * t + 0.5 * riseWidth - x2 = x + clockWidth * tnext - 0.5 * riseWidth - x3 = x + clockWidth * tnext - - # fill - if v.lower() == 'x': - p = path.path(path.moveto(x1, y + lowLevel)) - if not firstevt: - p.append(path.lineto(x0, y + midLevel)) - p.append(path.lineto(x1, y + highLevel)) - p.append(path.lineto(x2, y + highLevel)) - if not lastevt: - p.append(path.lineto(x3, y + midLevel)) - p.append(path.lineto(x2, y + lowLevel)) - p.append(path.lineto(x1, y + lowLevel)) - c.fill(p, [ color.gray(0.5) ]) - - lineStyle = [ ] - if v.lower() != 'x': - lineStyle.append(style.linewidth.Thick) - - # draw low part of signal - if v.lower() in '0vx': - p = path.path() - if firstevt: - p.append(path.moveto(x1, y + lowLevel)) - else: - p.append(path.moveto(x0, y + midLevel)) - p.append(path.lineto(x1, y + lowLevel)) - p.append(path.lineto(x2, y + lowLevel)) - if not lastevt: - p.append(path.lineto(x3, y + midLevel)) - c.stroke(p, lineStyle) - - # draw high part of signal - if v.lower() in '1vx': - p = path.path() - if firstevt: - p.append(path.moveto(x1, y + highLevel)) - else: - p.append(path.moveto(x0, y + midLevel)) - p.append(path.lineto(x1, y + highLevel)) - p.append(path.lineto(x2, y + highLevel)) - if not lastevt: - p.append(path.lineto(x3, y + midLevel)) - c.stroke(p, lineStyle) - - # draw center part of signal - if v.lower() == 'z': - p = path.path() - if firstevt: - p.append(path.moveto(x1, y + midLevel)) - else: - p.append(path.moveto(x0, y + midLevel)) - if lastevt: - p.append(path.lineto(x2, y + midLevel)) - else: - p.append(path.lineto(x3, y + midLevel)) - c.stroke(p, lineStyle) - - -th = 0.3 # an appearance of "hold time" in diagram -xstart = 1.2 - -text.set(mode='latex') - -#### Read timing - -c = canvas.canvas() - -drawGrid(xstart, 0.9, 5.5, 1, 9) - -c.text(0, 5, '\\textsf{\\textbf{CLK}}') -drawSignal(xstart, 5, - [ (0.5+i/2.0, str(i%2)) for i in range(20) ]) - -c.text(0, 4, '\\textsf{\\textbf{RXVALID}}') -drawSignal(xstart, 4, - [ (0.5, '0'), (2+th, '1'), (7+th, '0'), (10, '') ]) - -c.text(0, 3, '\\textsf{\\textbf{RXFLAG}}') -drawSignal(xstart, 3, - [ (0.5, 'x'), (2+th, 'v'), (4+th, 'v'), (6+th, 'v'), (7+th, 'x'), (10, '') ]) - -c.text(0, 2, '\\textsf{\\textbf{RXDATA}}') -drawSignal(xstart, 2, - [ (0.5, 'x'), (2+th, 'v'), (4+th, 'v'), (6+th, 'v'), (7+th, 'x'), (10, '') ]) - -c.text(0, 1, '\\textsf{\\textbf{RXREAD}}') -drawSignal(xstart, 1, - [ (0.5, '0'), (3+th, '1'), (4+th, '0'), (5+th, '1'), (8+th, '0'), (10, '') ]) - -c.stroke(path.line(xstart+4*clockWidth, 0.4, xstart+4*clockWidth, 0.8), [ deco.arrow() ]) -c.stroke(path.line(xstart+6*clockWidth, 0.4, xstart+6*clockWidth, 0.8), [ deco.arrow() ]) -c.stroke(path.line(xstart+7*clockWidth, 0.4, xstart+7*clockWidth, 0.8), [ deco.arrow() ]) - -c.writeEPSfile('timing_read.eps') - -#### Write timing - -c = canvas.canvas() - -drawGrid(xstart, 0.9, 5.5, 1, 9) - -c.text(0, 5, '\\textsf{\\textbf{CLK}}') -drawSignal(xstart, 5, - [ (0.5+i/2.0, str(i%2)) for i in range(20) ]) - -c.text(0, 4, '\\textsf{\\textbf{TXRDY}}') -drawSignal(xstart, 4, - [ (0.5, '1'), (5+th, '0'), (6+th, '1'), (9+th, '0'), (10, '') ]) - -c.text(0, 3, '\\textsf{\\textbf{TXWRITE}}') -drawSignal(xstart, 3, - [ (0.5, '0'), (2+th, '1'), (3+th, '0'), (4+th, '1'), (8+th, '0'), (10, '') ]) - -c.text(0, 2, '\\textsf{\\textbf{TXFLAG}}') -drawSignal(xstart, 2, - [ (0.5, 'x'), (2+th, 'v'), (3+th, 'x'), (4+th, 'v'), (5+th, 'v'), - (7+th, 'v'), (8+th, 'x'), (10, '') ]) - -c.text(0, 1, '\\textsf{\\textbf{TXDATA}}') -drawSignal(xstart, 1, - [ (0.5, 'x'), (2+th, 'v'), (3+th, 'x'), (4+th, 'v'), (5+th, 'v'), - (7+th, 'v'), (8+th, 'x'), (10, '') ]) - -c.stroke(path.line(xstart+3*clockWidth, 0.4, xstart+3*clockWidth, 0.8), [ deco.arrow() ]) -c.stroke(path.line(xstart+5*clockWidth, 0.4, xstart+5*clockWidth, 0.8), [ deco.arrow() ]) -c.stroke(path.line(xstart+7*clockWidth, 0.4, xstart+7*clockWidth, 0.8), [ deco.arrow() ]) -c.stroke(path.line(xstart+8*clockWidth, 0.4, xstart+8*clockWidth, 0.8), [ deco.arrow() ]) - -c.writeEPSfile('timing_write.eps') - -#### Time codes - -c = canvas.canvas() - -xstart = 1.4 - -drawGrid(xstart, 0, 6.5, 1, 9) - -c.text(0, 6, '\\textsf{\\textbf{CLK}}') -drawSignal(xstart, 6, - [ (0.5+i/2.0, str(i%2)) for i in range(20) ]) - -c.text(0, 5, '\\textsf{\\textbf{TICK\_OUT}}') -drawSignal(xstart, 5, - [ (0.5, '0'), (2+th, '1'), (3+th, '0'), (5+th, '1'), (6+th, '0'), (10, '') ]) - -c.text(0, 4, '\\textsf{\\textbf{CTRL\_OUT}}') -drawSignal(xstart, 4, [ (0.5, 'x'), (2+th, 'v'), (5+th, 'v'), (10, '') ]) - -c.text(0, 3, '\\textsf{\\textbf{TIME\_OUT}}') -drawSignal(xstart, 3, [ (0.5, 'x'), (2+th, 'v'), (5+th, 'v'), (10, '') ]) - -c.text(0, 2, '\\textsf{\\textbf{TICK\_IN}}') -drawSignal(xstart, 2, [ (0.5, '0'), (7+th, '1'), (8+th, '0'), (10, '') ]) - -c.text(0, 1, '\\textsf{\\textbf{CTRL\_IN}}') -drawSignal(xstart, 1, [ (0.5, 'x'), (7+th, 'v'), (8+th, 'x'), (10, '') ]) - -c.text(0, 0, '\\textsf{\\textbf{TIME\_IN}}') -drawSignal(xstart, 0, [ (0.5, 'x'), (7+th, 'v'), (8+th, 'x'), (10, '') ]) - -c.writeEPSfile('timing_timecode.eps') - -#### Link status - -c = canvas.canvas() - -clockWidth = 0.8 -xstart = 1.6 - -c.text(0, 5, '\\textsf{\\textbf{LINKSTART}}') -drawSignal(xstart, 5, [ (1, '0'), (2, '1'), (10, '0'), (19, '') ]) - -c.text(0, 4, '\\textsf{\\textbf{STARTED}}') -drawSignal(xstart, 4, [ (1, '0'), (4, '1'), (6, '0'), (19, '') ]) - -c.text(0, 3, '\\textsf{\\textbf{CONNECTING}}') -drawSignal(xstart, 3, [ (1, '0'), (6, '1'), (8, '0'), (19, '') ]) - -c.text(0, 2, '\\textsf{\\textbf{RUNNING}}') -drawSignal(xstart, 2, [ (1, '0'), (8, '1'), (16, '0'), (19, '') ]) - -c.text(0, 1, '\\textsf{\\textbf{ERRPAR}}') -drawSignal(xstart, 1, [ (1, '0'), (15.5, '1'), (16.5, '0'), (19, '') ]) - -c.stroke(path.line(xstart+6*clockWidth, 4.8, xstart+6*clockWidth, 2.6), [ style.linewidth.Thin ]) -c.stroke(path.line(xstart+8*clockWidth, 3.8, xstart+8*clockWidth, 1.6), [ style.linewidth.Thin ]) - -c.writeEPSfile('timing_link.eps') - Index: spacewire_light/trunk/bench/vhdl/streamtest_tb.vhd =================================================================== --- spacewire_light/trunk/bench/vhdl/streamtest_tb.vhd (revision 3) +++ spacewire_light/trunk/bench/vhdl/streamtest_tb.vhd (revision 2) @@ -28,7 +28,6 @@ component streamtest is generic ( sysfreq: real; - txclkfreq: real; tickdiv: integer range 12 to 24 := 20; rximpl: spw_implementation_type := impl_generic; rxchunk: integer range 1 to 4 := 1; @@ -85,7 +84,6 @@ streamtest_inst: streamtest generic map ( sysfreq => sys_clock_freq, - txclkfreq => sys_clock_freq, tickdiv => 16, rximpl => impl_generic, rxchunk => 1, Index: spacewire_light/trunk/rtl/vhdl/spwstream.vhd =================================================================== --- spacewire_light/trunk/rtl/vhdl/spwstream.vhd (revision 3) +++ spacewire_light/trunk/rtl/vhdl/spwstream.vhd (revision 2) @@ -11,7 +11,7 @@ -- -- The SpaceWire standard requires that each transceiver use an initial -- signalling rate of 10 Mbit/s. This implies that the system clock frequency --- must be a multiple of 10 MHz. See the manual for further details on +-- must be a multiple of 10 MHz. See the datasheet for further details on -- bitrates and clocking. -- @@ -26,14 +26,9 @@ -- System clock frequency in Hz. -- This must be set to the frequency of "clk". It is used to setup -- counters for reset timing, disconnect timeout and to transmit - -- at 10 Mbit/s during the link handshake. + -- at 10 Mbit/s during the handshake. sysfreq: real; - -- Transmit clock frequency in Hz (only if tximpl = impl_fast). - -- This must be set to the frequency of "txclk". It is used to - -- transmit at 10 Mbit/s during the link handshake. - txclkfreq: real := 0.0; - -- Selection of a receiver front-end implementation. rximpl: spw_implementation_type := impl_generic; @@ -72,13 +67,12 @@ -- Without autostart or linkstart, the link remains in state Ready. linkstart: in std_logic; - -- Do not start link (overrides linkstart and autostart) and/or - -- disconnect a running link. + -- Do not start link (overrides linkstart and autostart) and/or disconnect + -- if the link is in state Run. linkdis: in std_logic; - -- Scaling factor minus 1, used to scale the transmit base clock into - -- the transmission bit rate. The system clock (for impl_generic) or - -- the txclk (for impl_fast) is divided by (unsigned(txdivcnt) + 1). + -- Scaling factor minus 1, used to scale the system clock into the transmission + -- signalling rate. The system clock is divided by (unsigned(divcnt) + 1). -- Changing this signal will immediately change the transmission rate. -- During link setup, the transmission rate is always 10 Mbit/s. txdivcnt: in std_logic_vector(7 downto 0); @@ -199,12 +193,8 @@ constant disconnect_time: integer := integer(sysfreq * 850.0e-9); -- Initial tx clock scaler (10 Mbit). - type impl_to_real_type is array(spw_implementation_type) of real; - constant tximpl_to_txclk_freq: impl_to_real_type := - (impl_generic => sysfreq, impl_fast => txclkfreq); - constant effective_txclk_freq: real := tximpl_to_txclk_freq(tximpl); constant default_divcnt: std_logic_vector(7 downto 0) := - std_logic_vector(to_unsigned(integer(effective_txclk_freq / 10.0e6 - 1.0), 8)); + std_logic_vector(to_unsigned(integer(sysfreq / 10.0e6 - 1.0), 8)); -- Registers. type regs_type is record

/spacewire_light/trunk/rtl/vhdl/spwxmit_fast.vhd

122,7 → 122,7