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URL https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk

Subversion Repositories spacewire_light

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  • This comparison shows the changes necessary to convert path 
    /spacewire_light/trunk/syn/spwamba_gr-xc3s1500
    from Rev 7 to Rev 12
    ↔ Reverse comparison
  •

Rev 7 → Rev 12

/leon3mp.ucf
436,12 → 436,12
NET "ata_data(1)" LOC = "g18" | IOSTANDARD = LVTTL; #genio(27)
NET "ata_data(0)" LOC = "j18" | IOSTANDARD = LVTTL; #genio(28)
#NET "genio(29)" LOC = "j21" | IOSTANDARD = LVTTL; #genio(29) / not used
NET "ata_dmarq" LOC = "j22" | IOSTANDARD = LVTTL | PULLDOWN; #genio(30) / DMARQ
NET "genio(30)" LOC = "j22" | IOSTANDARD = LVTTL;
NET "ata_diow" LOC = "h21" | IOSTANDARD = LVTTL; #genio(31) / nDIOW
NET "ata_dior" LOC = "k22" | IOSTANDARD = LVTTL; #genio(32) / DIOR
NET "ata_iordy" LOC = "k21" | IOSTANDARD = LVTTL | PULLUP; #genio(33) / IORDY
NET "genio(33)" LOC = "k21" | IOSTANDARD = LVTTL;
NET "ata_dmack" LOC = "k18" | IOSTANDARD = LVTTL; #genio(34) / nDMACK
NET "ata_intrq" LOC = "l19" | IOSTANDARD = LVTTL | PULLDOWN; #genio(35) / INTRQ
NET "genio(35)" LOC = "l19" | IOSTANDARD = LVTTL;
NET "ata_da(1)" LOC = "l18" | IOSTANDARD = LVTTL; #genio(36) / DA1
NET "ata_da(0)" LOC = "k17" | IOSTANDARD = LVTTL; #genio(37) / DA0
NET "ata_cs0" LOC = "l17" | IOSTANDARD = LVTTL; #genio(38) / nCS0
/config.in
56,10 → 56,10
source lib/gaisler/greth/greth.in
endmenu
 
mainmenu_option next_comment
comment 'IDE Disk controller '
source lib/gaisler/ata/ata.in
endmenu
# mainmenu_option next_comment
# comment 'IDE Disk controller '
# source lib/gaisler/ata/ata.in
# endmenu
 
mainmenu_option next_comment
comment 'CAN '
/Makefile
5,7 → 5,7
-include .config
 
# Change this to your local GRLIB directory.
GRLIB = /data/leon3/grlib-gpl-1.1.0-b4104
GRLIB = /data/leon3/grlib-gpl-1.2.2-b4123
 
TOP=leon3mp
BOARD=gr-xc3s-1500
/leon3mp.vhd
36,7 → 36,6
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.grusb.all;
use gaisler.ata.all;
 
library esa;
use esa.memoryctrl.all;
157,22 → 156,7
usb_txvalid : out std_ulogic;
usb_validh : inout std_ulogic;
usb_xcvrsel : out std_ulogic;
usb_vbus : in std_ulogic;
 
ata_rstn : out std_logic;
ata_data : inout std_logic_vector(15 downto 0);
ata_da : out std_logic_vector(2 downto 0);
ata_cs0 : out std_logic;
ata_cs1 : out std_logic;
ata_dior : out std_logic;
ata_diow : out std_logic;
ata_iordy : in std_logic;
ata_intrq : in std_logic;
ata_dmarq : in std_logic;
ata_dmack : out std_logic;
--ata_dasp : in std_logic
ata_csel : out std_logic
 
usb_vbus : in std_ulogic
);
end;
 
185,7 → 169,7
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+CFG_SVGA_ENABLE+
CFG_ATA+CFG_GRUSBDC;
CFG_GRUSBDC;
 
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
241,7 → 225,7
 
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN + CFG_ATA + CFG_GRUSBDC;
constant IOAEN : integer := CFG_CAN + CFG_GRUSBDC;
 
signal stati : ahbstat_in_type;
 
256,9 → 240,6
signal usbi : grusb_in_type;
signal usbo : grusb_out_type;
 
signal idei : ata_in_type;
signal ideo : ata_out_type;
 
constant SPW_LOOP_BACK : integer := 0;
 
signal dac_clk, video_clk, clk50 : std_logic; -- signals to vga_clkgen.
824,57 → 805,6
end generate usb_dcl0;
-----------------------------------------------------------------------
--- AHB ATA ----------------------------------------------------------
-----------------------------------------------------------------------
 
ata0 : if CFG_ATA = 1 generate
atac0 : atactrl
generic map(
tech => 0, fdepth => CFG_ATAFIFO,
mhindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+
CFG_GRUSBDC,
shindex => 3, haddr => 16#A00#, hmask => 16#fff#, pirq => CFG_ATAIRQ,
mwdma => CFG_ATADMA, TWIDTH => 8,
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 => 6, -- 70ns
PIO_mode0_T2 => 28, -- 290ns
PIO_mode0_T4 => 2, -- 30ns
PIO_mode0_Teoc => 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
)
port map(
rst => rstn, arst => vcc(0), clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN+
CFG_GRUSB_DCL+CFG_GRUSBDC),
ahbsi => ahbsi, ahbso => ahbso(3), atai => idei, atao => ideo);
ata_rstn_pad : outpad generic map (tech => padtech)
port map (ata_rstn, ideo.rstn);
ata_data_pad : iopadv generic map (tech => padtech, width => 16, oepol => 1)
port map (ata_data, ideo.ddo, ideo.oen, idei.ddi);
ata_da_pad : outpadv generic map (tech => padtech, width => 3)
port map (ata_da, ideo.da);
ata_cs0_pad : outpad generic map (tech => padtech)
port map (ata_cs0, ideo.cs0);
ata_cs1_pad : outpad generic map (tech => padtech)
port map (ata_cs1, ideo.cs1);
ata_dior_pad : outpad generic map (tech => padtech)
port map (ata_dior, ideo.dior);
ata_diow_pad : outpad generic map (tech => padtech)
port map (ata_diow, ideo.diow);
iordy_pad : inpad generic map (tech => padtech)
port map (ata_iordy, idei.iordy);
intrq_pad : inpad generic map (tech => padtech)
port map (ata_intrq, idei.intrq);
dmarq_pad : inpad generic map (tech => padtech)
port map (ata_dmarq, idei.dmarq);
dmack_pad : outpad generic map (tech => padtech)
port map (ata_dmack, ideo.dmack);
ata_csel <= '0';
end generate;
 
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
 

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