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  • This comparison shows the changes necessary to convert path
    /spacewire_light/trunk/syn/streamtest_digilent-xc3s200
    from Rev 2 to Rev 3
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Rev 2 → Rev 3

/streamtest_top.vhd
1,5 → 1,6
--
-- Test of spwstream on Digilent XC3S200 board.
-- 60 MHz system clock, 200 MHz receive clock and transmit clock.
--
-- LED 0 = link started
-- LED 1 = link connecting
98,6 → 99,7
component streamtest is
generic (
sysfreq: real;
txclkfreq: real;
tickdiv: integer range 12 to 24 := 20;
rximpl: spw_implementation_type := impl_generic;
rxchunk: integer range 1 to 4 := 1;
173,6 → 175,7
streamtest_inst: streamtest
generic map (
sysfreq => 60.0e6,
txclkfreq => 200.0e6,
tickdiv => 22,
rximpl => impl_fast,
rxchunk => 4,

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