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/spwstream_gr-xc3s1500/spwstream_top.vhd
50,6 → 50,7
spwstream_inst: spwstream
generic map (
sysfreq => 60.0e6,
txclkfreq => 240.0e6,
rximpl => impl_fast,
rxchunk => 4,
tximpl => impl_fast,
/spwstream_gr-xc3s1500/Makefile
60,7 → 60,7
$(RM) $(PROJ).twx $(PROJ).twr
$(RM) $(PROJ).pcf $(PROJ)_map.mrp $(PROJ)_map.ncd $(PROJ)_map.ngm
$(RM) $(PROJ).ncd $(PROJ).pad $(PROJ).par $(PROJ).xpi $(PROJ)_pad.csv $(PROJ)_pad.txt
$(RM) $(PROJ).bit $(PROJ).bgn $(PROJ).drca
$(RM) $(PROJ).bit $(PROJ).bgn $(PROJ).drc
$(RM) $(PROJ).ptwx $(PROJ).unroutes *.xrpt $(PROJ)_summary.xml $(PROJ)_usage.xml $(PROJ)_map.map
 
bitfile : $(PROJ).bit
/streamtest_gr-xc3s1500/streamtest.ucf
0,0 → 1,46
# Constraints for Pender GR-XC3S-1500 board (either revision).
 
# Board clock, 50 MHz = 20 ns nominal, - 2 ns margin = 18 ns
NET "clk" TNM_NET = "clk" ;
TIMESPEC "TS_clk" = PERIOD "clk" 18.0 ns ;
 
# Paths between fastclk and sysclk must be constrained to fastclk period.
# fastclk = 200 MHz = 5 ns nominal, - 1 ns margin = 4 ns
NET "sysclk" TNM_NET = "sysclk" ;
NET "fastclk" TNM_NET = "fastclk" ;
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 4 ns ;
TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 4 ns ;
 
# Board clock
NET "clk" LOC = "aa12" | IOSTANDARD = LVTTL;
 
# Note: LEDs use inverted logic
NET "led(0)" LOC = "f11" | IOSTANDARD = LVTTL;
NET "led(1)" LOC = "e11" | IOSTANDARD = LVTTL;
NET "led(2)" LOC = "d11" | IOSTANDARD = LVTTL;
NET "led(3)" LOC = "c11" | IOSTANDARD = LVTTL;
 
NET "btn_reset" LOC = "D19" | IOSTANDARD = LVTTL;
NET "btn_clear" LOC = "D21" | IOSTANDARD = LVTTL;
 
NET "switch(0)" LOC = "f16" | IOSTANDARD = LVTTL;
NET "switch(1)" LOC = "f13" | IOSTANDARD = LVTTL;
NET "switch(2)" LOC = "f12" | IOSTANDARD = LVTTL;
NET "switch(3)" LOC = "e16" | IOSTANDARD = LVTTL;
NET "switch(4)" LOC = "c22" | IOSTANDARD = LVTTL;
NET "switch(5)" LOC = "c20" | IOSTANDARD = LVTTL;
NET "switch(6)" LOC = "c21" | IOSTANDARD = LVTTL;
NET "switch(7)" LOC = "d20" | IOSTANDARD = LVTTL;
 
NET "spw_rxdp" LOC = "m1";# | IOSTANDARD = LVDS_25;
NET "spw_rxdn" LOC = "m2";# | IOSTANDARD = LVDS_25;
NET "spw_rxsp" LOC = "m3";# | IOSTANDARD = LVDS_25;
NET "spw_rxsn" LOC = "m4";# | IOSTANDARD = LVDS_25;
NET "spw_txdp" LOC = "n1";# | IOSTANDARD = LVDS_25;
NET "spw_txdn" LOC = "n2";# | IOSTANDARD = LVDS_25;
NET "spw_txsp" LOC = "n3";# | IOSTANDARD = LVDS_25;
NET "spw_txsn" LOC = "n4";# | IOSTANDARD = LVDS_25;
 
CONFIG PROHIBIT = "aa14"; #"fpgadata"
CONFIG PROHIBIT = "w12"; #"fpgainit"
 
/streamtest_gr-xc3s1500/Makefile
0,0 → 1,298
 
###############################################################################
## ##
## project-dependent variables ##
## ##
###############################################################################
 
# The project name. The bit-file that is generated in the end will be named
# "$(PROJ).bit"
 
PROJ = streamtest
 
# The top-level entity to be instantiated
 
TOPLEVEL = streamtest_top
 
# The VHDL sources that need to be compiled during synthesis
 
RTLDIR = ../../rtl/vhdl
VHDL_SOURCES = streamtest_top.vhd \
$(RTLDIR)/streamtest.vhd \
$(RTLDIR)/spwpkg.vhd \
$(RTLDIR)/spwstream.vhd \
$(RTLDIR)/spwlink.vhd \
$(RTLDIR)/spwram.vhd \
$(RTLDIR)/spwrecv.vhd \
$(RTLDIR)/spwxmit.vhd \
$(RTLDIR)/spwxmit_fast.vhd \
$(RTLDIR)/spwrecvfront_generic.vhd \
$(RTLDIR)/spwrecvfront_fast.vhd
 
# For Pender XC3S1500 board
FPGA_TYPE = xc3s1500-fg456-4
 
## For Pender XC3S2000 rev2 board
#FPGA_TYPE = xc3s2000-fg456-4
 
# The default target; recommended targets: "bitfile" or "upload"
 
default : bitfile
 
UCFFILE = streamtest.ucf
 
###############################################################################
## ##
## miscellaneous project-independent variables & rules ##
## ##
###############################################################################
 
# use this to make most tools quieter
OPT_INTSTYLE = -intstyle ise
 
# Phony (non file creating) targets
 
.PHONY : default clean bitfile
 
clean :
$(RM) -rf *~ work dump.xst _ngo 'file graph' xlnx_auto_0_xdb
$(RM) $(PROJ).xst-script
$(RM) $(PROJ).lso $(PROJ).prj
$(RM) $(PROJ).ngc $(PROJ).xst.log $(PROJ).syr $(PROJ).srp $(PROJ).ngr
$(RM) $(PROJ).ngd $(PROJ).bld
$(RM) $(PROJ).twx $(PROJ).twr
$(RM) $(PROJ).pcf $(PROJ)_map.mrp $(PROJ)_map.ncd $(PROJ)_map.ngm
$(RM) $(PROJ).ncd $(PROJ).pad $(PROJ).par $(PROJ).xpi $(PROJ)_pad.csv $(PROJ)_pad.txt
$(RM) $(PROJ).bit $(PROJ).bgn $(PROJ).drc
$(RM) $(PROJ).ptwx $(PROJ).unroutes *.xrpt $(PROJ)_summary.xml $(PROJ)_usage.xml $(PROJ)_map.map
 
bitfile : $(PROJ).bit
 
###############################################################################
# #
# STAGE 1: "xst" (Xilinx Synthesis Tool) #
# needs: #
# #
# $(PROJ).vhdl #
# $(PROJ).prj - Project file (created below) #
# $(PROJ).lso - Library Search Order file (created below) #
# #
# created files: #
# #
# $(PROJ).ngc - netlist #
# $(PROJ).ngr - XILINX-XDB 0.1 STUB 0.1 ASCII / XILINX-XDM V1.2e #
# (optional, depending on the '-rtlview' option) #
# $(PROJ).xst.log - human-readable synthesis report #
# (AKA .syr, .srp) #
# #
# created directories: #
# #
# work #
# dump.xst #
# #
###############################################################################
 
# Generate a "Library Search Order" file, containing just "work" for now.
 
$(PROJ).lso :
@echo "work" > $@
 
# Generate a "Project" file, consisting of lines containing each of the
# VHDL_SOURCES, preceded by "vhdl work".
 
$(PROJ).prj :
$(shell echo -n $(VHDL_SOURCES) | \
sed 's/\([^ ]\+\) */vhdl work \1\n/g' > $@)
 
$(PROJ).xst-script :
@echo "set -tmpdir /tmp" > $@
@echo "set -xsthdpdir ." >> $@
@echo "run" >> $@
@echo "-ifn $(PROJ).prj" >> $@
@echo "-ifmt mixed" >> $@
@echo "-ofn $(PROJ)" >> $@
@echo "-ofmt ngc" >> $@
@echo "-p $(FPGA_TYPE)" >> $@
@echo "-top $(TOPLEVEL)" >> $@
@echo "-opt_mode speed" >> $@
@echo "-opt_level 1" >> $@
@echo "-iuc no" >> $@
@echo "-lso $(PROJ).lso" >> $@
@echo "-keep_hierarchy no" >> $@
@echo "-glob_opt AllClockNets" >> $@
@echo "-rtlview no" >> $@
@echo "-read_cores yes" >> $@
# Note: write_timing_constraints is non-standard
@echo "-write_timing_constraints yes" >> $@
@echo "-cross_clock_analysis no" >> $@
# @echo "-hierarchy_separator _" >> $@
@echo "-bus_delimiter <>" >> $@
@echo "-case maintain" >> $@
@echo "-slice_utilization_ratio 100" >> $@
# @echo "-verilog2001 yes" >> $@
# @echo "-vlgincdir" >> $@
@echo "-fsm_extract yes" >> $@
@echo "-fsm_encoding auto" >> $@
@echo "-fsm_style lut" >> $@
# Note: safe_implementation is non-standard
@echo "-safe_implementation yes" >> $@
@echo "-ram_extract yes" >> $@
@echo "-ram_style auto" >> $@
@echo "-rom_extract yes" >> $@
@echo "-rom_style auto" >> $@
@echo "-mux_extract yes" >> $@
@echo "-mux_style auto" >> $@
@echo "-decoder_extract yes" >> $@
@echo "-priority_extract yes" >> $@
@echo "-shreg_extract yes" >> $@
@echo "-shift_extract yes" >> $@
@echo "-xor_collapse yes" >> $@
@echo "-resource_sharing yes" >> $@
@echo "-mult_style auto" >> $@
@echo "-iobuf yes" >> $@
@echo "-max_fanout 500" >> $@
@echo "-bufg 8" >> $@
@echo "-register_duplication yes" >> $@
@echo "-equivalent_register_removal yes" >> $@
@echo "-register_balancing no" >> $@
@echo "-slice_packing yes" >> $@
@echo "-optimize_primitives no" >> $@
@echo "-iob auto" >> $@
 
$(PROJ).ngc $(PROJ).xst.log : $(VHDL_SOURCES) $(PROJ).prj $(PROJ).lso $(PROJ).xst-script
rm -rf work dump.xst
xst $(OPT_INTSTYLE) -ifn $(PROJ).xst-script -ofn $(PROJ).xst.log
rm -rf work dump.xst
 
###############################################################################
# #
# STAGE 2: ngdbuild #
# needs: #
# #
# $(PROJ).ngc #
# #
# created files: #
# #
# $(PROJ).bld - human-readable build log #
# $(PROJ).ngd - XILINX-XDB 0.1 STUB 0.1 ASCII / XILINX-XDM V1.2e #
# #
# created dir: #
# _ngo #
# #
###############################################################################
 
$(PROJ).ngd $(PROJ).bld: $(PROJ).ngc $(UCFFILE)
rm -rf _ngo
ngdbuild $(OPT_INTSTYLE) -dd _ngo -aul -p $(FPGA_TYPE) $(if $(UCFFILE),-uc $(UCFFILE)) $(PROJ).ngc $(PROJ).ngd
rm -rf _ngo
 
###############################################################################
# #
# STAGE 3: Mapper #
# needs: #
# #
# $(PROJ).ngd #
# #
# created files: #
# #
# $(PROJ).pcf - ASCII file #
# $(PROJ)_map.mrp - human-readable mapping report #
# $(PROJ)_map.ncd - binary format #
# $(PROJ)_map.ngm - XILINX-XDB 0.1 STUB 0.1 ASCII / XILINX-XDM V1.2e #
# #
# NOTE: #
# #
# In order to prevent the make process from terminating on these spurious #
# problems, we precede the "map" invocation with a hyphen, instructing #
# make to ignore the return code from "map". #
# #
###############################################################################
 
$(PROJ).pcf $(PROJ)_map.mrp $(PROJ)_map.ncd $(PROJ)_map.ngm: $(PROJ).ngd
map $(OPT_INTSTYLE) -p $(FPGA_TYPE) -cm area -pr b -c 100 -o $(PROJ)_map.ncd $(PROJ).ngd $(PROJ).pcf
 
###############################################################################
# #
# STAGE 4: Place-and-Route #
# needs: #
# #
# $(PROJ).pcf #
# $(PROJ)_map.ncd #
# #
# created files: #
# #
# $(PROJ).ncd - binary file #
# $(PROJ).pad - ASCII file for import in spreadsheet #
# $(PROJ).par - human-readable place-and-route report #
# $(PROJ).xpi - ASCII file #
# $(PROJ)_pad.csv - human-readable CVS file #
# $(PROJ)_pad.txt - human-readable file #
# #
###############################################################################
 
$(PROJ).ncd $(PROJ).pad $(PROJ).par $(PROJ).xpi $(PROJ)_pad.csv $(PROJ)_pad.txt: $(PROJ).pcf $(PROJ)_map.ncd
par -w $(OPT_INTSTYLE) -t 1 $(PROJ)_map.ncd $(PROJ).ncd $(PROJ).pcf
 
###############################################################################
# #
# STAGE 4.5 (optional): trace #
# needs: #
# #
# created files: #
# #
###############################################################################
 
$(PROJ).twr $(PROJ).twx : $(PROJ).ncd $(PROJ).pcf
trce $(OPT_INTSTYLE) -e 5 -l 5 -u 5 -xml $(PROJ) $(PROJ).ncd -o $(PROJ).twr $(PROJ).pcf
 
###############################################################################
# #
# STAGE 5: Generate BIT-file #
# needs: #
# #
# $(PROJ).ncd #
# #
# created files: $(PROJ).bgn $(PROJ).bit $(PROJ).drc #
# #
# $(PROJ).bgn - human-readable BitGen report #
# $(PROJ).drc - human readable DRC report #
# $(PROJ).bit - binary image file #
# #
###############################################################################
 
# We omit "-g StartUpClk:JtagClk" ; this doesn't work if the image is loaded
# from a PROM.
 
# Note: LCK_cycle:3 is non-standard
OPT_BITGEN = -w \
-g DebugBitstream:No \
-g Binary:no \
-g CRC:Enable \
-g ConfigRate:6 \
-g CclkPin:PullUp \
-g M0Pin:PullUp \
-g M1Pin:PullUp \
-g M2Pin:PullUp \
-g ProgPin:PullUp \
-g DonePin:PullUp \
-g TckPin:PullUp \
-g TdiPin:PullUp \
-g TdoPin:PullUp \
-g TmsPin:PullUp \
-g UnusedPin:PullDown \
-g UserID:0xFFFFFFFF \
-g DCMShutDown:Disable \
-g DONE_cycle:4 \
-g GTS_cycle:5 \
-g GWE_cycle:6 \
-g LCK_cycle:3 \
-g Match_cycle:Auto \
-g Security:None \
-g DonePipe:No \
-g DriveDone:No
 
$(PROJ).bit $(PROJ).bgn $(PROJ).drc: $(PROJ).ncd
bitgen $(OPT_INTSTYLE) $(OPT_BITGEN) $(PROJ).ncd
 
###############################################################################
 
/streamtest_gr-xc3s1500/streamtest_top.vhd
0,0 → 1,259
--
-- Test of spwstream on Pender GR-XC3S-1500 board.
-- 60 MHz system clock; 200 MHz receive clock and transmit clock.
--
-- LED 0 = link run
-- LED 1 = link error (sticky until clear button)
-- LED 2 = gotdata
-- LED 3 = data/timecode error (sticky until reset)
--
-- Button S2 = reset
-- Button S3 = clear LED 1
--
-- Switch 0 = link start
-- Switch 1 = link disable
-- Switch 2 = send data
-- Switch 3 = send time codes
-- Switch 4-7 = bits 0-3 of tx bit rate scale factor
--
-- SpaceWire signals on expansion connector J12:
-- Data In pos,neg = m1,m2 = pin 3,2
-- Strobe In pos,neg = m3,m4 = pin 6,5
-- Data Out pos,neg = n1,n2 = pin 9,8
-- Strobe Out pos,neg = n3,n4 = pin 12,11
--
-- To get proper LVDS signals from connector J12, the voltage on I/O bank 6
-- must be set to 2.5V. This is the default on GR-XC3S-1500-rev2, but on
-- GR-XC3S-1500-rev1 a change is required on the board (described in
-- the board manual).
--
-- To terminate the incoming LVDS signals, 100 Ohm termination resistors
-- must be installed on the board in positions R120 and R121.
--
-- The SpaceWire port should be looped back to itself, either directly
-- or via an other SpaceWire device. For a direct loopback, place 4 wires
-- from the output pins to the corresponding input pins. For an indirect
-- loopback, connect the SpaceWire signals to an additional SpaceWire device
-- which is programmed to echo everything it receives (characters, packets,
-- time codes). See the datasheet for a wiring diagram from J12 to MDM9.
--
 
library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
use work.spwpkg.all;
 
entity streamtest_top is
 
port (
clk: in std_logic;
btn_reset: in std_logic;
btn_clear: in std_logic;
switch: in std_logic_vector(7 downto 0);
led: out std_logic_vector(3 downto 0);
spw_rxdp: in std_logic;
spw_rxdn: in std_logic;
spw_rxsp: in std_logic;
spw_rxsn: in std_logic;
spw_txdp: out std_logic;
spw_txdn: out std_logic;
spw_txsp: out std_logic;
spw_txsn: out std_logic );
 
end entity streamtest_top;
 
architecture streamtest_top_arch of streamtest_top is
 
-- Clock generation.
signal boardclk: std_logic;
signal sysclk: std_logic;
signal fastclk: std_logic;
 
-- Synchronize buttons
signal s_resetbtn: std_logic := '0';
signal s_clearbtn: std_logic := '0';
 
-- Sticky LED
signal s_linkerrorled: std_logic := '0';
 
-- Interface signals.
signal s_rst: std_logic := '1';
signal s_linkstart: std_logic := '0';
signal s_autostart: std_logic := '0';
signal s_linkdisable: std_logic := '0';
signal s_senddata: std_logic := '0';
signal s_sendtick: std_logic := '0';
signal s_txdivcnt: std_logic_vector(7 downto 0) := "00000000";
signal s_linkstarted: std_logic;
signal s_linkconnecting: std_logic;
signal s_linkrun: std_logic;
signal s_linkerror: std_logic;
signal s_gotdata: std_logic;
signal s_dataerror: std_logic;
signal s_tickerror: std_logic;
signal s_spwdi: std_logic;
signal s_spwsi: std_logic;
signal s_spwdo: std_logic;
signal s_spwso: std_logic;
 
-- Make clock nets visible to UCF file.
attribute KEEP: string;
attribute KEEP of sysclk: signal is "SOFT";
attribute KEEP of fastclk: signal is "SOFT";
 
component streamtest is
generic (
sysfreq: real;
txclkfreq: real;
tickdiv: integer range 12 to 24 := 20;
rximpl: spw_implementation_type := impl_generic;
rxchunk: integer range 1 to 4 := 1;
tximpl: spw_implementation_type := impl_generic;
rxfifosize_bits: integer range 6 to 14 := 11;
txfifosize_bits: integer range 2 to 14 := 11 );
port (
clk: in std_logic;
rxclk: in std_logic;
txclk: in std_logic;
rst: in std_logic;
linkstart: in std_logic;
autostart: in std_logic;
linkdisable: in std_logic;
senddata: in std_logic;
sendtick: in std_logic;
txdivcnt: in std_logic_vector(7 downto 0);
linkstarted: out std_logic;
linkconnecting: out std_logic;
linkrun: out std_logic;
linkerror: out std_logic;
gotdata: out std_logic;
dataerror: out std_logic;
tickerror: out std_logic;
spw_di: in std_logic;
spw_si: in std_logic;
spw_do: out std_logic;
spw_so: out std_logic );
end component;
 
begin
 
-- Buffer incoming clock.
bufg0: BUFG port map ( I => clk, O => boardclk );
 
-- Generate 60 MHz system clock.
dcm0: DCM
generic map (
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 6,
CLK_FEEDBACK => "NONE",
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
STARTUP_WAIT => true )
port map (
CLKIN => boardclk,
RST => '0',
CLKFX => sysclk );
 
-- Generate 200 MHz fast clock.
dcm1: DCM
generic map (
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLK_FEEDBACK => "NONE",
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
STARTUP_WAIT => true )
port map (
CLKIN => boardclk,
RST => '0',
CLKFX => fastclk );
 
-- Streamtest instance
streamtest_inst: streamtest
generic map (
sysfreq => 60.0e6,
txclkfreq => 200.0e6,
tickdiv => 22,
rximpl => impl_fast,
rxchunk => 4,
tximpl => impl_fast,
rxfifosize_bits => 11,
txfifosize_bits => 10 )
port map (
clk => sysclk,
rxclk => fastclk,
txclk => fastclk,
rst => s_rst,
linkstart => s_linkstart,
autostart => s_autostart,
linkdisable => s_linkdisable,
senddata => s_senddata,
sendtick => s_sendtick,
txdivcnt => s_txdivcnt,
linkstarted => s_linkstarted,
linkconnecting => s_linkconnecting,
linkrun => s_linkrun,
linkerror => s_linkerror,
gotdata => s_gotdata,
dataerror => s_dataerror,
tickerror => s_tickerror,
spw_di => s_spwdi,
spw_si => s_spwsi,
spw_do => s_spwdo,
spw_so => s_spwso );
 
-- LVDS buffers
spwdi_pad: IBUFDS
generic map ( IOSTANDARD => "LVDS_25" )
port map ( O => s_spwdi, I => spw_rxdp, IB => spw_rxdn );
spwsi_pad: IBUFDS
generic map ( IOSTANDARD => "LVDS_25" )
port map ( O => s_spwsi, I => spw_rxsp, IB => spw_rxsn );
spwdo_pad: OBUFDS
generic map ( IOSTANDARD => "LVDS_25" )
port map ( O => spw_txdp, OB => spw_txdn, I => s_spwdo );
spwso_pad: OBUFDS
generic map ( IOSTANDARD => "LVDS_25" )
port map ( O => spw_txsp, OB => spw_txsn, I => s_spwso );
 
process (sysclk) is
begin
if rising_edge(sysclk) then
 
-- Synchronize buttons
s_resetbtn <= btn_reset;
s_rst <= s_resetbtn;
s_clearbtn <= btn_clear;
 
-- Synchronize switch settings
s_autostart <= '0';
s_linkstart <= switch(0);
s_linkdisable <= switch(1);
s_senddata <= switch(2);
s_sendtick <= switch(3);
s_txdivcnt(3 downto 0) <= switch(7 downto 4);
 
-- Sticky link error LED
s_linkerrorled <= (s_linkerrorled or s_linkerror) and
(not s_clearbtn) and
(not s_resetbtn);
 
-- Drive LEDs (inverted logic)
led(0) <= not s_linkrun;
led(1) <= not s_linkerrorled;
led(2) <= not s_gotdata;
led(3) <= not (s_dataerror or s_tickerror);
 
end if;
end process;
 
end architecture streamtest_top_arch;
/streamtest_digilent-xc3s200/streamtest_top.vhd
1,5 → 1,6
--
-- Test of spwstream on Digilent XC3S200 board.
-- 60 MHz system clock, 200 MHz receive clock and transmit clock.
--
-- LED 0 = link started
-- LED 1 = link connecting
98,6 → 99,7
component streamtest is
generic (
sysfreq: real;
txclkfreq: real;
tickdiv: integer range 12 to 24 := 20;
rximpl: spw_implementation_type := impl_generic;
rxchunk: integer range 1 to 4 := 1;
173,6 → 175,7
streamtest_inst: streamtest
generic map (
sysfreq => 60.0e6,
txclkfreq => 200.0e6,
tickdiv => 22,
rximpl => impl_fast,
rxchunk => 4,

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