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URL https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk

Subversion Repositories spacewire_light

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  • This comparison shows the changes necessary to convert path 
    /spacewire_light/trunk/rtl/vhdl
    from Rev 5 to Rev 6
    ↔ Reverse comparison
  •

Rev 5 → Rev 6

/spwahbmst.vhd
335,7 → 335,7
v.mstate := st_rxfinal;
end if;
-- Stop at max burst length boundary.
if (andv(r.rxaddr(maxburst+2 downto 2)) = '1') then
if (andv(r.rxaddr(maxburst+1 downto 2)) = '1') then
v_burstreq := '0';
v.mstate := st_rxfinal;
end if;
438,7 → 438,7
v.txdes_len := std_logic_vector(unsigned(r.txdes_len) - 4);
v.txaddr := std_logic_vector(unsigned(r.txaddr) + 1);
-- Handle end of burst/transfer.
if andv(r.txaddr(maxburst+2 downto 2)) = '1' then
if andv(r.txaddr(maxburst+1 downto 2)) = '1' then
-- This was the last data cycle before the max burst boundary.
-- Go through st_idle to pick up more work.
v_burstreq := '0';
451,12 → 451,12
-- Stop at end of requested length (one more data cycle).
v_burstreq := '0';
v.mstate := st_txfinal;
elsif andv(r.txaddr(maxburst+2 downto 3)) = '1' then
elsif andv(r.txaddr(maxburst+1 downto 3)) = '1' then
-- Stop at max burst length boundary (one more data cycle).
v_burstreq := '0';
end if;
else
if andv(r.txaddr(maxburst+2 downto 2)) = '1' then
if andv(r.txaddr(maxburst+1 downto 2)) = '1' then
-- Stop at max burst length boundary (just one more data cycle).
v_burstreq := '0';
end if;
597,7 → 597,7
v.hbusreq := '1';
if ahbi.hready = '1' then
-- Increment address and continue burst in bs_active.
v.haddr := std_logic_vector(unsigned(r.haddr) + 1);
v.haddr(maxburst+1 downto 2) := std_logic_vector(unsigned(r.haddr(maxburst+1 downto 2)) + 1);
v.burststat := bs_active;
-- Stop burst when application ends the transfer.
v.hbusreq := v_burstreq;
616,7 → 616,7
v.hbusreq := '1';
if ahbi.hresp /= HRESP_OKAY then
-- Error response from slave.
v.haddr := std_logic_vector(unsigned(r.haddr) - 1);
v.haddr(maxburst+1 downto 2) := std_logic_vector(unsigned(r.haddr(maxburst+1 downto 2)) - 1);
if ahbi.hresp = HRESP_ERROR then
-- Permanent error.
v.ahberror := '1';
628,7 → 628,7
v.burststat := bs_idle;
elsif ahbi.hready = '1' then
-- Increment address.
v.haddr := std_logic_vector(unsigned(r.haddr) + 1);
v.haddr(maxburst+1 downto 2) := std_logic_vector(unsigned(r.haddr(maxburst+1 downto 2)) + 1);
-- Stop burst when application ends the transfer.
v.hbusreq := v_burstreq;
if v_burstreq = '0' then
646,7 → 646,7
v.hbusreq := r.hbusreq or v_burstreq;
if ahbi.hresp /= HRESP_OKAY then
-- Error response from slave.
v.haddr := std_logic_vector(unsigned(r.haddr) - 1);
v.haddr(maxburst+1 downto 2) := std_logic_vector(unsigned(r.haddr(maxburst+1 downto 2)) - 1);
if ahbi.hresp = HRESP_ERROR then
-- Permanent error.
v.ahberror := '1';
/spwamba.vhd
310,15 → 310,16
signal recv_inact: std_logic;
signal recv_inbvalid: std_logic;
signal recv_inbits: std_logic_vector(rxchunk-1 downto 0);
signal xmit_rst: std_logic;
signal xmiti: spw_xmit_in_type;
signal xmito: spw_xmit_out_type;
signal xmit_divcnt: std_logic_vector(7 downto 0);
signal link_rst: std_logic;
signal linki: spw_link_in_type;
signal linko: spw_link_out_type;
signal msti: spw_ahbmst_in_type;
signal msto: spw_ahbmst_out_type;
signal ahbmst_rstn: std_logic;
signal s_rst: std_logic;
 
-- Memory interface signals.
signal s_rxfifo_raddr: std_logic_vector(rxfifosize-1 downto 0);
352,7 → 353,7
reset_time => reset_time )
port map (
clk => clk,
rst => s_rst,
rst => link_rst,
linki => linki,
linko => linko,
rxen => recv_rxen,
405,7 → 406,7
xmit_inst: spwxmit
port map (
clk => clk,
rst => s_rst,
rst => xmit_rst,
divcnt => xmit_divcnt,
xmiti => xmiti,
xmito => xmito,
417,7 → 418,7
port map (
clk => clk,
txclk => txclk,
rst => s_rst,
rst => xmit_rst,
divcnt => xmit_divcnt,
xmiti => xmiti,
xmito => xmito,
596,7 → 597,10
v.rxroom := "111111";
else
-- less than 64 bytes room.
v.rxroom := std_logic_vector(v_tmprxroom(5 downto 0));
-- If linko.rxchar = '1', decrease rxroom by one to account for
-- the pipeline delay through r.rxfifo_write.
v.rxroom := std_logic_vector(v_tmprxroom(5 downto 0) -
to_unsigned(conv_integer(linko.rxchar), 6));
end if;
 
-- Update TX fifo write pointer.
616,10 → 620,19
v.txfifo_nxfull := msto.txfifo_write;
end if;
 
-- Detect TX fifo more than 3/4 full.
if unsigned(r.txfifo_raddr) - unsigned(r.txfifo_waddr) = to_unsigned(2**(txfifosize-2), txfifosize) then
-- currently exactly 3/4 full.
v.txfifo_highw := msto.txfifo_write;
-- Detect TX fifo high water mark.
if txfifosize > maxburst then
-- Indicate high water when there is no room for a maximum burst.
if unsigned(r.txfifo_raddr) - unsigned(r.txfifo_waddr) = to_unsigned(2**maxburst + 1, txfifosize) then
-- currently room for exactly one maximum burst.
v.txfifo_highw := msto.txfifo_write;
end if;
else
-- Indicate high water when more than half full.
if unsigned(r.txfifo_raddr) - unsigned(r.txfifo_waddr) = to_unsigned(2**(txfifosize-1), txfifosize) then
-- currently exactly half full.
v.txfifo_highw := msto.txfifo_write;
end if;
end if;
 
-- Update descriptor pointers.
827,7 → 840,8
 
-- Reset components.
ahbmst_rstn <= rstn and (not r.ctl_reset) and (not r.ctl_resetdma);
s_rst <= (not rstn) or r.ctl_reset;
link_rst <= (not rstn) or r.ctl_reset;
xmit_rst <= not rstn;
 
-- Clear TX fifo on cancel request.
if r.ctl_txcancel = '1' then
/streamtest.vhd
4,7 → 4,7
-- This entity implements one spwstream instance with SpaceWire signals
-- routed to external ports. The SpaceWire port is assumed to be looped back
-- to itself externally, either directly (tx pins wired to rx pins) or
-- through a foreigh SpaceWire device which is programmed to echo anything
-- through a remote SpaceWire device which is programmed to echo anything
-- it receives.
--
-- This entity submits a series of test patterns to the transmit side of

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