URL
https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk
Subversion Repositories spacewire_light
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/spacewire_light/trunk/syn/streamtest_gr-xc3s1500
- from Rev 3 to Rev 5
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Rev 3 → Rev 5
/streamtest.ucf
5,11 → 5,14
TIMESPEC "TS_clk" = PERIOD "clk" 18.0 ns ; |
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# Paths between fastclk and sysclk must be constrained to fastclk period. |
# fastclk = 200 MHz = 5 ns nominal, - 1 ns margin = 4 ns |
# fastclk = 200 MHz = 5 ns nominal |
# 3 ns data path + 1 ns source skew + 1 ns destination skew = 5 ns |
NET "sysclk" TNM_NET = "sysclk" ; |
NET "fastclk" TNM_NET = "fastclk" ; |
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 4 ns ; |
TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 4 ns ; |
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 3 ns DATAPATHONLY ; |
TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 3 ns DATAPATHONLY ; |
NET "sysclk" MAXSKEW = 1 ns ; |
NET "fastclk" MAXSKEW = 1 ns ; |
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# Board clock |
NET "clk" LOC = "aa12" | IOSTANDARD = LVTTL; |